JPH03283176A - Ferroelectric substance memory - Google Patents

Abstract

PURPOSE:To attain the polarization and inversion of a ferroelectric substance by connecting a means giving one of two potentials to a first electrode and connecting a means holding the intermediate potential between two potentials to a second electrode. CONSTITUTION:Ferroelectric substance memory cells consisting of ferroelectric substance capacitor and transistor are respectively connected to the cross parts of bit lines BL1, the inverse of BL1...BLn, the inverse of BLn and word lines WL1...WLm. Dummy cells consisting of reference ferroelectric substance capacitor and the transistor are respectively connected to the cross parts of the bit lines BL1, the inverse of BL1...BLn and the inverse of BLn and dummy word lines DWL and DWL'. Consequently, the dummy cell connected to the other bit line (the inverse of BL1, for example) is selected for the memory cell connected to one bit line (BL1, for example) by selecting the word line WL1 and one dummy word line DWL. Thus, the ferroelectric substance can be polarized and inverted.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a ferroelectric memory.

(Prior Art) Ferroelectric memory has attracted attention in recent years due to its high integration, high speed, and nonvolatility. This is intended to reverse the spontaneous polarization of a ferroelectric material by an externally applied electric field, and to store one bit of information depending on the direction of the polarization.

A ferroelectric material has a hysteresis characteristic as shown in FIG. 26 between the applied voltage and the spontaneous polarization generated inside.

When voltage VM is applied to a ferroelectric material, polarization shown at point A occurs. Gradually lower the voltage applied to the ferroelectric material,
Even when it finally reaches Ov, the polarization shown at point B remains. Furthermore, when a reverse voltage is applied, polarization shown at the 0 point occurs at voltage -■2, and as this voltage is increased, when it reaches OV, the polarization shown at point D remains in the ferroelectric material. . In this way, in a ferroelectric material, the polarization that remains in the ferroelectric material when the externally applied voltage is OV, that is, the residual polarization, differs between point B and 0.
We will have two states of points. To read this, for example, when a voltage vM is applied externally, only a current corresponding to (A-B) flows for the one at point B, but the current corresponding to (A-D) flows for the one at point D. A large current corresponding to the current will flow, and it will be possible to distinguish whether the current was at point B or point D. The principle of ferroelectric memory is to make these two states correspond to one bit of information.

As mentioned above, in order to use it as a ferroelectric memory, it is necessary to arbitrarily invert the polarization of the ferroelectric material during writing and reading. However, in order to reverse the polarization of the ferroelectric material, the vertical relationship of the potentials of a pair of electrodes sandwiching the ferroelectric material must be reversed. That is, as shown in FIG. 27, of the pair of electrodes 12 and 13 sandwiching the ferroelectric material 11, the first electrode 12 is at L level, the second electrode 13 is at H level,
Or in order to realize the opposite state, the picture electrode 12
．． 13 must be applied with a potential of L1H level. For example, J.T. EVANS et al.
JOURNAL 0FSOLID-8TATE CIR
CUITS VOL, 23. An in No51988
Experimental 512bitNonvo
Latli Memory with Ferroele
Ferroelectric memory in which one electrode of the ferroelectric is connected to the bit line via a FET, and the other electrode is connected to each sense amplifier and dry line driver as a drive line, as shown in "ctric Storage Ce1l". is known. In this ferroelectric memory, the direction of polarization of the ferroelectric material can be adjusted according to the vertical relationship between the potentials of the bit line and the drive line. However, in this configuration, the number of drives is the same as that of word lines. There is a problem that not only a line is required, but also the peripheral circuitry becomes complicated accordingly.

On the other hand, in conventional dynamic random access memory (DRAM) using capacitors, one bit of information is recorded depending on whether or not charge is stored in the capacitor.
By setting only one electrode of the capacitor to an L or H level potential, and fixing the other electrode to one of the potentials, charge will be stored when a potential difference occurs.
When the potential is equal, it is possible to create a state where it cannot be stored.

That is, in the conventional DRAM using capacitors, one of the electrodes of the capacitors of all memory cells can be made common, and wiring is simple.

In this way, in a ferroelectric memory, in order to reverse the polarization direction, it is necessary to connect both of the ferroelectric electrodes of the memory cell to, for example, a driver so that their potential relationships can be independently reversed. For this reason, the wiring is
The problem arises that it is more complicated than M. To avoid this, the above-mentioned literature describes a ferroelectric memory in which memory cells connected to the same word line are sandwiched between ferroelectric materials, and the unconnected electrodes of the FETs are shared. ing. However, because it uses a method in which memory cells that are polarized in one direction are polarized once and then memory cells that are polarized in the opposite direction are polarized, the writing time is twice as long as that of conventional DRAMs. . Moreover, the number of common lines must be equal to the number of word lines. In addition, it is known that polarization reversal of ferroelectric materials takes a certain amount of time, and in the ferroelectric memory, the time from when a memory cell is selected to when data is finalized, that is, the access time, becomes long. There is a problem. Furthermore, in ferroelectric materials, a fatigue phenomenon (wear-out) has been observed in which the amount of spontaneous polarization decreases as polarization reversals are repeated, and there is a problem in that the number of rewrites is limited.

(Problems to be Solved by the Invention) The present invention was made to solve the above-mentioned conventional problems, and it is possible to perform polarization inversion of a ferroelectric material with a structure similar to that of a conventional DRAM, and furthermore, Access time is short,
The aim is to provide a long-life ferroelectric memory.

[Structure of the Invention (Means for Solving the Problem) A ferroelectric memory according to the present invention is a ferroelectric memory that records one bit of information by polarization of a ferroelectric. Among the electrodes, 1 is placed on the first electrode.
A means for applying one of two potentials corresponding to binary writing of bit information is connected, and the second electrode is held at an intermediate or approximately intermediate potential between the two potentials corresponding to binary writing. It is characterized in that the means are connected.

Further, in another ferroelectric memory according to the present invention, in which one bit of information is recorded by polarization of a ferroelectric material, a first electrode of a pair of electrodes sandwiching the ferroelectric material is provided. 2 corresponding to binary writing of 1-bit information
A means for applying one of two potentials is connected to the second electrode, and the second electrode is held at an intermediate or approximately intermediate potential between the two potentials corresponding to the binary writing, or This is characterized in that means for applying one of two potentials is connected.

As the ferroelectric material, for example, lead zirconate titanate (
PZT), etc.

Examples of the electrode include aluminum, polycrystalline silicon, metal silicide, tungsten, platinum, and gold.

The potential applied to the first and second electrodes may be not only a positive potential but also a negative potential.

(Function) According to the present invention, the structure is similar to that of conventional DRAM, that is, the second electrode of the electrodes sandwiching the ferroelectric material can be made common to all memory cells, so wiring and control circuits can be simplified. can be converted into This can improve the degree of integration of memory cells, and is more advantageous as the number of memory cells increases.

Furthermore, according to another ferroelectric memory according to the present invention, by adding means for making the potential of the second electrode equal to one corresponding to binary writing while power is applied, the first and second Since the vertical relationship between the electrodes does not change, the polarization direction does not change, but when the picture electrodes are the same, charge is not stored, and when they are different, charge is stored.This is a small capacitor area that takes advantage of the large dielectric constant of ferroelectric material. It can be operated as a DRAM with sufficient S/N ratio. In this case, since the polarization direction of the ferroelectric is not reversed, it is possible to avoid delays in access time due to polarization reversal and limitations on life due to fatigue of the ferroelectric. Also in this case, since it has the same structure as a conventional DRAM, refresh operations, reading, writing, etc. can all be realized with the same circuit as a DRAM. Before turning off the power, after performing a refresh operation,
If the potential of the second electrode is set between two potentials corresponding to binary writing, the polarization of the ferroelectric material changes according to the retained data, and information can be stored in a nonvolatile state.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Example 1 FIG. 1 is a circuit diagram of a ferroelectric memory according to Example 1. This memory includes a plurality of bit line pairs BL extending in the column direction.
, BL, ... BL, , BL, word lines WL, ... WL extending in the row direction, and a pair of dummy word lines DWLSDWL'. The bit line BL+
BLt -BL, , BL- and the word line WL, .
A ferroelectric memory cell consisting of one ferroelectric capacitor and one transistor is connected to the intersection of the bit lines BL+ and BLt -BL, respectively.
Dummy cells each consisting of one reference paraelectric capacitor and one transistor are connected to the intersections of -, BL- and the dummy word lines DWL, DWL'. The word line WL and one dummy word line D
By selecting WL, a dummy cell connected to the other bit line (eg B L I ) is selected for a memory cell connected to the one bit line (eg BL). For simplicity, the bit lines BL,
Two memory cells connected to the intersection of BL and the word lines WL1 and WL2, bit lines BL, BL, -
The explanation will be centered on a pair of dummy cells connected to the intersection of the dummy word lines DWL and DWL'.

A memory cell connected to the intersection of one bit line BL and word line WL is composed of a ferroelectric capacitor MC and a switching transistor MF. This ferroelectric capacitor MC has a structure in which a ferroelectric layer made of lead zirconate titanate formed by, for example, a sputtering method is sandwiched between first and second electrodes made of, for example, platinum. A first electrode of the capacitor MC is connected to one bit line BL via the switching transistor MF. A second electrode of the capacitor MC is connected to a plate line PL.

Here, VssSH level is vCc as L level.
was selected, and the plate line PL was set to 1/2 VCC potential. Further, there are various ways to apply the potential, such as supplying it from the outside or creating it internally, but in this embodiment 1 (the same applies to the following embodiments), it was obtained by dividing the voltage using a resistor.

The gate of the switching transistor MF is connected to the word line WL1. The memory cell connected to the intersection of the other bit line BL and word line WL2 is a ferroelectric capacitor M having the same structure as described above.
C' and a switching transistor MF'. The first electrode of the capacitor MC' is
It is connected to the other bit line BL via the switching transistor MF'.

A second electrode of the capacitor MC' is connected to the plate line PL. The gate of the switching transistor MF' is connected to the word line WL2.

The one bit line BL and the other dummy word line DW
The dummy cell connected to the intersection of L' is a reference paraelectric capacitor DC and a switching transistor DF.
It is composed of. This paraelectric capacitor DC has a paraelectric layer having a capacity through which a current flows between the cases where the polarization of the ferroelectric capacitor MC is not reversed and the case where the polarization is not reversed.The paraelectric layer is sandwiched between first and second electrodes made of, for example, platinum. Has a structure.

A first electrode of the capacitor DC is connected to one bit line BL via the switching transistor DF. A second electrode of the capacitor DC is connected to the plate line PL. The gate of the switching transistor DF is connected to the other dummy word line DW.
Connected to L'. In addition, the other bit line BL,
The dummy cell connected to the intersection of the dummy word line DWL and one dummy word line DWL is composed of a paraelectric capacitor DC' and a switching transistor DF' having the same structure as described above. The first electrode of the capacitor DC' is connected to the other bit line BL via the switching transistor DF'. A second electrode of the capacitor MC' is connected to the plate line PL. The gate of the switching transistor DF' is connected to the negative dummy word line DWL. In a ferroelectric memory having such memory cells and dummy cells, the peripheral circuits required for write, hold, and read operations are almost the same as in conventional dynamic random access memories (DRAMs).

That is, the word lines WL1 and WL2 are connected to the row decoder/word line driver 1, and each of the dummy word lines D
WL1DWL' is connected to dummy word line decoder/driver 2.

The bit line pair BL, BL is set to a first equalizing circuit 3 that sets the bit line pair BL, BL to a precharge potential Vp (at the time of reading), and the bit line pair BL, BL, is set to a capacitor MC after writing.

Same as the second electrode of MC'! /2Vcc and is connected to a second equalization circuit 4 that cancels the charge of the memory cell. The first equalize circuit 3 is operated by a first clock signal φ1. Note that the precharge potential VPC from the first equalization circuit 3 is V(((and V,
It is possible to select the potential of The second equalize circuit 4 is operated by a second clock signal φ2. Further, the bit line pair BL, BL is connected to the sense amplifier signal φACT S9! ' It is connected to the sense amplifier 5 operated by ACT. Furthermore, the bit line pair B
L, BL are column selection switching transistors CF, 1, CF+b and data input/output lines I10, I
It is connected to a data input/output line (not shown) via lo. the column selection switching transistor CF;
, CF, , are connected to a column decoder/column select line driver 6 via a column select line C3L.

[Write Mode] The write operation and timing in the ferroelectric memory of the first embodiment described above will be explained with reference to FIG.

Conventional dynamic random access memory (DRAM)
), a write cycle is started by setting the write signal WE to the L level before lowering the chip enable σT to the L level. Chip enable C
It is assumed that the memory address and write data DIN from a data input/output unit (not shown) are determined before E is lowered to the L level. When a chip is not selected, the second equalize circuit 4 is operated with the second clock signal φ2 set to VCC, and the bit line pair BL, ,BL, is set to 1/2.
Precharged and equalized to V and c.

When the second clock signal φ2 is set to VSll, the precharge and equalization of the bit line pair BL, BL are canceled. At this time, the data input/output lines I10 and Ilo have a signal of VS according to the write data DIN from the data input/output section.
It is determined to be S or VCC.

Thereafter, the row decoder/word line driver 1 is operated according to the address signal designation, and the selected word line WL,
from VSS to vcc. At this time, word line W
The switching transistor M of the memory cell connected to L.
F is turned on and one bit line BL and plate line P
A voltage is applied to the ferroelectric capacitor MC between L,
Since one bit line BL is maintained in a floating state at 1/2 V cc, which is the same potential as the plate line PL, the polarization of the ferroelectric capacitor MC does not change.

On the other hand, when the column decoder/column select line driver 6 is operated according to the address signal specification and the selected column select line C5LI is pulled up from VSS to VCC,
Column selection switching transistors CF, , CF
+b is turned on, the data input/output lines I10, Ilo and the bit line pair BL, BL are connected, respectively, and the potential of the data input/output lines I10, Ilo (V ss or V cc
) and bit line pair BL, BL become equal in potential.

Due to such an operation, a potential difference is generated between the bit line pair BL, BL, and the plate line PL having a potential of 1/2VCC, which is connected to the word line WL and increases the strength of the memory cell to which the potential difference is applied. Dielectric capacitor M
C is polarized depending on the data to be written. After writing, column select line C8L is set to V((from vs
s, column selection switching transistor C
F, CF, , turns off and bit line pair BL, , BL,
is disconnected from data input/output lines I10 and Ilo. At the same time, the second clock signal φ2 is changed from VSS to VCC to equalize the bit line pair BL, BL to 1/2Vcc.

This reduces the potential of both picture electrodes of the memory cell to 1/2.
Since the voltage becomes Vcc, the charge accumulated during writing is canceled. However, since the potential difference is 0, the written polarization does not change. Thereafter, by changing the word line WL from VcC to VSS, the memory cell is separated from one bit line BL. The write cycle is ended by raising the chip enable CE to H level and setting the write signal WE to H level. Through this series of operations, data is written into the ferroelectric memory cell specified by the address signal and is held.

[Read Mode] The read operation and timing of data written in the write mode will be explained using FIG. 6.

In this read operation, the bit line precharge potential before reading the written data in FIG. 1 is VPC, which is the potential of the first equalization circuit 3 operated by the first clock signal φ. Here vCc
shall be.

A read cycle is started by setting write signal WE to H level when chip enable CE is lowered to L level. It is assumed that the memory address has been determined before chip enable CE is lowered to L level.

When no chip is selected, bit line pairs BL, ,B
L, is precharged and equalized to 1/2V cc by the second equalization circuit 4.

The second clock signal φ2 is set to v5. and bit line pair BL1
, BL, and at the same time, the first clock signal φ□ is raised from VSS to VCC. This causes bit line pair BL.

BL is precharged and equalized to VCC.

Here, when the first clock signal φ is lowered from VCC to V55, the bit line pair BL, BL, becomes a floating state while being maintained at the VCC level. In this state, the row decoder/word line driver l is operated according to the address signal designation, and the selected word line WL is set to VSS.
to VCC. At the same time, a dummy word line decoder/driver is installed so that a dummy cell consisting of a paraelectric capacitor DC'' and a switching transistor DF' is connected to the complementary (other) bit line BL1 of one bit line BL to which the ferroelectric memory cell is connected. 2 works.In other words, one dummy word line DWL is selected and VS2
From V. By being pulled up to C, the dummy cell is connected to the other bit line BL. Through this operation, one bit line BL+l:Vcc-plate line PLI: connected to the ferroelectric memory cell consisting of the selected ferroelectric capacitor MC and transistor MF.
l/2V (() is added.At this time, if the ferroelectric capacitor MC of the memory cell has the same polarization direction as the electric field direction, the current will flow small, and if the polarization direction is opposite, it will be polarized by this electric field. If the current is reversed, a larger current will flow.

Accordingly, in the former case, the potential drop of one bit line BL is small, and in the latter case, the potential drop of one bit line BL is large. By using a paraelectric capacitor as the dummy cell, which has a capacitance such that a current between the two flows into it and a potential drop between the two, the difference in data can be reduced by bits, similar to conventional dynamic random access memory (DRAM). It appears as a potential difference between the line pair BL, BL. If this potential difference is amplified by the same sense amplifier 5 as in a conventional dynamic random access memory (DRAM), the written data will be read out.

Specifically, by operating the sense amplifier signals φACT and NφACT to operate the sense amplifier 5 with a potential difference occurring between the bit line pair BL and SBL, the potential of the bit line with a small potential drop is raised to VCC. The potential of the bit line whose potential has decreased significantly is lowered to VSS. Due to such destructive reading, the polarization direction remains constant during reading regardless of the original data, but rewriting is performed by determining the potential by the sense amplifier 5. After determining the potential of the bit line, the column decoder/column select line driver 6 is operated according to the address signal specification, and when the selected column select line C3LI is raised from VSS to vCc, the bit line pair is changed as described above. BL and BL are connected to data input/output lines I10 and Ilo, respectively, and output data D is passed through the I10 buffer. Output to U□. The column select line C8L is set to V. By changing the voltage from 0 to VSS, the data input/output lines I10 and Ilo are separated from the bit line pair BL and BL. After operating the sense amplifier signal φACT sφAC to stop the operation of the sense amplifier 5, the second clock signal φ2 is changed from ■ss to V.
CC and bit line pair BL, BL.

Equalize to 1/2Vcc. As a result, the potential of the picture electrode of the ferroelectric memory cell is both 1/2V cc
Therefore, the charge accumulated during rewriting is canceled. However, since the potential difference is 0, the written polarization does not change. After that, the word line WL is set to VCC
to VSS to the word line WL.

The ferroelectric memory cell connected to the bit line BL.

separate from The read cycle is ended by raising chip enable CE to H level.

Note that in FIG. 6 described above, the potential VPC of the first equalization circuit 3 that precharges the bit line before reading the data written in FIG. 1 is set to VCC.
It may also be VSS. The read operation in this case will be explained below with reference to the timing chart of FIG.

The second clock signal φ2 is set to Vss, and the bit line pair BL
, BL, and at the same time, the first clock signal φ1 is raised from VSS to VCC. As a result, the bit line pair BL1, BLl becomes v5
5 nib charge, equalized. Here, when the first clock signal φ1 is lowered from vcc to VSS, the bit line pair BL, , BL becomes a floating state while being maintained at the VSS level. In this state, the row decoder/word line driver 1 is operated according to the designation of the address signal, and the selected word line WL is raised from VSS to VCC. At the same time, as mentioned above, a dummy cell consisting of a paraelectric capacitor DC' and a switching transistor DF' is connected to the complementary (other) bit line BL of one bit line BL connected to the ferroelectric memory cell. Word line decoder/driver 2 operates. Due to this operation, VS! is applied to one bit line BL connected to the ferroelectric memory cell consisting of the selected ferroelectric capacitor MC and transistor MF. 1/2V cc is applied to the bs plate line PL. At this time, if the ferroelectric capacitor MC of the memory cell has the same polarization direction as the electric field direction, the current flow is small, and if the polarization direction is opposite and the polarization is reversed by this electric field, the current flow is large. Current will flow into it. Along with this, in the former case, the potential rise of one bit line BL is small;
In the latter case, the potential of one bit line BL increases significantly. As the dummy cell, by using a paraelectric capacitor with a capacitance such that a current between the two flows and a potential rise between the two, the difference in data is reduced to bits, similar to conventional dynamic random access memory (DRAM). It appears as a potential difference between the line pairs BL, , BL. In this state, the sense amplifier operation signals φAcT, φACT
By operating the sense amplifier 5 by operating each of the bit lines, the potential of the bit line with a large potential rise is set to V. The potential of the bit line whose potential rise is small is pulled down to VSS. Other operations are the same as described above.

As described above, in the ferroelectric memory of the first embodiment, the first
Connecting the electrode to a bit line (for example, one bit line BL) that provides one of two potentials (Vss or V.C) corresponding to binary writing of 1-bit information via a switching transistor MF, The second capacitor MC
By connecting the plate line PL that holds the electrode at an intermediate potential (for example, 1/2 V cc) between the two potentials corresponding to the binary writing, the first voltage of the capacitor MC is By setting the bit line BL connected to one electrode to VCC or VSS, the first and second electrodes of the capacitor MC are set to H level, respectively.
It can be set to L level, inverted L level, or H level. Therefore, according to the first embodiment, the peripheral circuitry becomes complicated, as in the conventional case, the same number of drive lines as the word lines are required in order to realize a state opposite to the HSL level state between the ferroelectric capacitors. Since the problem can be solved, the degree of freedom in design can be improved and a high-density ferroelectric memory can be obtained.

Furthermore, according to the first embodiment, it has non-volatility that retains data even when the power is turned off, and there is no need for a refresh operation.
Conventional dynamic random access memory (DRAM)
), it is possible to obtain a ferroelectric memory suitable for high integration.

Embodiment 2 FIG. 2 shows a ferroelectric capacitor MC and a switching transistor M connected to one word line (for example, WL).
This is a ferroelectric memory in which a memory cell consisting of F, a ferroelectric capacitor MC', and a switching transistor MF' is used as one bit, and one of the cells is used as a dummy cell. In this ferroelectric memory, the polarization of the ferroelectric material in the ferroelectric capacitor of one memory cell and the ferroelectric material of the ferroelectric capacitor of the other memory cell are reversed, and the combination of polarizations is used to generate one bit. The information is stored. According to this configuration, the sense amplifier 5
After precharging, the word line WL is changed from v, s to V
When set to CC, data can be obtained by determining which bit line pair (for example, BL, , BLI) connected to the body capacitor has a higher potential. This eliminates the need to provide a separate dummy cell, increases resistance to noise, and improves reliability. V 85 as bit line precharge
, V ((() is the same as in the first embodiment. The timing charts are also as shown in FIGS. 5 to 7 described above.

Embodiment 3 FIG. 3 is a circuit diagram of a ferroelectric memory according to Embodiment 3, in which a means for switching the potential of the second electrode of a ferroelectric capacitor in a ferroelectric memory cell is added to the circuit of Embodiment 1 described above. It has a structure with 7 added. The potential cutoff warning means 7 is a first branched line provided at the other end of the plate line PL.
power supply 1/2vcc, second power supply VPL, and the first and second
The first and second switching transistors FR, for selecting one of the power supplies 1/2V ccSV PL,
It is composed of FR2. By turning on and off the first and second switching transistors FR, FR2, respectively, the potential of the plate line PL becomes 1/2 V cc of the first power supply, and it operates as a ferroelectric nonvolatile memory as in the first embodiment described above. It becomes possible to do so. The first and second switching transistors F R+
By turning FR2 off and on, the potential of the plate line PL becomes VPL. This vpt potential is
It doesn't matter if it's VCC or VSS. By doing this, while power is being applied, one bit can be stored depending on the presence or absence of charge, similar to a conventional dynamic random access memory (DRAM) using a capacitor. In this case, apart from the dummy cell of the ferroelectric memory, one bit line BL
, and the dummy word 1idDWL for the other DRAM mode.
A dummy cell for DRAM mode, the other bit line BL, and one dummy word line d for DRAM mode are placed at the intersection of ``.
Dummy cells for DRAM mode were connected to the intersections of the DWLs.

The one DRAM mode dummy cell is composed of a paraelectric capacitor dDC having half the capacity of a ferroelectric capacitor and a switching transistor dDF. A first electrode of the capacitor dDC is connected to one bit line BL via the switching transistor dDF.
It is connected to the. A second electrode of the capacitor dDC is connected to the plate line PL. The gate of the switching transistor dDF is connected to the other DRA'M.
It is connected to the mode dummy word line dDWL'. The other DRAM mode dummy cell is a paraelectric capacitor dDC' and a switching transistor dD.
It is composed of F'. The capacitor dDC'
The first electrode of the switching transistor dDF
' is connected to the other bit line BL1.

A second electrode of the capacitor dDC' is connected to the plate line PL. The gate of the switching transistor dDF' is connected to one DRAM mode dummy word line dDWL. In addition, the DRA
Dummy word line dDWL for M mode.

dDWL' is dummy word line decoder/driver 2
It is connected to the.

Next, the state in which it operates as a ferroelectric nonvolatile memory is called a nonvolatile memory mode, and the state in which 1 bit is stored depending on the presence or absence of charge, similar to a conventional dynamic random access memory (DRAM) using a capacitor, is called a DRAM mode. Switching from storage mode to DRAM mode, operation in DRAM mode, and switching from DRAM mode to nonvolatile storage mode will be explained separately. It is assumed that a DRAM mode operation signal is provided as an external output signal and a switching signal CHG is provided as an external input signal.

[Switching from non-volatile memory mode to DRAM mode] When using ferroelectric memory in non-volatile memory mode, the first
As described in the first embodiment, the precharge potential Vp (of the first equalization circuit 3 operated by the clock signal φ) can be either V.C or ■s□.Furthermore, in the DRAM mode, Plate line and PL when using
Since the potential VPL can be either VCCsV, . . . , the following four combinations are possible.

■■,. , VPL are both VCC mode switching precharge potentials V,. , plate line potential v1. As both V. The operation when it is set to 0 will be explained with reference to the timing chart of FIG.

DRAM mode operation signal n is H in nonvolatile memory mode.
maintained at the level. By setting the switching signal r to the L level before lowering the chip enable six to the L level, a switching cycle from the nonvolatile storage mode to the DRAM mode is started.

The switching procedure is to sequentially scan the row addresses in the same way as refreshing a DRAM, and to sequentially switch information based on the polarization of the ferroelectric memory cell connected to the word line to information based on the presence or absence of charge. If this operation is performed for all word lines, switching is completed. As a method of counting up the row address, it is possible to prepare a dedicated counter, but in the third embodiment, the refresh counter is used with one scan.

When no chip is selected, the bit line pair BL,
BL is set to 1/2Vcc by the second equalization circuit 4.
precharged and equalized.

By setting the second clock signal φ2 to v5s, the precharge and equalization of the bit line pair BL, BL are canceled and at the same time the first clock signal φ is set to v5s.

is raised from vss to V((.The first clock signal φ
1 to V55, bit line pair BL,
, BL, are in a VCC floating state.

Here, the row decoder/word line driver is operated according to the designation of the address signal, and the first word line WL is changed from VSS to ■. Pull up to C. At the same time, a dummy word line is connected so that a dummy cell consisting of a paraelectric capacitor DC' and a switching transistor DF' is connected to the complementary (other) bit line BL of one bit line BL to which the ferroelectric memory cell is connected. The decoder/driver 2 works. That is, the dummy word line DWL is selected and pulled up from v5. to VCo, thereby connecting the dummy cell to the other bit line BL.Similar to the first embodiment, the ferroelectric memory The information based on the polarization of the cell is read out, and the sense amplifier 5 determines the potential of the bit line pair BL, , BL.In this state, the first switching transistor FR of the potential switching means 7 is switched from ■.C to Vss.
(off), the second switching transistor FR2 is set to V
Change from SS to VCC (on) and plate line P
Change the potential of L from 1/2V cc to VCC. Then, when "1" is stored in the nonvolatile storage mode, since one bit line BL is at VCC, the bit line BL and plate line PL have the same potential, and the charges are canceled. Conversely, when "0" is stored in the non-volatile storage mode, one bit line BL1 is at VSS, so charges are stored between it and the potential vco of the plate line PL. In this way, information based on the polarization direction of the ferroelectric material can be made to correspond to the presence or absence of charge. In reality, in addition to the presence or absence of charge, the polarization direction remains opposite, but the precharge potential VPC and the plate line potential VP
Since L is at the same potential, no reversal of polarization occurs during rewriting or refreshing when reading DRAM Morton-Kusuji data, so there is no problem in operation. Furthermore, when data is rewritten in DRAM mode, the polarization may be reversed, but since this is during writing, there is no problem. word line WL, to V. C to V5s to disconnect the memory cell from the bit line BL. The sense amplifier signal φACT %φ^CT is operated to stop the operation of the sense amplifier 5, and the first clock signal φ1 is set to VSS.
After raising it from VCC to VCC, lower it to VCC floating state. During this time, the first switching transistor FR is turned from V55 to Vcc (ON), and the second switching transistor FR2 is turned to VCC. C to V5° (off)
to change the potential of the plate line PL from Vcc to
Set it to 1/2 VCC. Then, the row decoder/word line driver 1 is operated according to the designation of the large address signal,
The next word line WL2 is set to v5. From V. Raise it to C and repeat the above operation. After the above operations are completed for all word lines, the second clock signal φ2 is set to VCC, and the second equalize circuit 4 sets the bit line pairs BL, , BL, to 1.
Precharge and equalize to /2V cc. Also,
At the same time, the first switching transistor FR of the potential switching means 7 is changed to Vss (off) and the second switching transistor FR2 is changed to Vcc (on) to keep the potential of the plate line PL at VCC. When all of these are completed, the DRAM mode operation signal DR is lowered from the H level to the L level. This indicates that the memory has transitioned to DRAM mode. Externally, it is necessary to operate the refresh circuit at the same time as the signal is output. Also, internally, the dummy cells are switched to those for DRAM mode.

By setting the switching signal CHG to H level and setting the chip enable C1 to H level, the switching cycle from the nonvolatile memory mode to the DRAM mode is completed.

■Mode switching where V and c are VSS and VPL is VCC Set the precharge potential VPC to V55. Plate line potential v
1. The operation when VcC is selected will be explained with reference to the timing chart of FIG.

After reading information in non-volatile memory mode using VSS floating, the bit line pair BL is set by the sense amplifier 5.
, BL+ is determined. In this state, the first switching transistor FR of the potential switching means 7,
from VCC to Vss (off), and the second switching transistor FR2 from v5. The potential of the plate line PL is changed from 1/2 Vcc to Vcc (on). C
Make it. The subsequent operation is similar to the mode switching operation described above. In this way, information based on the polarization direction of the ferroelectric material can be made to correspond to the presence or absence of charge. In addition to the presence or absence of charge, the polarization direction also remains opposite.
Since the precharge potential VPC is VSS and the plate line potential vpt is Vcc, the data due to polarization is “1”.
That is, the polarization is reversed when reading the bit line potential at Vcc or during refresh. However, since it works in the direction of expanding the potential difference caused by the presence or absence of charge, there is no problem after all. There is no problem even if it is reversed when writing.

■vPc is ■. 0, vpt is VSS, and the mode switching precharge potential VPC is set to V ((, the operation when the plate line potential V, , - is selected as VSS will be described with reference to the timing chart in FIG. 10.

V for reading information in non-volatile storage mode. After C floating, the bit line pair BL is set by the sense amplifier 5.
, BL, are determined. In this state, the first switching transistor FR of the potential switching means 7,
V. C to V8. (off), the second switching transistor FR is changed from vss to Vcc (on), and the potential of the plate line PL is changed from 1/2 Vcc to vss. Then, if "1" is stored in the nonvolatile storage mode, the bit line is at vcc, so that charge is accumulated between it and the potential Vss of the plate line PL. Conversely, if "0" is stored in non-volatile storage mode, the bit line becomes v5. Therefore, the bit line and plate line are at the same potential, and the charges are canceled. In this way, information based on the polarization direction of the ferroelectric material can be made to correspond to the presence or absence of charge. In addition to the presence or absence of charge, the polarization direction also remains opposite, or the precharge potential V,. is V,. , plate line potential VPL is VSS
Therefore, when data due to polarization is "0", that is, the bit line potential is VSS, is read out or during refresh, the polarization is reversed. However, since it works in the direction of expanding the potential difference caused by the presence or absence of charge, there is no problem after all. Similarly, there is no problem even if it is reversed during writing.

■V. is VSS, and vpt is the mode switching precharge potential V of VSS. 59, and the operation when the plate line potential VPL is selected as VSS will be explained with reference to the timing chart of FIG.

After reading information in the non-volatile memory mode using vss floating, the sense amplifier 5 reads the bit line pair BL.
, BL, are determined. Potential switching means 7
The first switching transistor FR, is ■. 0 to V
ss (off), the second switching transistor FR2 is changed from Vss to Vcc (on), and the potential of the plate line PL is changed from 1/2VCC to VSS. Then, in the non-volatile memory mode, if "1° is stored, the bit line is V. Since it is 0, charge is stored between it and the potential v5° of the plate line PL. Conversely, in the non-volatile memory mode, " If 0” is stored, the bit line is set to VSS.
Therefore, the bit line and plate line are at the same potential, and the charges are canceled. In this way, it was possible to make information based on the polarization direction of the ferroelectric material correspond to the presence or absence of charge. In this case, as well as the presence or absence of charge, the polarization direction remains opposite, but since the precharge potential VPC and the plate line potential VPL are at the same potential, the polarization will change during rewriting or refreshing when the same data is being read. Since no reversal occurs, there is no problem in operation.

Furthermore, when data is rewritten in DRAM mode, the polarization may be reversed, but since this is during writing, there is no problem at all.

[Operation in DRAM Mode] The write operation and timing in DRAM mode in the ferroelectric memory of the third embodiment will be explained with reference to FIG.

Although the plate line potential VPL may be VCC or VSS, it is set to VCC here. Similar to the conventional DRAM, a write cycle is started by setting the write signal WE to the L level before the chip enable 1 is lowered to the L level. It is assumed that the memory address and the write data D1N from the input/output section are determined before the chip enable Uτ is lowered to the L level. When no chip is selected, bit line pair B
L, , 117; is converted to t/ by the second equalization circuit 4.
Precharged and equalized to 2V cc.

The second clock signal φ2 is set to VSS, and the bit line pair BLI
, cancel the precharge and equalization of r. Data input/output lines I10 and Ilo that connect memory cells and the outside
The signal is VSS or VCC according to the write data DIN.
It has been confirmed that After that, the row decoder/word line driver 1 is operated according to the address signal designation, and the word line W
L, from VSS to V. Raise it to 0. In this state, the memory cell is connected to the bit line BL. On the other hand, the column decoder/column select line driver 6 is operated according to the address signal designation, and the selected column select line C3L is activated.
, is pulled up from VSS to VCC, column selection switching transistors CF,..., CF,b are turned on and data input/output lines I10, Ilo and bit line pairs BL,
, BL, are connected to each other, and data input/output lines I10,
Ilo potential (v55 or Vcc) and bit line pair BL
, , "The potentials of the ports become equal. By doing this, when the bit line BL is at VCC, no potential difference is created between the plate lines PL whose potential is VCC, and the charges are canceled. The bit line IBL , is VSS, a potential difference is generated between the plate lines PL, and charge is stored in the memory cell.After writing, the word line WL is lowered from VCC to VB2, and the memory cell is connected to the bit line BL. , disconnect from.Column select line C3L
, V. 0 to V'55, bit line pairs BL, , BL become data input/output lines I10. It is separated from I10. At the same time, the second clock signal φ2 is set to VB2.
to VCC, and the second equalization circuit 4 equalizes the bit line pair BL to 1/2 V cc.The chip enable CE is raised to H level, and the write signal W lower is set to H level, thereby starting the write cycle. Through this series of operations, data is written to the ferroelectric memory cell specified by the address and is retained.

In addition, in DRAM mode, refresh operation or conventional D
It is necessary like RAM.

Note that the operation when the plate line potential VPL is set to VB2 in the write operation described above will be explained with reference to the timing chart of FIG. 13. In this operation, when the bit line is at VCC, a potential difference is generated between the plate lines PL and charge is stored in the memory cell, and when the bit line is at VB2, no potential difference is generated between the plate lines PL. , the other operations are exactly the same as described above, except that the charges are canceled.

Next, the read operation and timing of data written in the write mode will be explained. As the bit line precharge before reading the written data, the precharge potential VP of the first equalization circuit 3 is used.
When using C and the potential 1/2 of the second equalization circuit 4
A case of using Vcc is considered, and there are also methods of setting the precharge potential VPC to vCC and VSS. Also, for each plate line potential ■, L is V. . There are six combinations in total, which will be explained below.

■V. is V CC5V PL is V. The first equalizer circuit 3 is used to precharge the 0 read mode bit line.
Using the potential Vp (as V.0, the plate line PL
The first read operation is performed when the potential vPL of is set to VCC.
This will be explained with reference to the timing chart in FIG.

A read cycle is started because the write signal W1 is at the H level when the chip enable is lowered to the L level. It is assumed that the memory address is fixed before the chip is enabled and lowered to the 100 or L level. When no chip is selected, the bit line pair BLI is set to l/2 by the second equalization circuit 4.
Precharged and equalized to Vcc.

When the second clock signal φ2 is set to VSS, and
At the same time as precharging and equalizing one port, the first clock signal φ1 is raised to VCC, and the first clock signal φ1 is raised to VCC.
By the equalization circuit 3, the bit line pair BL1, BLI is
☆Precharge and equalize Jcc. here,
When the first clock signal φ1 is lowered from vCC to Vss, the bit line pair BL1, BL becomes a floating state while being maintained at the VCC level. In this state, the row decoder/word line driver 1 is operated according to the designation of the address signal, and the word line WL is raised from VB2 to Vco. At the same time, a dummy word is connected so that a DRAM mode dummy cell consisting of a paraelectric capacitor dDC' and a switching transistor dDF' is connected to the complementary (other) bit line BL of one bit line BL to which the ferroelectric memory cell is connected. Line decoder/driver 2 works.In other words, one DRAM mode dummy word line d
DWL is selected and pulled up from VSS to VCC, thereby connecting the DRAM mode dummy cell to the other bit line port T. Then, the potential V of the bit line BL is applied to the selected ferroelectric memory cell. The potential VCC of the c1 plate line PL is applied.

At this time, if charge is stored in the memory cell, the potential drop of the bit line is large, and if no charge is stored, the potential drop is small. By using a paraelectric capacitor having half the capacity of a ferroelectric capacitor in the DRAM mode dummy cell, a data difference appears as a potential difference between the bit line pair BL, BL, as in the conventional DRAM. In this state, the sense amplifier signal φ^CT%
<6 By operating the sense amplifier 5 by operating each ACT, the potential of the bit line whose potential drop is small is raised to VCC, and the potential of the bit line whose potential drop is large is pulled down to VSS. As with conventional DRAMs, all charges are lost during reading due to destructive reading, but rewriting is performed by determining the potential by the sense amplifier 5. After the potentials of the bit lines BL, BL are determined, the column decoder/column select line driver 6 is operated according to the designation of the address signal, and the selected column select line C3L is set to v9. From V. Pull up to C.

Then, bit lines BL, , BL, and data input/output line I
10 and Ilo are connected, respectively, and the output data is output to D0LIT through the I10 buffer, as in the first embodiment. Column select line C3L is V. C becomes VSS, and the data input/output lines I10 and Ilo are separated from the bit line pair BL1 and BLI. Word line WL
, V. 0 to VSS, the word line WL,
The memory cells connected to the bit line BL are separated from the bit line BL.

The sense amplifier signals φACT and φACT are operated to stop the operation of the sense amplifier 5, and the second clock signal φ2 is set to V.
B5 to VCC and bit line pair BL+, BLl to 1
Equalize to /2vcc. The read cycle ends by raising chip enable CE to H level.

■■,. is VSS and VPL is V. 0 read mode Before reading the written data, the first equalize circuit 8 sets the precharge potential VPC of the bit line to VSS.
The read operation in this case will be explained with reference to the timing chart of FIG.

The second clock signal φ2 is set to VSS, and the bit line pair BL,
, BL, and at the same time, the first clock signal φ1 is raised from v,s to V(((). As a result, the bit line pair BL1, BL is set to V3s.
is precharged and equalized. Here, when the first clock signal φ1 is lowered from Vcc to V55, the bit line pair BL, BL, becomes floating while being maintained at the VSS level. In this state, the row decoder/word line driver 1 is operated according to the designation of the address signal, and the selected word line WL is changed from V5s to V5. Pull up to C. At the same time, a dummy cell for DRAM mode consisting of a paraelectric capacitor dDC' and a switching transistor dDF' is connected to the complementary (other) bit line BL of one bit line BL to which the ferroelectric memory cell is connected. Word line decoder/driver 2
works. Then, in the selected ferroelectric memory cell, the potential 56 of the bit line BL and the potential 56 of the plate line PL are applied. If C is applied and a charge is stored, almost no current will flow; if no charge is stored, a current will flow. Accordingly, in the former case, the potential rise of the bit line is small, and in the latter case, the potential rise of the bit line is large. As a dummy cell for DRAM mode,
It is sufficient to use the same dummy cell as when the precharge potential Vp (is set to VCC).In this state, by operating the sense amplifier operation signals φACT and <6ACT to operate the sense amplifier 5, the bit line with a large potential increase, .

The potential of the bit line pair whose potential rise is small is pulled down to VSS. Other operations are the same as above.

■V. is vc and VPL is VSS read mode 1st
The precharge potential V of the bit line by the equalization circuit 3
PC is vcc, plate line potential VPL is V, 5
The read operation in the case of 1 is explained with reference to the timing chart in FIG.

After setting the bit line pair BL, , Bl to VCC floating state, the row decoder/
The word line driver 1 is operated and the selected word line WL is
, is raised from VSs to VCC, the potential V of the bit line BL is applied to the selected ferroelectric memory cell. Potential V55 of c1 plate line PL is applied. Here, when charges are stored in the memory cell, the potential drop of the bit line is small, and when no charges are stored, the potential drop is large. The former 4 is V due to the sense amplifier 5. 0, and the latter is lowered to V55. Other operations are the same.

■V. is VSs, v, and L are v 55” Read mode The bit line precharge potential VPC by the first equalization circuit 8 is set to V55, and the plate line potential VPL is set to V.
The read operation in the case of SS will be explained with reference to the timing chart of FIG. 17.

After setting the bit line pair BL, BL to the VSS floating state, the row decoder/word line driver 1 is operated according to the designation of the address signal, and the selected word line W is activated.
When L is raised from VSS to V((, the potential VSS of the bit line BL and the potential ■ss of the plate line PL are applied to the selected ferroelectric memory cell. Charge is stored in the memory cell. When the charge is stored, the potential rise of the bit line is large, and when no charge is stored, the potential rise is small.The sense amplifier 5 pulls up the former to VCC, and lowers the latter to VSS.Other operations are the same. It is.

■Bit line precharge potential is l/2V cc, V
In the read mode where PL is VCC, the second equalize circuit 4 sets the bit line precharge potential to 1/2V cc, and the plate line potential VPL to VCC. The read operation in the case of C is explained with reference to the timing chart of FIG.

When no chip is selected, the bit line pair BL,
BL is set to 1/2Vcc by the second equalization circuit 4.
precharged and equalized.

In this case, the first equalize circuit 3 is not operated and the second
Bit line pair BL with clock signal φ2 set to VSS,
When the precharge and equalization of BL are canceled, the bit line pair BL, BL, becomes a floating state while being maintained at the 1/2 Vcc level.

The row decoder/word line driver 1 is operated according to the designation of the address signal, and the selected word line WL is set to VSS.
From V. When raised to 0, the potential 1/2 Vcc of the bit line BL and the potential VCC of the plate line PL are applied to the selected ferroelectric memory cell. Here, if charge is stored in the memory cell, the bit line potential is 1/2
Slightly lower than Vcc, and higher than 1/2Vcc if no charge is stored. The sense amplifier 5 pulls down the former to VSS, and pulls the latter up to VCC.

Other operations are the same.

■Bit line precharge potential is 1/2V cc, V
In the read mode where PL is VSS, the second equalize circuit 4 sets the bit line precharge potential to 1/2 Vcc, and the plate line potential VPL to VSS.
The read operation in the case of 55 will be explained with reference to the timing chart of FIG.

When no chip is selected, the bit line pair BL,
BL is set to 1/2Vcc by the second equalization circuit 4.
precharged and equalized.

In this case, the first equalize circuit 3 is not operated and the second
Bit line pair BL with clock signal φ2 set to VSS,
When the precharge and equalization of BL, are canceled, the bit line pair BL, BL+ becomes a floating state while being maintained at the l/2Vcc level.

The row decoder/word line driver 1 is operated according to the designation of the address signal, and the selected word line WL is set to VSS.
From V. When the bit line BL is pulled up to 0, the potential '/2vccs of the bit line BL and the potential VSS of the plate line PL are applied to the selected ferroelectric memory cell. If charge is stored in the memory cell, the potential of the bit line is 1/2
It becomes slightly higher than Vcc, and becomes lower than 1/2 Vcc when no charge is stored. The former is V due to sense amplifier 5. C, the latter is V5. be lowered to

Other operations are the same.

As described above, there are several possible ways to set the precharge potential and plate line potential, and any of these methods will allow the device to operate well as a DRAM.

[Switching from DRAM mode to non-volatile memory mode] This operation reads out information in DRAM mode and sequentially writes it to non-volatile memory mode, so it will be explained below in correspondence with the above-mentioned six types of DRAM mode read methods. There are six methods.

However, the basic operations are all the same.

■■,. , vpL are both VCC mode switching precharge potential vPCsThe operation when both of plate line potential VPL are set to VCC will be described with reference to FIG.

DRAM mode operation signal F ball is L in DRAM mode.
maintained at the level. In addition, along with this, the first switching transistor FR of the potential switching means 7 is switched to Vs.
s (off), the second switching transistor FR2 is ■
. C (on) and the plate line potential is VCC. By setting the switching signal CHG to the L level before the chip enable CE is lowered to the L level, a switching cycle from the DRAM mode to the nonvolatile storage mode is started.

The switching procedure is to sequentially scan the row addresses in the same way as refreshing a DRAM, and to sequentially switch information based on the presence or absence of charge in the ferroelectric memory cells connected to the word line to information based on polarization. If this operation is performed for all word lines, switching is completed. Although a dedicated counter can be prepared as a method for counting up addresses, in this embodiment, a refresh counter is used with one scan.

When no chip is selected, the bit line pair BL,
, BL, are set to 1/2Vcc by the second equalization circuit 4.
precharged and equalized.

The second clock signal φ2 is set to vss, and the bit line pair BL
, , BL, and at the same time, the first clock signal φ1 is set to V3. bit line pair BL by lowering the first clock signal φ1 to 55.

BL becomes a floating state of VCC. here,
The row decoder/word line driver 1 is operated according to the address signal designation, and the first word line WL is changed from Vss to Vss.
Upload to CC. At the same time, the complementary bit line BL to which the ferroelectric memory cell is connected is connected to the DRAM.
The dummy word line decoder/driver 2 operates so that the mode dummy cells are connected. Similar to the reading in the DRAM mode described above, information based on the presence or absence of charge in the ferroelectric memory cell is read out, and the sense amplifier 5 reads the information from the bit line pair B.
The potentials of L and BL are determined. In this state, the first switching transistor FR of the potential switching means 7
, is Vcc (on), and the second switching transistor F
Change R2 to VB2 (off) to change the plate line potential from VCC to 1/2VCC. Then, if "1" is stored in DRAM mode, the bit line will be set to VCC.
Therefore, a potential difference is generated between the bit line and the plate line potential 1/2V cc, and the bit line is polarized toward the plate line. Further, when "0" is stored in the DRAM mode, the bit line becomes vss, a potential difference is generated between the bit line and the plate line potential 1/2Vcc, and the bit line is polarized from the plate line toward the bit line. After operating the sense amplifier signal φAcrsd)h- to stop the operation of the sense amplifier 5, the second clock signal φ2 is changed from vss to VC.
Equalize the bit line pair BL to 1/2 V CC by setting it to C. As a result, the potential of both picture electrodes of the ferroelectric memory cell becomes 1/2 V CC, so the charge accumulated during writing is canceled. However, since the potential difference is 0, the written polarization does not change.Then, by changing the word line WL from VCC to VSS, the ferroelectric memory cell is separated from the bit line BL1.The second clock At the same time as the signal φ2 is changed from VCC to Vss, the first clock signal φ1 is raised from vs to V((, and then lowered to the VCC floating state. During this time, the first switching transistor FR, from VCC to Vss (off), and the second switching transistor FR2 from VSS to Vcc.
(on) and set the plate line potential to 1/2Vc.
c to v. Leave it at 0.

Then, the row decoder/word line driver 1 is operated according to the designation of the address signal, and the selected next word line WL is
2 from VB2 to VCC and repeat the above operation. After the above operations are completed for all word lines, the second clock signal φ2 is set to VCC, and the bit line pair BL1, B
Precharge and equalize Ll to 1/2Vcc.

At the same time, the first switching transistor FR of the potential switching means 7 is changed to VccC (on), and the second switching transistor FR2 is changed to VB2 (off) to keep the plate line potential at 1/2 Vcc. When all of these are completed, the DRAM mode operation signal DR is raised from the L level to the H level. This indicates that the memory has transitioned to non-volatile storage mode. Externally, it is necessary to stop the refresh circuit at the same time as this signal is issued. Also, internally, the dummy cells are switched to those for non-volatile memory mode.

The switching cycle from the DRAM mode to the nonvolatile storage mode is completed by setting the switching signal C2 to H level and the chip enable CE to H level.

■Vp (is VSS, VPL is VCC mode switching precharge potential V,. VB2 is plate line potential V
The operation when PL is selected as VCC will be explained with reference to the timing chart of FIG.

After reading the DRAM mode information using VSS floating, the sense amplifier 5 reads the bit line pair BL,
, rllm is determined. In this state, the first switching transistor FR of the potential switching means 7 is changed from VSS to V. 0 (on), and the second switching transistor FR2 is ■. The plate line potential is changed from 0 to Vss (off) and the plate line potential is changed from V(( to 1/2V cc.) The subsequent operation is the same as described above. Information can be made to correspond to the polarization direction.

(2) Mode switching where VPo is VCCN and VPL is Vs The operation when the precharge potential VPC is set to VCCs and the plate line potential VPL is set to VSS will be described with reference to the timing chart of FIG.

■ Read out DRAM mode information. After C floating, the bit line pair BLI is set by the sense amplifier 5.
F'r? Determine the potential of In this state, the first switching transistor FR of the potential switching means 7 is changed from V55 to V. . (on), the second switching transistor FR2 is set to V. 0 to Vss (off) to change the plate line potential from v55 to 1/2Vcc.

The subsequent operations are the same as described above. In this way, information based on the presence or absence of charge in the ferroelectric material can be made to correspond to the polarization direction.

■V. is the mode switching precharge potential V, where VSS is VSS and VPL is VSS. The operation when both the plate line potentials v and L are selected as VSS will be explained with reference to the timing chart of FIG.

After reading the DRAM mode information with V55 floating, the bit line pair BL,
, BL, are determined. In this state, the first switching transistor FR of the potential switching means 7 is changed to v
5. Then, the second switching transistor FR2 is changed from VCC to Vss (off) to change the plate line potential from VSS to 1/2V cc.

The subsequent operations are the same as described above. In this way, information based on the presence or absence of charge in the ferroelectric material can be made to correspond to the polarization direction.

■Bit line precharge potential is 1/2 VC and VPL is V
The CC mode switching precharge potential is set to 1/2 Vcc, which is the potential of the second equalization circuit 4, and the plate line potential VPL is set to V.

The operation in case of C is explained with reference to the timing chart of FIG.

When no chip is selected, the bit line pair BL,
, BL, are set to 1/2V c by the second equalization circuit 4.
Precharged and equalized to c.

In this case, the first equalization circuit 3 does not operate, the second clock signal φ2 is set to vss, and the bit line pairs BL, ,
When the precharge and equalization of BL are canceled, the bit line pair BL, 8, becomes a floating state while being maintained at the 1/2 Vcc level.

After reading the information in the DRAM mode with 1/2 Vcc floating, the sense amplifier 5 determines the potential of the bit line pair BL, BL-1. In this state, the first switching transistor FR of the potential switching means 7 is changed from V55 to V. . (on), changes the second switching transistor FR2 from VCC to Vss (off) to change the plate line potential from vcc to I/2V.
Make it cc. The subsequent operations are the same as described above.

In this way, information based on the presence or absence of charge in the ferroelectric material can be made to correspond to the polarization direction.

■Bit line precharge potential is 1/2V cc, V
The mode switching precharge potential VPC where PL is Vss is set to 1/2V cc, which is the potential of the second equalization circuit 4, and the plate line potential VP
The operation when L is set to Vss will be explained with reference to the timing chart of FIG. 24.

After reading the information in the DRAM mode with 1/2'Vcc floating, the sense amplifier 5 determines the potential of the bit line pair BL, BL. In this state, the first switching transistor F of the potential switching means 7
R, from VSS to Vcc (on), and the second switching transistor FR2 from Vcc. Change the plate line potential from VSS to I/2V cc by changing from C to Vss (off).
Make it. The subsequent operations are the same as described above. In this way, information based on the presence or absence of charge in the ferroelectric material can be made to correspond to the polarization direction.

According to the third embodiment described above, while power is being applied, the DRAM
mode to reduce the number of polarization reversals of the ferroelectric material,
It is possible to obtain a ferroelectric memory that can shift to a nonvolatile storage mode and retain information in the memory before turning off the power.

Embodiment 4 FIG. 4 shows a memory cell consisting of a ferroelectric capacitor MC and a switching transistor MF connected to one word line (WL+) and a memory cell consisting of a ferroelectric capacitor MC' and a switching transistor MF'' connected to one word line (WL+) for one bit. This is a ferroelectric memory in which one of the cells is used as a dummy cell, and the other structure is the same as that of the third embodiment described above.

In this ferroelectric memory, the polarization of the ferroelectric layer of the ferroelectric capacitor of one memory cell and the ferroelectric material of the ferroelectric capacitor of the other memory cell are reversed, and the combination of polarizations is used to generate one bit. Remember information. According to this configuration, the sense amplifier 5 is connected to the word line WL after being precharged.

■ from VSS. Since data can be obtained by determining which bit line pair BL, , BL, connected to the ferroelectric capacitor has a higher potential when set to 0, it is not necessary to provide a dummy cell as in the third embodiment described above. It also becomes more resistant to noise and improves reliability. Furthermore, there is no need to switch dummy cells when switching between nonvolatile memory mode and DRAM mode. As in the third embodiment, the precharge potential of the bit line can also be VS or 1/2 Vcc in the vCc1DRAM mode.

Also, v5. Also V. You can also get a C. The timing charts in these cases are also as shown in FIGS. 8 to 25 described above.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a highly integrated ferroelectric memory that has a structure and circuit configuration similar to conventional DRAMs, has nonvolatility, and does not require refreshing. Also,
According to another ferroelectric memory of the present invention, it is possible to switch between DRAM mode and nonvolatile mode, and the service life is reduced due to access time delays due to ferroelectric polarization and ferroelectric polarization fatigue phenomena. It has remarkable effects such as being able to avoid problems.

[Brief explanation of the drawing]

1 is a circuit diagram of a ferroelectric memory according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a ferroelectric memory according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a ferroelectric memory according to a third embodiment of the present invention. FIG. 4 is a circuit diagram of a ferroelectric memory according to the fourth embodiment of the present invention; FIG. 5 is a timing chart illustrating write operation of the ferroelectric memory according to the first embodiment; FIG. The figure is a timing chart explaining the read operation of the ferroelectric memory according to the first embodiment, FIG. 7 is a timing chart explaining other read operations of the ferroelectric memory according to the first embodiment, and FIGS. The figures are timing charts for explaining the switching from the nonvolatile mode to the DRAM mode of the ferroelectric memory in the third embodiment, and FIG. 12 is the DR of the ferroelectric memory in the third embodiment.
FIG. 13 is a timing chart for explaining the write operation in AM mode, FIG. 13 is a timing chart for explaining the write operation in other DRAM modes of the ferroelectric memory in the third embodiment, and FIGS. 20 to 25 are timing charts for explaining the read operation of the ferroelectric memory in the DRAM mode of the third embodiment, respectively, and FIGS. Timing chart for explaining the switching operation, No. 26
The figure is a hysteresis characteristic diagram showing the relationship between the applied voltage and polarization of a ferroelectric, and Figure 27 shows the first and second ferroelectric capacitors.
FIG. 2 is a schematic diagram showing the arrangement of electrodes in FIG. DESCRIPTION OF SYMBOLS 1... Row decoder/word line driver, 2... Dummy word line decoder/driver, 3... First equalization circuit, 4... Second equalization circuit, 5... Sense amplifier, 6...・Column decoder φ column select line driver, 7...potential switching means, WLl, WLl
...Word line, DWL%DWL' ...Dummy word line, dDWL, dDWL' ...Dummy word line for DRAM mode, BL,, BL, --...Bit line pair, M
C, MC'...ferroelectric capacitor, DC, DC'
...Reference paraelectric capacitor, dDC, dDC...
- Paraelectric capacitor, MFSMF'DFSDF'
...Switching transistor, FRl...First switching transistor, FR2...Second switching transistor, φ1, φ2...Clock signal, φA
CT s d) ACT-Sense Amplifier Signal, Ilo,
Ilo...Data input/output line.

Claims (2)

[Claims] (1) In a ferroelectric memory that records 1-bit information by polarization of a ferroelectric material, the first electrode of a pair of electrodes sandwiching the ferroelectric material corresponds to binary writing of 1-bit information. A ferroelectric device characterized in that a means for applying one of two potentials is connected to the second electrode, and a means for holding a potential intermediate or approximately intermediate between the two potentials corresponding to the writing of the binary value is connected to the second electrode. body memory. (2) In a ferroelectric memory that records 1-bit information by polarization of a ferroelectric material, binary information of 1-bit information is written to the first electrode of a pair of electrodes that sandwich the ferroelectric material. Connecting a means for applying one of the two corresponding potentials and causing the second electrode to hold an intermediate or approximately intermediate potential between the two potentials corresponding to the writing of the binary value, or
Alternatively, a ferroelectric memory characterized in that a means for applying one of two potentials corresponding to the binary writing is connected.