JP2000100175A - Multiple-value ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiple-value ferroelectric memory that can be highly integrated, requires less bit costs, and can increase the reading operation speed of cell data by easily storing a multiple-value polarization amount that is equal to or more than four values while each '0' data and '1' data can be distinguished among a plurality of cell capacitors of an FRAM cell in a multiple-value FRAM and reading the data with one time read operation of the cell. SOLUTION: A multiple-value FRAM is provided with a plurality of cell capacitors CA and CB where a ferroelectric film is used for an insulation film between electrodes and each one end is commonly connected, at least one switch element Q where one end is connected to a common connection node at each one end side of a plurality of cell capacitors, and a memory cell array MCA where a memory cell that is constituted of a plurality of capacitors and one switch element are arranged two-dimensionally, a plurality of capacitors of each memory cell have essentially different capacitance values.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a ferroelectric memory (FRAM) having an array of ferroelectric memory cells using a ferroelectric thin film as an insulating film of an information storage capacitor, and more particularly to a plurality of ferroelectric memories. FR for storing multi-valued data (polarization amount) of three or more values in a memory cell configured by connecting a dielectric capacitor to at least one MOS transistor
The present invention relates to a cell data read / write control circuit in an AM, and is applied to a semiconductor integrated circuit including an FRAM.

[0002]

2. Description of the Related Art In recent years, an FRAM having an array of FRAM cells using a ferroelectric material having a perovskite structure or a layered perovskite structure as an inter-electrode insulating film of an information storage capacitor has attracted attention.

A ferroelectric has a hysteresis characteristic in a relationship between an applied electric field (V / m) and an electric polarization (C / m), and reduces an applied voltage (applied electric field) between both ends of a ferroelectric film. The characteristic is that the polarization remains even after returning to, that is, it shows non-volatility.

That is, the electric polarization once generated when an electric field is applied remains even when the electric field is no longer applied, and becomes polarized when an electric field of a certain strength or more is applied in a direction opposite to the electric field. Has the characteristic of reversing the direction.

Focusing on such characteristics, a FRAM cell which stores information as a polarization direction of a ferroelectric capacitor using a ferroelectric thin film as an inter-electrode insulating film is realized and stores binary data. Technology is being developed.

The FRAM cell has a configuration in which the capacitor of the DRAM cell is replaced with a ferroelectric capacitor, and electric charges at the time of polarization inversion or non-inversion are extracted from the ferroelectric capacitor via a switching MOS transistor. (Data destructive read), rewrite is performed after data read.

[0007] An FRAM having an array of FRAM cells as described above is characterized in that the number of times of data rewriting is large and the data rewriting speed is extremely high as compared with a flash memory which is another nonvolatile memory. Also,
Compared to a battery-backable SRAM used for a memory card or the like, it has features that the power consumption is small and the cell area can be significantly reduced.

The expectation of the FRAM having the above-mentioned features is very large, for example, replacement of existing DRAM, flash memory and SRAM, application to a logic embedded device, and the like. In addition, since FRAM can operate at high speed without a battery, a non-contact card (RF-ID: Radio-
Development to Frequency-Identification) is beginning.

There are two types of FRAM memory cell structures: a structure using a ferroelectric film for a capacitor for storing information and a structure using a ferroelectric film for a gate insulating film of a MOS transistor for a switch. It is roughly divided. In the latter case, if the semiconductor substrate is silicon, there is no suitable ferroelectric film that can be directly formed on the interface, and thus the feasibility remains a question.

In the former FRAM cell configuration, as shown in FIG. 12, one MOS transistor Q for a switch is used.
And one ferroelectric capacitor C for storing information in series with one transistor and one capacitor, and two sets of one transistor and one capacitor cell (two transistors and two ferroelectric capacitors). (A dielectric capacitor).

The one-transistor, one-capacitor type cell has the advantage of being able to achieve high integration equivalent to that of a DRAM, and the two-transistor, two-capacitor type cell has the advantage of being excellent in reliability.

The one-transistor, one-capacitor type F
In the RAM cell, the switching MOS transistor Q has a gate connected to the word line WL and a node on one end side connected to the bit line BL. The ferroelectric capacitor C has one end connected to the other end of the MOS transistor Q and the other end (plate electrode) connected to the plate line PL.

FIG. 13 is a hysteresis curve shown to explain the "0" read operation and "1" read operation corresponding to the cell capacitor of the one-transistor, one-capacitor type FRAM cell shown in FIG. , A, b, c, and d indicate the amount of remanent polarization.

Next, the operation of a binary information storage type FRAM having an array of one transistor / one capacitor type FRAM cells will be described with reference to FIG. First, in the precharge cycle, the bit line voltage VBL is set to the ground potential. Next, release the precharge of the bit line,
After the word line WL is selected and the transistor Q is turned on, the charge of the capacitor C is read out to the bit line by raising the plate line voltage VPL from the ground potential to the power supply voltage, and the change in the bit line potential caused by this is sensed. The signal is compared and amplified by an amplifier (not shown).

At this time, in the case of "0" reading, since the polarization of the capacitor C does not reverse, the amount of charge read to the bit line is small, and as a result of comparison and amplification by the sense amplifier, the bit line (the storage node Side) is at the ground potential. As a result, the polarization point of the capacitor C moves from the point a to the point c on the hysteresis curve.

On the other hand, in the case of "1" reading, the polarization of the capacitor C is reversed, and the plate line voltage VPL is read.
When the power supply voltage is applied, the amount of charge read out to the bit line is larger than in the case of "0" reading, and the bit line (storage node side of the capacitor C) becomes the power supply voltage as a result of comparison and amplification by the sense amplifier. As a result, the polarization point of the capacitor C shifts from point b to point c of the hysteresis curve and then to point a.

Next, after the output data of the sense amplifier is sent to a data line (not shown), the plate line voltage VPL
Is dropped to the ground potential, the polarization point for "0" reading returns to point a, and the polarization point for "1" reading moves to point d.

Thereafter, when the transistor Q is turned off, the polarization point in the case of "1" reading shifts from the point d to the point b, and the rewriting to the cell capacitor C is completed. In the above, reading and rewriting have been described. When data is to be rewritten, when the power supply voltage is applied as the plate voltage VPL, when "1" is to be written, the power supply voltage is applied to the bit line. To write "0", a ground potential may be applied to the bit line through an input / output line (not shown).

On the other hand, a "ferroelectric memory device" disclosed in Japanese Patent Application Laid-Open No. 4-90189 has a structure in which one ferroelectric capacitor is connected to one MOS transistor to form one memory cell. A technique capable of accumulating a polarization amount equal to or more than a value (multi-valued data equal to or more than three values) is disclosed.

Although this memory cell uses a plurality of ferroelectric capacitors, it can store multi-valued data and requires only one contact with a bit line. Can be realized.

However, in this technique, since the areas of the plurality of cell capacitors are equal, it is not possible to simultaneously distinguish data "1" or data "0". Also, since the number of sense amplifiers (not shown) used to read data from the memory cells is only one, there is a problem that the sense amplifiers need to be driven a plurality of times by the number of capacitors.

Hereinafter, this problem will be described through specific operations. FIG. 14 shows a configuration in which a quaternary memory is realized using, for example, two capacitors and one transistor.

In the case of such a configuration, first, the bit line voltage VBL is set to the ground potential in the precharge cycle. Next, the precharge of the bit line is released, the word line WL is selected and the transistor Q is turned on, and then the first plate line potential VPLA is raised from the ground potential to the power supply voltage, whereby the first cell capacitor is released. The electric charge of A is read out to the bit line, and the change in the bit line potential caused by this is compared and amplified by a sense amplifier (not shown). At this time,
The plate line potential of the unselected second cell capacitor B (that is, the second plate line potential VPLB) is set to Vcc / 2.

Next, after the output data of the sense amplifier is sent to a data line (not shown), the first plate line voltage VPLA is dropped to the ground potential, so that rewriting to the first cell capacitor A can be performed. finish.

Next, after the bit line voltage VBL is equalized to the ground potential, the precharging of the bit line is released, and the data of the second cell capacitor B is read out in the same procedure as the reading of the first cell capacitor A described above. Is read. Also at this time, the plate line potential of the unselected first cell capacitor A (that is, the first plate line potential VPLA) is set to Vcc / 2 as described above.

Next, after the output data of the sense amplifier is sent out to a data line (not shown), the second plate line voltage VPLB is dropped to the ground potential, so that rewriting to the second cell capacitor B can be performed. finish.

Finally, by turning off the transistor Q, the read / rewrite operation of the memory cell is completed. Note that the first cell capacitor A as described above,
In reading data from the second cell capacitor B, the plate line potential of each of the cell capacitors which are not selected is set to Vcc / 2, but "1" may be read from the selected cell capacitor. Even if "0" is read, only an electric field equal to or lower than the coercive electric field is applied between the electrodes of the non-selected cell capacitors, and no polarization inversion occurs.

A characteristic of such an operation is as follows.
In order to read and rewrite one memory cell, the plate line and the sense amplifier must be driven twice.

In connection with this, Japanese Patent Laid-Open No.
Japanese Patent Application Laid-Open No. -90189 does not disclose at all what the number of ferroelectric capacitors and the capacity of each capacitor should be in order to speed up the read operation.

[0030]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is a state in which "0" data and "1" data can be distinguished between a plurality of cell capacitors of one FRAM cell. , The multi-level polarization amount of three or more values can be easily stored, and the multi-level data can be read out by operating each of the plate line and the sense amplifier substantially once, thereby enabling high integration. Low bit cost,
It is an object of the present invention to provide a multi-valued ferroelectric memory which can speed up a cell data reading operation.

[0031]

The multilevel ferroelectric memory according to the present invention uses a ferroelectric film as an inter-electrode insulating film, the capacitance values thereof are substantially different, and one end of each memory is shared. A memory formed by two-dimensionally forming a memory cell including a plurality of connected capacitors and at least one switch element having one end connected to a common connection node at one end of each of the plurality of capacitors. It is characterized by having a cell array.

Further, the multi-valued ferroelectric memory of the present invention uses a ferroelectric film as an inter-electrode insulating film, has substantially different capacitance values, and has a plurality of terminals each having one end commonly connected. A memory cell array formed by two-dimensionally forming memory cells each including at least one switch element having one end connected to a common connection node on one end side of each of the plurality of capacitors and the plurality of capacitors; A first bit line connected to a node on the other end of the switch element of the memory cell in each column of the memory cell array, and a first electrode connected to a plate electrode on the other end of each of the plurality of capacitors. A plate line, and n read from the memory cell to the first bit line.
A sense amplifier region including a plurality of (n-1) sense amplifiers for respectively comparing and amplifying value data with a plurality of different reference potentials, and a memory cell having the first bit line connected to the memory cell An NMOS transistor inserted at a position dividing the region into the sense amplifier region and an NMOS transistor inserted at a position dividing the plurality of sense amplifiers, and the switch is controlled by a gate control signal applied to each gate. A sense amplifier area dividing switch element for selectively connecting and disconnecting a plurality of sense amplifiers to and from a first bit line, and a data read start from the memory cell connected to a first bit line in the memory cell area Before the first bit line is precharged to the ground potential, and when data reading from the memory cell is started. It is characterized by comprising a precharge circuit for releasing the pre-charge.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a multi-valued FRAM according to the present invention will be described in detail with reference to the drawings. The FRAM cells used in the multi-valued FRAM of the present invention each use a ferroelectric film as an inter-electrode insulating film, have substantially different capacitance values, and have a plurality of terminals each having one end commonly connected. A capacitor, and at least one switch element having one end connected to a common connection node at one end of each of the plurality of capacitors.

In the FRAM cell having such a configuration, multi-value data of four or more values is stored by storing n (≧ 4) polarization amounts as information in a plurality of capacitors.

Hereinafter, a four-valued FRAM capable of storing four-valued data will be described as a first embodiment of the multi-valued FRAM of the present invention. FIG. 1 is an equivalent circuit diagram showing an example of one FRAM cell used in a four-valued FRAM.

This FRAM cell has a capacitance ratio of 1: 2.
Is a memory cell of a one-transistor / two-capacitor configuration in which one end node of one MOS transistor Q is connected to one end node of each of the cell capacitors CA and CB.

In order to set the capacitance ratio of the cell capacitors CA and CB to 1: 2, usually, the ratio of the facing area (area of the ferroelectric thin film) between the capacitor electrodes is set to 1: 2. However, the thickness of the ferroelectric thin film may be set to 2: 1.

The one-transistor, two-capacitor type F
The transistor Q of the RAM cell has a gate connected to the word line WL.
Are connected, and the bit line BL is connected to the node on the other end side. The plate electrodes on the other end sides of the two cell capacitors CA and CB correspond to the first plate line PLA and the second plate line, respectively. Connected to PLB.

FIG. 2 shows "0" of the FRAM cell shown in FIG.
Read, "1" Cell capacitor C to explain the read operation
A hysteresis curves corresponding to A and CB are shown, in which A0, A1, A2 and A3 are the residual polarization amounts of the cell capacitor CA, and B0, B1, B2 and B3 are the cell capacitors C
4 shows the amount of remanent polarization of B.

Here, since the area ratio of the ferroelectric thin film of the cell capacitors CA and CB is 1: 2, the potential difference (VPLA-VBL) between each plate line and bit line,
When (VPLB-VBL) is equal, the polarization charge amount is also 1:
It becomes 2.

<First Embodiment> FIG. 3 shows a schematic configuration of a main part of a four-valued FRAM according to a first embodiment, and particularly shows a circuit connection of a memory cell array and a part of peripheral circuits.

In FIG. 3, reference numeral 10 denotes a memory cell area for storing multi-value data, and 12k (k = 0, 1, 2) denotes a sense amplifier (k) for comparing and amplifying the multi-value data read from the memory cells to the bit lines. S / A) area.

The sense amplifier region 12k is divided into a plurality of (three in this example) regions each including one sense amplifier S / Ak in order to compare and amplify multi-value data at one time. The three sense amplifier regions 12k are sequentially arranged in the first sense amplifier region 12k from the memory cell region 10 side.
0, the second sense amplifier area 121, and the third sense amplifier area 122.

(BL0, BBL0), (BL1, BBL)
1) and (BL2, BBL2) are bit line pairs in the divided three sense amplifier regions 12k, and all have substantially the same capacitance.

In the memory cell region 10, in addition to the memory cell array MCA in which the memory cells MC as shown in FIG.
It includes a precharge / equalize circuit section 11 for precharge / equalize L and BBL.

In the memory cells MC in the same column in the memory cell region 10, the node at the other end of the transistor Q is connected to the bit line BL or BBL. The gates of the switching element transistors Q of the cells MC in the same row in the memory cell region 10 are commonly connected to the word line WL.
i (representatively, only two of WL0 and WL1 are shown).

The plate electrodes of the cell capacitors CA of the cells MC in the same row are commonly connected to the first plate line PL.
i0 (typically, only two of PL00 and PL10 are shown), and the plate electrode of the cell capacitor CB of the cell MC in the same row is commonly connected to the second plate line P
Li1 (only two of PL01 and PL11 are shown) is connected. These plate lines PLi0, P
Li1 is arranged substantially parallel to the word line WLi.

The precharge / equalize circuit section 11
Is the bit line precharge potential (ground potential Vs in this example)
s) and an NMOS transistor QN for bit line precharging connected between the Vss line to which the s) is applied and the bit line pair BL and BBL in the memory cell region 10, and connected between the bit line pair BL and BBL. An NMOS transistor QE for equalizing the bit line potential, and is controlled by a precharge / equalize control signal EQ.

A plurality of word lines WLi in the memory cell region 10 are connected to one word line (for example, WL) by a word line selection circuit (not shown) based on an address signal.
0) is selected and the word line drive voltage VWLi is supplied.

A plurality of plate lines PLi0 and PLi1 in the memory cell region 10 are selected from a pair of plate lines (for example, PL00 and PL01) by a plate line selection circuit (not shown) based on an address signal. A plate line voltage is supplied as described below.

The memory cell region 10 and the three sense amplifier regions 12k are located between the bit line pair BL, BBL of the memory cell region 10 and the bit line pair BL0, BBL0 of the first sense amplifier region 120, respectively. It is separated by one inserted NMOS transistor QS for dividing the sense amplifier region, and is selectively disconnected by a control signal φt applied to the gate of the transistor QS.

The first sense amplifier area 120
The bit line pair BL0, BBL0 of the second sense amplifier region 121 and the bit line pair BL1, BBL1 of the second sense amplifier region 121 each have one NM for dividing the sense amplifier region inserted between them.
The connection is separated by an OS transistor QS, and the connection and disconnection are selectively performed by a control signal φt applied to the gate of the transistor QS.

Similarly, the second sense amplifier region 12
One bit line pair BL1 and BBL1 and the bit line pair BL2 and BBL2 of the third sense amplifier region 122 are connected to each other by one N for dividing the sense amplifier region.
The connection is selectively performed by a control signal φt which is divided by a MOS transistor QS and applied to the gate of the transistor QS.

FIG. 4 is a circuit diagram showing a specific example of one of the three sense amplifier regions 12k (k = 0, 1, 2) in the multi-level FRAM of FIG. In the sense amplifier area 12k, a sense amplifier S / Ak
In addition to itself, a dummy cell part DCA for creating a reference potential
k and a column selection gate CGk.

The sense amplifier S / Ak determines the potential of the bit line connected to the selected memory cell (cell data read potential) and the potential of the bit line connected to the selected dummy cell (reference potential). Transistor S / A for bit line potential sensing for comparing and amplifying
It comprises PMOS transistors S / Ap0 and S / Ap1 for restoring bit line potentials for restoring n0, S / An1 and bit line potentials to power supply potential Vcc.

The NMOS transistor S / An
0, S / An1 is given a ground potential (= 0V) /
The NMOS transistor TN is connected to the SAN line via an activation control NMOS transistor TN.
When the NMOS drive signal / SANDr in the sense amplifier applied to the gate of the gate is 0 V, the NMOS drive signal / SANDr is inactive.
When Dr becomes Vcc, it is controlled to the active state.

Further, the PMOS transistor S / Ap
0, S / Ap1 are connected to an SAP line to which a power supply potential Vcc is applied via a PMOS transistor TP for activation control, and a PMOS drive signal SAPD in the sense amplifier applied to the gate of the PMOS transistor TP.
When r is Vcc, it is inactive, and when SAPDr becomes 0V, it is activated.

The dummy cell portion DCAk of each sense amplifier region 12k has a dummy cell (described later) for generating a reference potential connected to each of the bit lines BLk and BBLk one by one in the sense amplifier region 12k.

Dummy cells in the same row of the memory cell array are connected to a pair of dummy word lines DWL and / DWL selected by a dummy word line circuit (not shown).
It is connected to the.

In this case, if one word line selected in the memory cell region 10 is, for example, WL0,
To select a dummy cell connected to a complementary bit line BBLk paired with a bit line BLk connected to a cell MC selected by the word line WL0, a dummy word line DWL is selected and a reference potential is selected. Is supplied.

Here, it should be noted that the dummy cell portion DCAk generates a different reference potential for each sense amplifier region 12k. That is, assuming that the n-value signal potential read to the bit line (for example, BLk) of the sense amplifier area 12k is Vk (where 0 ≦ k ≦ (n−1), Vk <V (k + 1)). , Different reference potentials Vref k (0 ≦ k ≦ (n−2), Vre used in the (n−1) sense amplifiers S / Ak).
fk <Vref (k + 1)) is Vk <Vrefk <V (k + 1). In this case, for example, Vref k = (Vk + V (k + 1))
/ 2.

In this embodiment, the bit lines BLk and BB
As a dummy cell connected corresponding to Lk, a switching NMOS transistor Qd (one equivalent to the cell switching NMOS transistor Q) having one end connected to the bit line BLk or BBLk, An NMOS transistor Qc for supplying a dummy cell reference potential, one end of which is connected to the other end.

The gate of the transistor Qd is connected to a corresponding dummy word line DWL or / DWL. The transistor Qc has a gate connected to a dummy cell write control signal line DCP, and the other end connected to a dummy cell reference potential VD.
Ck is given.

Then, during a predetermined period before the dummy word line DWL or / DWL is selected, the dummy cell write control signal line DCP is activated and the transistor Qc for supplying the dummy cell reference potential is controlled to the ON state. Charge is written to a connection node between transistors Qc and Qd.

The column selection gate CGk of the sense amplifier region 12k includes a pair of data line pairs DQk and / DQk provided in common for a plurality of columns and a corresponding bit line pair BLk, NMOS transistors QGk0 and QGk0 connected to BBLk, respectively.
Gk1 and a pair of bit lines BLk, B in a desired column.
The switch is controlled by a column selection signal CSL for selecting BLk, and the sense amplifier S / A of the corresponding column is selected.
bit line pair BLk, BBLk after comparative amplification by k
Is transferred to the corresponding data line pair DQk, / DQk.

Further, each sense amplifier region 12k shown in FIG.
Some of the bit line pairs BL and B in the memory cell region 10
A rewrite potential supply circuit for supplying a rewrite potential to BL is provided.

This rewrite potential supply circuit is used to rewrite multivalued data into a memory cell.
0 bit line pair BL, BBL connected to a pair of rewrite potential supply lines 13, 13B, and a first rewrite potential VR.
First to fourth rewriting potential lines 130 to 133 supplied with W0 to fourth rewriting potential VRW3
And a PMOS transistor P0 for supplying a rewrite potential to the pair of rewrite potential supply lines 13 and 13B.
To P5 and NMOS transistors N0 to N5.

Here, the first rewrite potential VRW0 (=
0V) are applied between the first rewrite potential line 130 and the pair of rewrite potential supply lines 13 and 13B, and the transistors P0 and P3 are connected to the first rewrite potential selection circuit. Make up.

In this case, the transistors P0 and P
3 is a first sense amplifier region 12 corresponding to each gate.
It is controlled by the potential of the 0 bit line pair BL0, BBL0. The transistors P1 and N0 connected in series between the second rewriting potential line 131 to which the second rewriting potential VRW1 (= Vcc pulse potential) is applied and one of the rewriting potential supply lines 13 and The transistors P4 and N3 connected in series between the second rewriting potential line 131 and the other rewriting potential supply line 13B constitute a second rewriting potential selection circuit.

In this case, the NMOS transistor N0
And N3 are controlled by the potentials of bit line pairs BL0 and BBL0 of the first sense amplifier area 120 corresponding to the respective gates, and the PMOS transistors P1 and P4
Indicates that each gate corresponds to the second sense amplifier region 121
Is controlled by the potential of the pair of bit lines BL1 and BBL1.

The third rewrite potential VRW2 (= V
cc pulse potential) to be applied to the third rewriting potential line 13
2 and one of the transistors P2 and N1 connected in series between one rewriting potential supply line 13 and the third rewriting potential line 132 and the other rewriting potential supply line 13B connected in series. The transistors P5 and N4 constitute a third rewriting potential selection circuit.

In this case, the NMOS transistor N1
N4 and N4 have their gates correspondingly controlled by the potentials of bit line pairs BL1 and BBL1 in the second sense amplifier region 121, and are connected to the PMOS transistors P2 and P5.
Indicate that each gate corresponds to the third sense amplifier region 122
Is controlled by the potential of the bit line pair BL2 and BBL2.

Then, the fourth rewrite potential VRW3 (=
Vcc pulse potential) applied to the fourth rewriting potential line 1
Transistors N2 and N5 correspondingly connected between the pair 33 and the pair of rewrite potential supply lines 13 and 13B are the fourth transistors.
In the rewriting potential selection circuit.

In this case, the NMOS transistor N2
N5 and N5 are controlled by the potentials of the bit line pair BL2 and BBL2 in the third sense amplifier region 122 corresponding to each gate.

FIG. 5 (a) shows a binary 2-bit I / O in the four-valued FRAM shown in FIG. 1 in which three sets of data line pairs DQk and / DQk shown in the sense amplifier area 12k shown in FIG. FIG. 5B is a circuit diagram showing an example of a first data conversion circuit for converting the data into line pair data. FIG. 5B is a truth table showing the operation of the circuit shown in FIG.

In FIG. 5 (a), two-input NAND circuits 41 to 46 and inverter circuits 47 to 50 are arranged as shown in FIG.
Logically connected to realize the operation of the truth table shown in FIG.

FIG. 6 (a) shows the I / O line pair data input in the binary 2-bit format in the four-valued FRAM of FIG.
The data line pair DQ shown in the sense amplifier region 12k of FIG.
FIG. 6B is a circuit diagram showing an example of a second data conversion circuit for converting data into three sets of data k and / DQk. FIG. 6B is a truth table showing the operation of the circuit shown in FIG.

In FIG. 6A, two-input NAND circuits 61 and 67, two-input NOR circuits 63 and 65, and inverter circuits 62, 64, 66 and 68 correspond to the truth table shown in FIG. Logically connected so as to realize the operation.

FIG. 7 shows the multi-value FR of FIG. 1 according to the first embodiment.
6 is a timing chart showing voltage waveforms of a read / rewrite operation of quaternary data in AM. In FIG.
The bit line precharge / equalize signal EQ, the sense amplifier region dividing transistor control signal φt, the selected word line (for example, WL0), and the selected dummy word line (for example, D
WL), the selected first plate line (eg, PL0
0), the selected second plate line (eg, PL0
1), the sense amplifier PMOS drive signal SAPDR, the sense amplifier NMOS drive signal / SANDr, the column selection signal CSL, the bit line pairs (BL0, BBL0), (BL1, BBL1) of the sense amplifier regions 120 to 122,
(BL2, BBL2) and the rewrite potential VRW0
An example of each voltage waveform of VRW3 is shown.

FIGS. 8A, 8B through 11A,
(B) shows the reading / reading of each quaternary data according to the first embodiment.
FIG. 14 is a diagram showing a voltage VPLA-VBL or VPLB-VBL between a plate electrode and a bit line and a hysteresis curve of two cell capacitors CA and CB of an FRAM cell during a rewrite operation.

Here, the data of the cell capacitor CA is "
The charge amount at the time of "0" is Q0, and the data of the cell capacitor CA is "
The charge amount at the time of 1 "is represented by Q1, and the cell capacitors CA,
Since the capacitance ratio of CB is 1: 2, the charge amount when the data of the cell capacitor CB is "0" is represented by 2Q0, and the charge amount when the data of the cell capacitor CB is "1" is represented by 2Q1.

There are four combinations of charge amounts according to the data states of the cell capacitors CA and CB.
Q in ascending order of the total charge of the cell capacitors CA and CB
00, Q01, Q10, and Q11, and the four-valued data are represented as "0", "1/3", "2/3", and "1", respectively, for the sake of convenience in ascending order of the total charge. I will call it.

At this time, FIG. 8 to FIG.
, "1/3", "2/3", and "1" each show a hysteresis curve of the two cell capacitors CA and CB during a read / rewrite operation for each case. .

Next, the operation of reading / rewriting quaternary data from the memory cell MC in FIG. 1 will be described with reference to the timing chart of FIG. 7 and the hysteresis curves of FIGS. 8 to 11.

(1) In the standby state, the signal EQ is in the active state (“H” level, Vcc in this example), the precharge / equalize circuit unit 11 is in the on state, and the bit line pair in the memory cell region 10 is BL and BBL are at the ground potential V
Equalized to ss.

At this time, the three pairs of sense amplifier region dividing transistors QS are controlled to be on by the signal φt, and the sense amplifier regions 120 to 1 are controlled.
22 bit line pairs BL0, BBL0-BL2, BBL2
Is precharged to Vss.

In the standby state, the cell capacitors CA,
The state of polarization of the CB is at the point (1) shown in the hysteresis curves of FIGS. (2) When starting the read / rewrite operation,
The signal EQ is deactivated (“L” level, 0 V) to turn off the precharge / equalize circuit unit 11, cancel the equalization of the bit line pair BL and BBL in the memory cell region 10 and put the bit line pair in a floating state To

(3) Next, the selected word line WL0 is raised to the boosted potential. Thereafter, by applying a Vcc potential to each of the selection plate lines PL00 and PL01, the polarization amount of the cell capacitors CA and CB is read out to the bit line BL as a charge amount.

At this time, as shown in Table 1 below, four kinds of charge amounts corresponding to the directions of polarization of the cell capacitors CA and CB and a bit line potential determined by the bit line capacitance CB appear. FIG. 7 shows the bit line potential when the data of the cell capacitors CA and CB are both “1” and the data “1” of the quaternary data is read.

[0090]

[Table 1]

In this state, the cell capacitors CA, CB
Is at the point (2) shown in the hysteresis curves of FIGS. (4) The data appearing on the bit line has three sense amplifiers S
/ Ak, the three pairs of sense amplifier region dividing transistors QS are turned off by the signal φt to control the bit line pairs (BL0, BBL0), (BL1,. BBL1), (BL
2, BBL2).

Next, a dummy word line (DW in this example) corresponding to a dummy cell connected to the bit lines BBL0, BBL1, and BBL2 of each sense amplifier region 12k.
The potential L) is raised, and the reference charge is read from the selected dummy cell.

Here, in each sense amplifier region 12k, bit lines BBL0, BBL1, B
The reference potentials Vrefk read to BL2 are all different and are as shown in Table 2 below.

[0094]

[Table 2]

Next, the drive signal SAPDr is set at "L" level and the drive signal / SANDr is set at "H" level to drive the sense amplifiers S / Ak to drive the three sense amplifiers S / Ak.
Comparatively amplified by Ak. The results are as shown in Table 3 below.

[0096]

[Table 3]

That is, as shown in Table 3, the three sets of sense amplifiers S / Ak convert one set of quaternary data read from the selected cell into three sets of binary data. Become.

(5) Next, in each of the divided sense amplifier regions 12k, the column selection signal CSL is activated (= Vcc) to activate the column selection gate CG.
k0 and CGk1 are turned on and the corresponding data line pair DQ
The data of the sense amplifier S / Ak is transferred to k and / DQk.

The data of the three pairs of data lines DQk and / DQk are converted by the 3-bit / 2-bit data conversion circuit shown in FIG. 5A into two-value data as shown in the truth table shown in FIG. Bit data is converted to binary data and output to the outside through two sets of input / output data lines I / O0, / I / O0, I / O1, and / I / O1.

(6) Next, by the rewriting potential supply circuit,
A potential (rewrite potential) VRW0 for rewriting the memory cell to the bit line (BL in this example) of the memory cell region 10 through the rewrite supply potential line 13 or 13B.
Give any of VRW3.

When the rewriting potential is supplied, the polarization state of the cell capacitors CA and CB is at the point (3) shown in the hysteresis curves of FIGS. (7) Next, the rewriting operation of the four-level data will be described with reference to Table 4 below.

Table 4 shows quaternary data "0", "1/3", "2/3".
, "1", the total charge amount of the two cell capacitors CA and CB, the rewrite potential supply transistors P0-P2 and N0-N2 in the sense amplifier region S / Ak.
And the relationship between the rewrite potentials VRW0 to VRW3 supplied to the rewrite potential supply line 13 are shown. Here, the asterisks indicate the ON states of the transistors that contribute to the supply of the rewrite potential.

[0103]

[Table 4]

(7-1) The case where the total charge amount Q00 (data "0") is read will be described with reference to the hysteresis curve of FIG. Initially, the polarization states of the cell capacitors CA and CB correspond to the point (1) shown in the hysteresis curve of FIG. By the comparison amplification by the sense amplifier S / Ak after reading the data "0", the bit lines BL0, BL1, BL2 of each sense amplifier area 12k become "0". At this stage, the polarization state of the cell capacitors CA and CB corresponds to the point (2) shown in the hysteresis curve of FIG.

At this point, the column selection signal CSL is activated, and the data line pairs (DQ0, / DQ0), (DQ1,
DQ1) and (DQ2, / DQ2) corresponding to data (0,
1), (0,1), (0,1) are output.

Thereafter, the data is converted into 2-bit binary data by the data conversion circuit shown in FIG. 5A, and two sets of input / output data lines (I / O0, / I / O0), (I / O1, / I
/ O1) outputs (0,1) and (0,1) to the outside of the chip.

At this time, the bit line pairs (BL0, BBL0), (BL1, BBL) in each sense amplifier region 12k
1), (BL2, BBL2) correspond to (0,1), (0,1),
Since it is (0, 1), only the first rewrite potential selection circuit (transistor P0) of the first to fourth rewrite potential selection circuits is turned on, and the rewrite potential VRW0 becomes the transistor P0. Is supplied to the rewrite supply potential line 13 through

Since the rewrite potential VRW0 is constant at 0 V, in this state, the cell capacitors CA and CB
Are both at the point (3) shown in the hysteresis curve of FIG.

Subsequently, the potential of the first plate line PL00 is lowered to 0 V, and then the first plate line PL00 is temporarily boosted to Vcc / 2 for the reason described in the section (7-3). During this time, since 0 V is supplied to the bit line, Vcc / 2 is applied between the electrodes of the cell capacitor CA.

Subsequently, the potential of the second plate line PL01 is lowered to 0V. At this point, the cell capacitor C
The polarization states of A and CB are both at the point (4) shown in the hysteresis curve of FIG.

After that, the potential of the first plate line PL00 is also returned to 0V. At this stage, the cell capacitors CA, CB
The state of polarization of point (1) shown in the hysteresis curve of FIG.
Return to

In addition to the first plate line PL00, the potential of word line WL0 and dummy word line DWL
The potential of 0 is returned to the original value of 0 V, the sense amplifier S / Ak is deactivated, the precharge / equalize circuit unit 11 is turned on, and the memory cell dividing transistor QS is turned on to set a standby state.

That is, FIG. 8 and FIGS.
, Point (1) is the initial state, point (2) is the plate line PL
00, PL01 are driven, point (3) is the state when the rewrite potential is supplied, and point (4) is the plate line P.
The potential of L00 rises to Vcc / 2 and plate line PL01
Corresponds to the state when the potential of the pixel has dropped to 0V.

(7-2) The case where the total charge amount Q10 (data "1/3") is read will be described with reference to the hysteresis curve of FIG. Initially, the polarization states of the cell capacitors CA and CB correspond to the point (1) shown in the hysteresis curve of FIG. Sense amplifier S / A after reading data "1/3"
By the comparison amplification by k, in the sense amplifier area 120 where k = 0, the bit line BL0 side becomes "1", and k = 1,
In the second sense amplifier regions 121 and 122, the bit lines BL1 and BL2 side become "0". At this stage, the polarization states of the cell capacitors CA and CB both correspond to the point (2) shown in the hysteresis curve of FIG.

At this point, the column selection signal CSL is activated, and the data line pairs (DQ0, / DQ0), (DQ1,
DQ1) and (DQ2, / DQ2) corresponding to data (1,
0), (0,1), (0,1) are output.

Thereafter, the data is converted into 2-bit binary data by the data conversion circuit shown in FIG. 5A, and two sets of input / output data lines (I / O0, / I / O0), (I / O1, / I
(1, 0) and (0, 1) are output to the outside of the chip via / O1).

At this time, the bit line pairs (BL0, BBL0), (BL1, BBL) in each sense amplifier region 12k
1), (BL2, BBL2) correspond to (1,0), (0,1),
Since it is (0, 1), only the second rewriting potential selection circuit (transistors N0 and P1) of the first to fourth rewriting potential selection circuits is turned on, and the rewriting potential VRW
1 is supplied to the rewrite supply potential line 13 through the transistors N0 and P1. At this time, another transistor P
2 also turns on, but since the transistor N1 connected in series with it turns off, the rewrite potential VRW2
Is not supplied to the rewriting supply potential line 13.

At this point, the cell capacitors CA, CB
Are both at the point (3) shown in the hysteresis curve of FIG. When the potential of the first plate line PL00 is reduced while the rewrite potential VRW1 is being supplied, the rewrite potential VRW1 is reduced to 0 V, and the polarization in the direction from the bit line to the plate line is applied to the cell capacitor CA. ("1" data) is rewritten. At this stage, the polarization states of the cell capacitors CA and CB correspond to the point A1 shown in the hysteresis curve of FIG.
, At B3.

On the other hand, the rewriting potential VRW1 is set to 0V
Then, when the potential of the second plate line PL01 is lowered, the polarization ("0" data) in the direction of the bit line from the plate line is rewritten in the cell capacitor CB.
However, the first plate line PL00 is temporarily boosted to Vcc / 2 for the reason described later in the section (7-3). In this state, the polarization states of the cell capacitors CA and CB are both at the point (4) shown in the hysteresis curve of FIG.

Thereafter, the potential of the first plate line PL00, the potential of the word line WL0 and the dummy word line DW
The potential of L0 is returned to the original 0 V, the sense amplifier S / Ak is deactivated, and the precharge / equalize circuit 11
Is turned on, and the memory cell dividing transistor QS is turned on to set a standby state. At this stage, the polarization states of the cell capacitors CA and CB both return to the point (1) shown in the hysteresis curve of FIG.

(7-3) The case where the total charge amount Q01 (data "2/3") is read will be described with reference to the hysteresis curve of FIG. Initially, the polarization states of the cell capacitors CA and CB correspond to the point (1) shown in the hysteresis curve of FIG. Sense amplifier S after reading data "2/3"
/ Ak, the bit lines BL0 and B0 in the sense amplifier regions 120 and 121 where k = 0 and k = 1.
The L1 side becomes "1", and the bit line BL2 side becomes "0" in the sense amplifier region 122 where k = 2. At this stage, both the polarization states of the cell capacitors CA and CB are as shown in FIG.
Corresponds to the point (2) shown in the hysteresis curve of FIG.

At this point, the column selection signal CSL is activated, and the data line pairs (DQ0, / DQ0), (DQ1,
DQ1) and (DQ2, / DQ2) corresponding to data (1,
0), (1,0), (0,1) are output.

Thereafter, the data is converted into 2-bit binary data by the data conversion circuit shown in FIG. 5A, and two sets of input / output data lines (I / O0, / I / O0), (I / O1, / I
(0,1) and (1,0) are output to the outside of the chip via / O1).

At this time, bit line pairs (BL0, BBL0), (BL1, BBL) in each sense amplifier region 12k
1), (BL2, BBL2) correspond to (1,0), (1,0),
Since it is (0, 1), only the third rewriting potential selection circuit (transistors N1 and P2) of the first to fourth rewriting potential selection circuits is turned on, and the rewriting potential VRW
2 is supplied to the rewrite supply potential line 13 through the transistors N1 and P2. At this time, another transistor N
0 also turns on, but since the transistor P1 connected in series to it is off, the rewrite potential VRW1
Is not supplied to the rewriting supply potential line 13.

At this point, the cell capacitors CA, CB
Are both at the point (3) shown in the hysteresis curve of FIG. If the potential of the first plate line PL00 is lowered while the rewrite potential VRW2 is still 0 V, the polarization ("0" data) in the bit line direction from the plate line is rewritten to the cell capacitor CA. At this stage, the polarization states of the cell capacitors CA and CB correspond to the point A shown in the hysteresis curve of FIG.
3, I'm at B2.

Thereafter, when the potential of the second plate line PL01 is lowered while the rewrite potential VRW2 is supplied, the rewrite potential VRW2 is lowered to 0V. The polarization ("1" data) in the direction of the plate line is rewritten. However, once the first plate line PL00 is stepped up to Vcc / 2, the polarization of the cell capacitor CA in the direction from the bit line to the plate line is prevented from being rewritten. In this state, the polarization states of the cell capacitors CA and CB are both the points shown in the hysteresis curve of FIG.
You are in (4).

Thereafter, the potential of the first plate line PL00, the potential of the word line WL0 and the dummy word line DW
The potential of L0 is returned to the original 0 V, the sense amplifier S / Ak is deactivated, and the precharge / equalize circuit 11
Is turned on, and the memory cell dividing transistor QS is turned on to set a standby state. At this stage, the polarization states of the cell capacitors CA and CB both return to the point (1) shown in the hysteresis curve of FIG.

(7-4) The case where the total charge amount Q11 (data "1") is read will be described with reference to the hysteresis curve of FIG. Initially, the polarization states of the cell capacitors CA and CB correspond to the point (1) shown in the hysteresis curve of FIG. Sense amplifier S / A after reading data "1"
k, each sense amplifier region 12k
Bit line BL0, BL1, BL2 side becomes "1". At this stage, the polarization states of the cell capacitors CA and CB are
Both correspond to the point (2) shown in the hysteresis curve of FIG.

At this point, the column selection signal CSL is activated, and the data line pair (DQ0, / DQ0), (DQ1,
DQ1) and (DQ2, / DQ2) corresponding to data (1,
0), (1,0), (1,0) are output.

Thereafter, the data is converted into 2-bit binary data by the data conversion circuit shown in FIG. 5A, and two sets of input / output data lines (I / O0, / I / O0), (I / O1, / I
(1, 0) and (1, 0) are output to the outside of the chip via / O1).

At this time, the bit line pairs (BL0, BBL0), (BL1, BBL) in each sense amplifier region 12k
1), (BL2, BBL2) correspond to (1,0), (1,0),
Since it is (1, 0), only the fourth rewriting potential selection circuit (transistor N2) of the first to fourth rewriting potential selection circuits is turned on, and the rewriting potential VRW3 is set to the level of the transistor N2. Is supplied to the rewrite supply potential line 13 through At this time, the transistors N0 and N1 are also turned on, but the transistor P connected in series with N0 is also turned on.
1 is off, the rewrite potential VRW1 is not supplied to the rewrite supply potential line 13, and
The rewrite potential VRW2 is not supplied to the rewrite supply potential line 13 because the transistor P2 connected in series to the P1 is off.

At this point, the cell capacitors CA, CB
Are both at the point (3) shown in the hysteresis curve of FIG. When the potential of the first plate line PL00 is reduced while the rewrite potential VRW3 is being supplied, the rewrite potential VRW3 is reduced to 0 V, and the polarization in the direction from the bit line to the plate line is applied to the cell capacitor CA. ("1" data) is rewritten.

Thereafter, when the potential of the second plate line PL01 is lowered while the rewrite potential VRW3 is supplied again, the rewrite potential VRW3 is lowered to 0V. Then, the polarization ("1" data) in the direction of the plate line is rewritten. However, as described in the section (7-3), the first plate line PL00 is temporarily boosted to Vcc / 2. In this state,
The polarization states of the cell capacitors CA and CB are shown in FIG.
It is at point (4) shown in the hysteresis curve of No. 1.

Thereafter, the potential of the first plate line PL00, the potential of the word line WL0, and the potential of the dummy word line DW
The potential of L0 is returned to the original 0 V, the sense amplifier S / Ak is deactivated, and the precharge / equalize circuit 11
Is turned on, and the memory cell dividing transistor QS is turned on to set a standby state. At this stage, the polarization states of the cell capacitors CA and CB both return to the point (1) shown in the hysteresis curve of FIG.

In the four-valued FRAM of the above embodiment, the area of the ferroelectric film of each of the two cell capacitors CA and CB in each memory cell is made different so that the cell capacitor C
"0" data and "1" data between A and CB can be distinguished from each other.
The four-valued data can be read out only by performing the operation multiple times.

In other words, the multi-valued FRAM of the present invention uses a ferroelectric film as an inter-electrode insulating film, has substantially different capacitance values, and has a plurality of capacitors each having one end commonly connected. And at least one capacitor having one end connected to a common connection node on one end of each of the plurality of capacitors.
A memory cell array formed by two-dimensionally arranging memory cells constituted by the switch elements.

With such a configuration, “0” data and “1” between a plurality of cell capacitors in each memory cell are set.
Multi-valued polarization of four or more values can be easily stored in a state where data can be distinguished from each other, and the data can be read out by a single readout operation of the cell. A multi-valued FRAM which is inexpensive and can speed up the cell data reading operation can be realized.

In the above (7-1) to (7-4), the data rewriting operation has been described. However, in the case of writing data input from outside the chip, the following control may be performed. That is, two sets of input / output data lines (I / I /
O0, / I / O0) and 2-bit binary data input via (I / O1, / I / O1) are converted into three sets of binary data as shown in the truth table shown in FIG. The data is converted into value data and output to three data line pairs DQk and / DQk.

At the time of comparison and amplification by the sense amplifier S / Ak when reading the cell data, the column selection signal C is applied to each of the divided sense amplifier regions 12k.
By activating SL, the column selection gate CG is turned on, and the corresponding bit line pair (BL) in each sense amplifier region 12k is switched from the data line pair DQk, / DQk.
0, BBL0), (BL1, BBL1), (BL2, B
BL2), and thereafter the bit lines BL and BB in the memory cell area are written in the same manner as in the rewrite operation.
What is necessary is just to supply a quaternary potential to L.

In the above embodiment, the cell capacitor C
Although the capacitance ratio of A and CB is 1: 2, the cell capacitor C
A and CB data "0" and "1" may be distinguished from each other, and the capacity ratio does not necessarily have to be 1: 2.

In the above embodiment, the case where two memory cells are connected to one transistor to form one memory cell has been described. However, three or more memory cells may be connected to one transistor. The case where one memory cell is formed by connection can also be implemented according to the above-described embodiment.

The multi-level FRAM according to the present invention is not limited to the above-described embodiment, but may employ a general configuration as described below. (1) In the sense amplifier region, the node supplying the lowest potential and the bit line among the potential generating circuits supplying the different n potentials for rewriting to the memory cell have the most gates. It is connected via a PMOS transistor connected to one node of a sense amplifier having a low reference potential.

(2) In the sense amplifier region, the node and the bit line that supply the highest potential among the potential generation circuits that supply different n potentials for rewriting to the memory cell are as follows: The gate is connected via an NMOS transistor connected to one node of the sense amplifier having the highest reference potential.

(3) The x-th (2 ≦ x ≦ n−1) potential among the potential generating circuits that supply n different potentials for rewriting to memory cells in the sense amplifier region And the bit line are connected to an NMOS transistor whose gate is connected to one node of the sense amplifier having the (x−1) th reference potential and a gate of which is connected to one node of the sense amplifier having the xth reference potential. Connected P
It is connected via a MOS transistor.

(4) The PMOS transistor connected to the sense amplifier to which the x-th reference potential is input is:
The N-th adjacent to the PMOS transistor connecting the x-th rewrite potential generating circuit and the bit line, and connected to the sense amplifier to which the x-th reference potential is input.
The MOS transistor is adjacent to the NMOS transistor that connects the bit line with the (x + 1) th rewriting potential generation circuit.

(5) At least one or more (n-1) sense amplifiers are connected to both ends of the bit line. At this time, if (n-1) is an even number, connect (n-1) sense amplifiers to both ends of the bit line by (n-1) / 2 each, and if (n-1) is an odd number, Has (n-1) sense amplifiers at both ends of the bit line.
Connect n / 2 and (n / 2) -1 each.

[0147]

As described above, according to the present invention, multi-valued data of four or more values can be distinguished between "0" data and "1" data between a plurality of cell capacitors of one FRAM cell. The amount of polarization can be easily stored, and the data can be read by one reading operation of the cell.
A multi-valued ferroelectric memory that can be highly integrated, has low bit cost, and can speed up cell data read operation can be realized.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing an example of one FRAM cell used in a four-valued FRAM.

FIG. 2 shows two ferroelectric cell capacitors CA and FIG. 2 for explaining “0” read and “1” read operations of the FRAM cell of FIG. 1;
FIG. 9 is a characteristic diagram showing a relationship between a potential difference between electrodes corresponding to CB and a polarization amount (representing a hysteresis curve).

FIG. 3 is a circuit diagram schematically showing a schematic configuration of a main part of a quaternary FRAM capable of storing quaternary data according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a specific example by extracting one of three sense amplifier regions 12k in FIG. 3;

FIG. 5 is a diagram showing a binary 2-bit I / O of data of three pairs of data lines DQk and / DQk in the four-valued FRAM of FIG.
1 is a circuit diagram illustrating an example of a data conversion circuit that converts line pair data, and a truth table illustrating the operation thereof.

6 is a diagram showing three pairs of data line pairs DQ and I / O line pairs input in a binary 2-bit format in the four-valued FRAM of FIG. 3;
1 is a circuit diagram illustrating an example of a data conversion circuit that converts data into k and / DQk data, and a truth table illustrating the operation thereof.

FIG. 7 is a timing chart showing an example of a read / rewrite operation in the four-valued FRAM of FIG.

8 is a characteristic diagram illustrating a relationship between a potential change of a bit line and a hysteresis curve of two cell capacitors in a “0” read operation by the operation illustrated in FIG. 7;

9 is a characteristic diagram illustrating a relationship between a potential change of a bit line and a hysteresis curve of two cell capacitors in a “1/3” read operation by the operation illustrated in FIG. 7;

FIG. 10 is a characteristic diagram for explaining a relationship between a potential change of a bit line and a hysteresis curve of two cell capacitors in a “2/3” read operation by the operation shown in FIG. 7;

FIG. 11 is a characteristic diagram illustrating a relationship between a potential change of a bit line and a hysteresis curve of two cell capacitors in a “1” read operation by the operation illustrated in FIG. 7;

FIG. 12 is an equivalent circuit diagram showing a configuration example of a conventional binary data storage FRAM cell.

13 is a hysteresis curve of “0” reading and “1” reading corresponding to the cell capacitor in FIG.

FIG. 14 is an equivalent circuit diagram showing a conventional example of an FRAM cell for storing multilevel data.

[Explanation of symbols]

10: memory cell area, MC: 1 transistor Q, 2 capacitor C type memory cell, MCA: memory cell array, BL, BBL: bit line pair of memory cell area, WL0, WL1 ... word line, PL00, PL10 ... first PL01, PL11: second plate line, 11: precharge / equalize circuit section, 12: sense amplifier area, S / Ak: sense amplifier, BL0, BBL0 to BL2, BBL2: bit line of sense amplifier area DCAk: Dummy cell portion, DWL0, / DWL0: Dummy word line, Qd: NMOS transistor for dummy switch, Qc: NMOS transistor for supplying dummy cell reference potential, CG (QGk0, QGk1): Column select gate (NM)
OS transistor), DQk, / DQk: data line pair, 13, 13B: rewriting potential supply line, 130 to 133: rewriting potential line.

Claims (19)

[Claims] 1. A ferroelectric film is used for an inter-electrode insulating film, the capacitance values of the ferroelectric films are substantially different, and a plurality of capacitors each having one end connected in common and each of the plurality of capacitors are connected. A multi-valued ferroelectric memory, comprising: a memory cell array formed by two-dimensionally arranging memory cells each including at least one switch element having one end connected to a common connection node on one end side. . 2. The multi-valued ferroelectric memory according to claim 1, wherein each of said plurality of capacitors includes a ferroelectric thin film having a different area from each other and used as an inter-electrode insulating film. Ferroelectric memory. 3. The multi-valued ferroelectric memory according to claim 1, wherein the plate electrodes on the other ends of the plurality of capacitors can be driven independently of each other. Body memory. 4. The multi-valued ferroelectric memory according to claim 1, wherein at the time of reading n-value data from said memory cell, a plate electrode at each other end of said plurality of capacitors. After driving the switch element to an ON state in a state where a ground potential is applied, by raising the potential of the plate electrode,
A multi-valued ferroelectric memory, further comprising a read control circuit for controlling to read n-value data in the form of n-value charge at the other end of the switch element. 5. The multilevel ferroelectric memory according to claim 4, wherein said read control circuit boosts the potentials of the plate electrodes at the other ends of said plurality of capacitors substantially simultaneously. Multi-valued ferroelectric memory. 6. The multi-valued ferroelectric memory according to claim 1, wherein said memory cell array includes a column connected to a node on the other end of a switch element of said memory cell in each column of said memory cell array. One bit line, plate lines respectively connected to the plate electrodes on the other end sides of the plurality of capacitors, and n-value data read from the memory cell to the first bit line. A sense amplifier region including a plurality of (n-1) sense amplifiers respectively amplifying by comparing with a plurality of different reference potentials; a memory cell region in which the first bit line is connected to the memory cell; A gate control comprising an NMOS transistor inserted at a position for dividing the sense amplifier region and a position for dividing the plurality of sense amplifiers, and applied to each gate; A sense amplifier area dividing switch element for selectively connecting and disconnecting a plurality of sense amplifiers to and from the first bit line by being switch-controlled by the first bit line; and a first bit line in the memory cell area. And a precharge circuit for precharging the first bit line to a ground potential before starting data reading from the memory cell, and canceling the precharge when starting reading data from the memory cell. Characteristic multi-valued ferroelectric memory. 7. The multi-valued ferroelectric memory according to claim 6, wherein when reading n-value data from said memory cell, a plurality of said plurality of memory cells connected to said memory cell are released after precharge by said precharge circuit is released. The switch element is turned on in a state where a ground potential is applied to the plate lines, and the signal charges from the memory cells are transferred to the first bit lines by raising the potentials of the plurality of plate lines to a power supply potential. The multi-valued ferroelectric material is characterized in that, after reading out to generate an n-valued signal potential, the (n-1) sense amplifiers are activated and compared with a plurality of different reference potentials Vrefk. memory. 8. The multi-level ferroelectric memory according to claim 7, wherein the n-level signal potential read to said first bit line is V
k (where 0 ≦ k ≦ (n−1), Vk <V (k + 1)), different reference potentials Vrefk (where 0 ≦ k ≦) used in the (n−1) sense amplifiers. (n-2), Vrefk <Vref (k + 1))
Is a multivalued ferroelectric memory, wherein Vk <Vrefk <V (k + 1). 9. The multi-valued ferroelectric memory according to claim 8, wherein Vrefk is Vrefk = (Vk + V (k + 1)) / 2. 10. The multi-valued ferroelectric memory according to claim 6, wherein at the time of rewriting after reading n-valued data from said memory cells, said (n-1) After the comparison and amplification by the sense amplifier, a potential for rewriting is generated in the first bit line, and the potentials of a plurality of plate lines connected to the memory cell are lowered to the ground potential. A multi-valued ferroelectric memory characterized in that by turning off the element, n-valued data is rewritten in the memory cell in the form of the polarization direction of the plurality of capacitors. 11. The multi-valued ferroelectric memory according to claim 10, wherein the potential of said plate line is lowered to a ground potential, and then the potential of said first bit line is lowered to provide a first capacitor to said capacitor. By rewriting the polarization in the direction from the bit line to the plate electrode, or by keeping the potential of the first bit line at the ground potential before and after decreasing the potential of the plate line, A multi-valued ferroelectric memory in which polarization in a direction toward a first bit line is rewritten. 12. The multi-valued ferroelectric memory according to claim 11, wherein the potentials of said plurality of plate lines are lowered at different timings from each other. 13. The multi-valued ferroelectric memory according to claim 10, wherein a sense amplifier region including said (n-1) sense amplifiers is located between said memory cell and said first memory cell. N different signal potentials which are read and supplied to the bit lines and compared with the different reference potentials, and which supply rewrite potentials for rewriting to the memory cells. And a first bit line in the memory cell region are selectively connected to each other. 14. The multi-valued ferroelectric memory according to claim 13, wherein, among the n rewriting potential lines, the lowest potential among n-level signal potentials to be rewritten to the memory cell is supplied. One rewriting potential line is constant at the ground potential, and the remaining (n-1) rewriting potential lines have polarization in the capacitor in the direction from the first bit line to the plate electrode. In the case of rewriting, a rewriting pulse is supplied in which the potential of the plate line connected to the capacitor falls from the power supply potential to the ground potential after the potential of the plate line drops to the ground potential. When rewriting the polarization in the direction toward the bit line, the ground potential is maintained before and after the potential of the plate line connected to the capacitor falls to the ground potential. Multi-level ferroelectric memory. 15. The multi-valued ferroelectric memory according to claim 14, wherein the capacitor in which the polarization in the direction from the plate electrode to the first bit line is rewritten is a capacitor of the plate line connected to the capacitor. If the potential of the first bit line rises to the power supply potential Vcc after the potential has fallen to the ground potential, the potential of the plate line must rise to Va (0 <Va) before the potential of the first bit line rises. A multi-valued ferroelectric memory characterized in that by increasing by <Vcc), polarization in a direction from the first bit line to the plate electrode is prevented from occurring. 16. The multi-valued ferroelectric memory according to claim 15, wherein said Va is Vcc / 2. 17. The multi-valued ferroelectric memory according to claim 6, wherein said multi-valued ferroelectric memory is paired with said first bit line and connected to said (n-1) sense amplifiers. A second bit line, and (n-1) reference potential generating circuits respectively connected to the respective portions of the second bit line connected to the (n-1) sense amplifiers. And generating the plurality of different reference potentials respectively corresponding to the respective portions of the second bit line connected to the (n-1) sense amplifiers. Multi-valued ferroelectric memory. 18. The multi-valued ferroelectric memory according to claim 6, wherein the binary information after comparison and amplification by said (n-1) sense amplifiers is m (where 2 ^(m-1) ≦ n ≦ 2 ^m ) A multi-valued ferroelectric memory, further comprising a first data conversion circuit for converting into binary information of bits and outputting it to the outside of the chip. 19. The multivalued ferroelectric memory according to claim 6, wherein m (where 2 ^(m−1) ≦ n ^{) is} input from outside the chip.
.Ltoreq.2 ^m ), further comprising a second data conversion circuit for converting binary information of bits into binary information to be supplied corresponding to the (n-1) sense amplifiers. Value ferroelectric memory.