JP2018195359A - Memory cell, memory module, information processing device and error correction method of memory cell - Google Patents

Abstract

To provide a memory cell, a memory module, an information processing device and an error correction method of the memory cell capable of suppressing an increase in latency without requiring a refresh operation after checking writing of data to a memory.SOLUTION: A memory cell comprises: a capacitor 3 including a stacked first electrode 31, a second electrode 32 and a third electrode 33 and capable of accumulating electric charges between the first electrode and the second electrode and between the second electrode and the third electrode; a first transistor 1 including a control terminal G connected to a control line wl, a first terminal S connected to a data signal line bl, and a second terminal D connected to the first electrode 31; and a second transistor 2 including a control terminal G connected to a control line cwl for data checking, a first terminal S connected to the second electrode 32, and a second terminal D connected to a predetermined potential line GND. The third electrode is connected to a signal line cbl for data checking.SELECTED DRAWING: Figure 7

Description

  The embodiments referred to in this application relate to a memory cell, a memory module, an information processing apparatus, and a memory cell error correction method.

  Conventionally, when data is read from a memory (for example, DRAM: Dynamic Random Access Memory), an error detection and correction code (ECC: Error Check and Correct Code, Error Correction Code) is added to prevent errors such as bit inversion due to disturbance. I am trying to correct it.

  By the way, due to the nature of the correction code, there is an upper limit to the number of bits that can be corrected. Is called Uncorrectable Error (UE). The CE and the UE are detected by passing through a circuit (ECCD: ECC Decoder) that checks the ECC at the time of reading.

  Here, the CE can be corrected in the ECCD and transferred to a CPU (Central Processing Unit). However, in the case of the UE, an uncorrectable flag is transmitted from the ECCD to the CPU, and the error data is discarded. Then, the CPU that has received the uncorrectable flag from the ECCD interrupts processing, or re-executes data that has become a UE from memory writing (hereinafter also referred to as UE retry). At this time, the UE retry takes twice as long as the normal data transfer.

  That is, because a common bus is used for writing and reading because of the structure of the memory, for example, reading of UE determination and reading and writing of original data cannot be performed in parallel. Furthermore, since it cannot be determined whether the UE has been written or read, it is required to re-execute from writing to the memory in both the UE at the time of writing and the UE at the time of reading.

  By the way, conventionally, various proposals have been made for memories and memory modules having an improved memory cell structure.

Japanese Patent Laid-Open No. 06-119773 JP 05-152537 A JP 2006-318132 A

  As described above, for example, in order to avoid bus contention between data writing from the CPU to the memory and data reading for UE determination, it is conceivable to provide a data check bus.

  However, for example, when a data error check is performed after data is written to the memory (memory cell), the capacitor charge is discharged, and thus a refresh process is performed. That is, for example, when the CPU reads data from the memory, refresh processing is required twice in total after data check and after normal data read, which may increase latency.

  According to one embodiment, the first electrode, the second electrode, and the third electrode are stacked, and a charge is charged between the first electrode and the second electrode, and between the second electrode and the third electrode. A memory cell is provided having a storable capacitor, a first transistor, and a second transistor.

  The first transistor includes a control terminal connected to a control line, a first terminal connected to a data signal line, and a second terminal connected to the first electrode. The second transistor includes a control terminal connected to a data check control line, a first terminal connected to the second electrode, and a second terminal connected to a predetermined potential line. The third electrode is connected to a data check signal line.

  The disclosed memory cell, memory module, information processing apparatus, and memory cell error correction method have an effect of suppressing an increase in latency without requiring a refresh operation after a data write check on the memory.

FIG. 1 is a circuit diagram showing an example of a memory cell of related technology. FIG. 2 is a block diagram showing an example of a memory cell array to which the memory cell shown in FIG. 1 is applied. FIG. 3 is a block diagram schematically illustrating a configuration example of a general memory module. FIG. 4 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 2 is applied. FIG. 5 is a block diagram showing another example of a memory cell array to which the memory cell shown in FIG. 1 is applied. FIG. 6 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 5 is applied. FIG. 7 is a circuit diagram showing the memory cell of this embodiment. FIG. 8 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. FIG. 9 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. FIG. 10 is a diagram for explaining a data write operation in a memory to which the memory cell shown in FIG. 1 is applied. FIG. 11 is a diagram for explaining a data read operation in a memory to which the memory cell shown in FIG. 1 is applied. FIG. 12 is a diagram for explaining a data write operation in a memory to which the memory cell shown in FIG. 7 is applied. FIG. 13 is a diagram for explaining a data read operation in a memory to which the memory cell shown in FIG. 7 is applied. FIG. 14 is a block diagram illustrating an example of the information processing apparatus according to this embodiment. FIG. 15 is a block diagram illustrating another example of the information processing apparatus according to this embodiment.

  First, before describing embodiments of a memory cell, a memory module, an information processing apparatus, and a memory cell error correction method in detail, an example of a memory cell, a general memory module, and a modification thereof will be described with reference to FIGS. This will be described with reference to FIG.

  FIG. 1 is a circuit diagram showing an example of a memory cell of related technology, and shows an example of a memory cell mc that can avoid bus contention. In other words, the memory cell mc shown in FIG. 1 includes two transistors 101 and 102 and a capacitor 103. For example, a bus conflict between data writing from the CPU to the memory and data reading for UE (uncorrectable error) determination. Try to avoid. Here, the transistors 101 and 102 are each formed by an n-channel MOS transistor, and the capacitor 103 is formed by sandwiching the dielectric layer 133 between the two electrodes 131 and 132, but is not limited thereto. .

  A control line wl is connected to the gate G of the transistor 101, and a data signal line bl is connected to the source S of the transistor 101. In addition, one electrode 131 of the capacitor 103 and the source S of the transistor 102 are connected to the drain D of the transistor 101. Further, the data check control line cwl is connected to the gate G of the transistor 102, and the data check signal line cbl is connected to the drain D of the transistor 102. The other electrode 132 of the capacitor 103 is grounded (GND).

  That is, for example, a data write bus (data signal line bl) and a check bus (data check signal line cbl) from the CPU to the memory (DRAM) are provided in the memory cell mc, which are controlled by the transistors 101 and 102, respectively. Is done.

  FIG. 2 is a block diagram showing an example of a memory cell array to which the memory cell shown in FIG. 1 is applied, and shows a configuration example of a memory array having data check dedicated lines (cbl, cwl). In FIG. 2, only three memory cells mc1 to mc3 are illustrated, but it goes without saying that a large number of memory cells mc are actually arranged in a matrix.

  The memory cell array shown in FIG. 2 performs memory address control for data access by the control lines wl (wl1 to wl3) in the same manner as a normal memory (DRAM). Further, after writing to the memory cells mc (mc1 to mc3) by the data signal lines bl (bl1 to bl3), the data check control lines cwl (cw1 to cw3) and the data check signal lines cbl (cbl1 to cbl3) are performed. ) Check memory. In this way, by dividing the signal line into the data signal line bl and the data check signal line cbl, bus contention is avoided.

  FIG. 3 is a block diagram schematically showing a configuration example of a general memory module, and FIG. 4 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 2 is applied. 3 and 4 schematically show a DIMM (Dual Inline Memory Module). The data signal line bl (data check signal line cbl) is drawn as 11 lines, and the control line wl (data check line) is shown. The control line cwl) is drawn as one line.

  As described with reference to FIGS. 1 and 2, in the memory cell mc capable of avoiding bus contention, four types of signal lines bl, wl, cbl, and cwl are used. Therefore, as shown in FIG. 4, in the memory module to which the memory cell array shown in FIG. 2 is applied, twice as many signal lines are used as compared with the general memory module shown in FIG. Will increase.

  This is not only an increase in the number of pins of the memory module (DIMM) but also, for example, a CPU is required to add a bus in the same manner. Furthermore, even when applied as a built-in memory, it is the same that the bus width is increased, which leads to an increase in cost due to an increase in chip area.

  FIG. 5 is a block diagram showing another example of a memory cell array to which the memory cell shown in FIG. 1 is applied, and shows a memory cell array incorporating a check circuit (checksum generation circuit) CC. FIG. 6 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 5 is applied.

  As is clear from comparison between FIGS. 5 and 6 and FIGS. 2 and 4 described above, in the memory module (DIMM) to which the memory cell array incorporating the check circuit CC is applied, for example, 11 data check signal lines It can be seen that cbl can be reduced to one. That is, by adding a checksum generation circuit (check circuit) in the memory module, a plurality of cbls (cbl1 to cbl3) are combined into one signal line cl and connected to the CPU in the memory module. By applying this method, the number of pins of the memory module (CPU bus width) can be reduced. For example, only a few signal lines are added to the general DIMM shown in FIG. It will be good.

  Furthermore, by using two types of error check codes, ECC (error detection and correction code) and checksum, it is possible to distinguish between errors when writing data to the memory and errors when reading data from the memory. . In other words, when an error is detected at the time of checking by a checksum, it can be determined that the error is at the time of writing, and when an error is detected by ECC, it is an error at the time of reading.

  However, application of the memory cell shown in FIG. 1 does not fundamentally solve the increase in latency caused by, for example, data error check. That is, in the memory cell of FIG. 1, when performing a data error check, the capacitor 103 is discharged, so a refresh process is required, and during this time, it is difficult to execute a normal data read / write process. . In other words, when the memory cell structure shown in FIG. 1 is applied, for example, when the CPU reads data from the memory, a refresh process is required twice in total after the data check and after the normal data read, resulting in an increase in latency. Will be invited.

  Hereinafter, embodiments of a memory cell, a memory module, an information processing apparatus, and a memory cell error correction method will be described in detail with reference to the accompanying drawings. FIG. 7 is a circuit diagram showing the memory cell of this embodiment. As shown in FIG. 7, the memory cell MC of this embodiment includes two transistors 1 and 2 and a triple capacitor 3.

  That is, the capacitor 3 has a triple structure including the stacked first electrode (conductor) 31, second electrode 32, and third electrode 33, and the first dielectric 31 is interposed between the first electrode 31 and the second electrode 32. A layer 34 is provided, and a second dielectric layer 35 is provided between the second electrode 32 and the third electrode 33. Here, the electrodes 31 to 33 are made of, for example, a metal such as aluminum or copper, or a conductive material such as polysilicon, and the dielectric layers 34 and 35 are made of dielectric such as silicon oxide or silicon nitride. Formed with body material.

  The transistor (first transistor) 1 and the transistor (second transistor) 2 are formed of, for example, n-channel MOS transistors, but are not limited thereto. In the transistor 1, the gate (control terminal) G is connected to the control line wl, the source (first terminal) S is connected to the data signal line bl, and the drain (second terminal) D is connected to the capacitor 3. The first electrode 31 is connected. In the transistor 2, the gate G is connected to the data check control line cwl, the source S is connected to the second electrode 32 of the capacitor 3, and the drain D is connected to the ground line (predetermined potential line) GND. It is connected. Here, the third electrode 33 of the capacitor 3 is connected to the data check signal line cbl.

  FIG. 8 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. 1, and FIG. 9 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. That is, the operation of the memory cell MC of this embodiment shown in FIG. 7 will be described in comparison with the operation of the memory cell of the related art shown in FIG. Here, FIGS. 8A and 9A show the state of charge before the data check, FIGS. 8B and 9B show the state of discharge after the data check, and FIG. c) shows the state of charge after refresh, and FIGS. 8 (d) and 9 (c) show the state of discharge after data reading. In the following description, the transistors 1, 2, 101, and 102 are described as n-channel MOS transistors. However, the conductivity type and type of the transistors, the level of the control signal, and the like can be variously modified and changed. Needless to say.

  First, the operation of the memory cell mc shown in FIG. 1 in which the capacitor 103 has two electrodes 131 and 132 will be described with reference to FIGS. 8 (a) to 8 (d). First, in data writing, for example, the data check control line cwl is set to a low level “L”, and the transistor 102 is turned off. Then, like a general DRAM cell, the control line wl is set to a high level “H”, the transistor 101 is turned on, and electric charges are accumulated in the capacitor 103 due to the potential difference between the data signal line bl and the ground line GND. This state is set as the initial state. Note that after data is written to the memory cell mc, wl is set to “L” and the transistor 101 is also turned off. That is, as shown in FIG. 8A, in the initial state, for example, the charging state corresponding to the data “1” (the charging state before the data check) is established, and between the electrodes 131 and 132 of the capacitor 103. Electric charges are accumulated in (dielectric layer 133).

  Further, data in the memory cell mc is read in order to perform an error check on the data written in the memory cell mc. That is, with wl set to “L”, cwl is set to “H”, the transistor 102 is turned on, and the charge accumulated in the capacitor 103 is taken out from the data check signal line cbl. As a result, as shown in FIG. 8B, the electric charge between the electrodes 131 and 132 of the capacitor 103 is discharged, resulting in a discharge state after the data check.

  Therefore, wl is set to “L” and wl is set to “H” to execute a refresh process, and the capacitor 103 is recharged. That is, as shown in FIG. 8 (c), the charge is accumulated between the electrodes 131 and 132 by the refresh process to enter the charged state after the refresh. For example, data in the memory cell (memory) can be read from the CPU. It becomes possible.

  In the memory data reading, similarly to the data writing, cwl is set to “L” and the transistor 102 is turned off, wl is set to “H”, the transistor 101 is turned on, and the charge accumulated in the capacitor 103 is read from bl. As a result, as shown in FIG. 8D, the electric charge between the electrodes 131 and 132 of the capacitor 103 is discharged, resulting in a discharge state after data reading.

  Next, the operation of the memory cell MC shown in FIG. 7 in which the electrode of the capacitor 3 is a triple structure (electrodes (conductors) 31 to 33) will be described with reference to FIGS. 9 (a) to 9 (c). First, for data writing, for example, the data check control line cwl is set to “L”, the transistor 2 is turned off, the central (second) electrode 32 is set in a floating state, and in this state, the control line wl is set to “H”. The transistor 1 is turned on. Then, electric charges are accumulated in the capacitor 3 due to the potential difference between the data signal line bl and the data check signal line cbl, and data is written. This state is the initial state (charge state corresponding to data “1”: charge before data check) State). In other words, in the capacitor 3, the second electrode is in a floating state, and writing is performed by the first electrode 31 and the third electrode 33. That is, as shown in FIG. 9A, in the initial state, between the electrodes 31 and 32 of the capacitor 3 (first dielectric layer 34) and between the electrodes 32 and 33 (second dielectric layer 35). ) Each has an accumulated charge.

  Further, in order to perform an error check of the data written in the memory cell MC, the data (charge accumulated in the second dielectric layer 35) of the memory cell MC is read. That is, the transistor 2 is turned on by setting cwl to “H”, the second electrode 32 is connected to the ground line GND, the transistor 1 is turned off by setting wl to “L”, and the charge accumulated in the second dielectric layer 35 is reduced. The data check signal line cbl is taken out. As a result, as shown in FIG. 9B, in the capacitor 3, the electric charge between the second electrode 32 and the third electrode 33 (second dielectric layer 35) is discharged, but the first electrode 31 and The electric charge between the second electrodes 32 (first dielectric layer 34) is held as it is.

  In the memory data reading, the data of the memory cells MC (charges accumulated in the first dielectric layer 34) are read. That is, the transistor 2 is turned on by setting cwl to “H”, the second electrode 32 is connected to the ground line GND, the transistor 1 is turned on by setting wl to “H”, and the charge accumulated in the first dielectric layer 34 is changed. The data signal line bl is taken out. As a result, as shown in FIG. 9C, in the capacitor 3, the electric charge between the first electrode 31 and the second electrode 32 (first dielectric layer 34) is discharged, and the discharge state after data reading is Become. That is, the capacitor 3 is completely discharged.

  Thus, by applying the memory cell of this embodiment shown in FIG. 7, for example, the refresh process after the data check when the memory cell of the related technology shown in FIG. 1 is applied can be made unnecessary. That is, according to this embodiment, it is possible to reduce the time required for the refresh process after the data check, and for example, it is possible to suppress an increase in latency when accessing the memory from the CPU.

  10 is a diagram for explaining a data write operation in a memory to which the memory cell shown in FIG. 1 is applied. FIG. 11 is a diagram for explaining a data read operation in a memory to which the memory cell shown in FIG. 1 is applied. FIG. 10 and 11, reference numeral 104 denotes a CPU, 141 denotes a MAC (Memory Access Controller), 142 denotes an ECCCD (Error Correction Code Decoder), 105 denotes a memory, and 151 denotes a cell array. .

  First, as shown in FIG. 10, for data writing, for example, two types of signals, ie, write data address information using wl and write information using b1, are transferred from the MAC 141 to the cell array (memory cell array) 151. Then, data writing is performed.

  Also, as shown in FIG. 11, for data reading, for example, a read data address information signal using wl is transmitted from the MAC 141 to the cell array 151 (P11). Based on this, the cell array 151 transfers read information (check data) to the ECCD 142 of the CPU 104 via b1 (P12). In the CPU 104, the ECCD 142 performs an error check on the read information, and then transfers the checked information to the MAC 141 (P13).

  Next, a data write operation and a data write operation in a memory to which the memory cell of this embodiment shown in FIG. 7 is applied will be described with reference to FIGS. FIG. 12 is a diagram for explaining the data write operation in the memory to which the memory cell shown in FIG. 7 is applied, and for explaining the data write operation using the checksum dedicated line and the check circuit in the memory module. is there. FIG. 13 is a diagram for explaining the data read operation in the memory to which the memory cell shown in FIG. 7 is applied, for explaining the data read operation using the checksum dedicated line and the check circuit in the memory module. Is.

  In FIG. 12 and FIG. 13, a checksum dedicated line (data check signal line cbl) is provided between the CPU 4 and the memory 5, and the check circuit 52 is built in the memory 5. 12 and 13, reference numeral 4 is a CPU, 41 is a MAC (memory access control circuit), 42 is an ECCD, 43 is a comparison circuit, 5 is a memory, 51 is a cell array, and 52 check circuit.

  As shown in FIG. 12, for writing, for example, two types of signals of write data address information using wl and write information using b1 are transferred from the MAC 41 of the CPU 4 to the cell array 51 of the memory 5. (P1). Further, the MAC 41 calculates a checksum of the data written in the memory 5 (cell array 51) and transmits it to the comparison circuit 43 of the CPU 4. At the same time, the address information of the check target data is transmitted to the cell array 51 via cwl. Is transmitted (P2).

  The cell array 51 calculates the checksum of the target data using the check circuit 52 based on the address information received via cwl. The check circuit 52 calculates the checksum of the target data calculated via cbl. To the comparison circuit 43 of the CPU 4 (P3). The comparison circuit 43 detects data corruption by comparing the checksum from the MAC 41 with the checksum from the memory 5 (check circuit 52). When the comparison circuit 43 detects data corruption from the comparison in the checksum, the CPU 4 immediately rewrites the data. At the same time, the data to be written from bl is stored based on the address information from wl.

  Further, as shown in FIG. 13, in the data reading, for example, a read data address information signal using wl is transmitted from the MAC 41 to the cell array 51 (P4). Based on this, the cell array 51 transfers the read information to the ECCD 42 of the CPU 4 via b1 (P5). The ECCD 42 performs an error check on the read information, and then transfers the checked information to the MAC 41 (P5). As described above, according to the memory to which the memory cell MC of this embodiment shown in FIG. 7 is applied, the refresh operation after the data write check on the memory becomes unnecessary, and it can be understood that an increase in latency can be suppressed.

  In the above, the memory to which the memory cell MC of the present embodiment is applied includes various memory modules such as the DIMM shown in FIG. 4 described above, a DIMM provided with the check circuit 52 (CC), or an HMB (High Bandwidth Memory). Can be applied to. Further, the memory to which the memory cell MC of the present embodiment is applied is not limited to the one provided as a memory module, and it goes without saying that it can be used as a built-in memory of a semiconductor integrated circuit, for example.

  FIG. 14 is a block diagram illustrating an example of the information processing apparatus according to this embodiment. In FIG. 14, reference numeral 6 is an information processing apparatus, 61 is a power supply circuit, 62 is a hard disk drive (HDD) / solid state drive (SSD), 63 is a chipset, 64 is a CPU, and , 65 indicates DIMM / HBM. That is, the information processing apparatus 6 illustrated in FIG. 14 includes a power supply circuit 61, an HDD / SSD 62, a chip set 63, a CPU 64, and a DIMM / HBM 65. The memory cell MC (memory module) of this embodiment described above is applied to the DMM / HBM 65.

  FIG. 15 is a block diagram showing another example of the information processing apparatus of the present embodiment, and corresponds to a configuration in which the four information processing apparatuses 6 shown in FIG. 14 are provided. That is, the information processing apparatus 60 shown in FIG. 16 includes four block circuits 6a to 6d, and each block circuit 6a to 6d connects the mutual block circuits to the information processing apparatus 6 shown in FIG. The switch chip 66 for this purpose is built in. The memory cell MC of the present embodiment described above is applied to the DMM / HBM 65 in each of the block circuits 6a to 6d.

  As described above, the memory cell MC and the memory module of this embodiment can be applied to various information processing apparatuses 6 and 60. Furthermore, as described above, this can be applied not only to memory modules such as DIMMs and HBMs but also to built-in memories of various semiconductor integrated circuits.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

1 transistor (first transistor)
2 transistors (second transistor)
3 capacitors 4,64 CPU
5 Memory 6, 60 Information processing device 6a to 6d Block circuit 31 Electrode (first electrode)
32 electrodes (second electrode)
33 electrodes (third electrode)
34 Dielectric layer (first dielectric layer)
35 Dielectric layer (second dielectric layer)
41 MAC
42 ECCD
43 Comparison circuit 51 Cell array 52 Check circuit 61 Power supply circuit 62 HDD / SSD
63 Chipset 65 DIMM / HBM

Claims (14)

A capacitor including a stacked first electrode, second electrode, and third electrode, and capable of storing electric charge between the first electrode and the second electrode, and between the second electrode and the third electrode;
A first transistor including a control terminal connected to the control line, a first terminal connected to the data signal line, and a second terminal connected to the first electrode;
A control terminal connected to a data check control line, a first terminal connected to the second electrode, and a second transistor including a second terminal connected to a predetermined potential line,
The third electrode is connected to a data check signal line.
A memory cell characterized by the above. The capacitor further includes:
A first dielectric layer provided between the first electrode and the second electrode;
A second dielectric layer provided between the second electrode and the third electrode,
The memory cell according to claim 1. The first transistor and the second transistor are n-channel MOS transistors.
The memory cell according to claim 1, wherein the memory cell is a memory cell. When writing data,
The second transistor is turned off by a signal of the data check control line,
The first transistor is controlled based on a signal of the control line, and charge accumulation based on a voltage difference between the data signal line and the data check signal line is controlled between the first electrode and the third electrode. To
The memory cell according to claim 1, wherein the memory cell is a memory cell. When checking
The first transistor is turned off by a signal of the control line,
The second transistor is controlled based on a signal of the data check control line, and data based on the electric charge accumulated between the second electrode and the third electrode connected to the predetermined potential line is stored in the data Take out from the check signal line,
The memory cell according to claim 4. At the time of the check,
When the data extracted from the data check signal line is different from the data to be written at the time of data writing, data writing is performed again.
The memory cell according to claim 5. When reading data,
The second transistor is turned on by a signal of the data check control line,
Controlling the first transistor based on a signal of the control line, and taking out data based on the charge accumulated between the second electrode and the first electrode from the data signal line;
The memory cell according to claim 4, wherein the memory cell is a memory cell. The memory cell is a DRAM cell;
The memory cell according to claim 1, wherein the memory cell is a memory cell. The memory cell according to any one of claims 1 to 8,
A memory module characterized by that. further,
At the time of checking, it has a check circuit for checking whether the data taken out from the data check signal line is different from the data written at the time of data writing,
The memory module according to claim 9. The memory module is a DIMM;
The memory module according to claim 9, wherein the memory module is a memory module. The memory module according to claim 9.
An information processing apparatus characterized by that. An error correction method for a memory cell according to any one of claims 1 to 3,
When writing data,
The second transistor is turned off by a signal of the data check control line,
The first transistor is controlled based on a signal of the control line, and charge accumulation based on a voltage difference between the data signal line and the data check signal line is controlled between the first electrode and the third electrode. And
When checking
The first transistor is turned off by a signal of the control line,
The second transistor is controlled based on a signal of the data check control line, and data based on the electric charge accumulated between the second electrode and the third electrode connected to the predetermined potential line is stored in the data Take out from the check signal line,
At the time of the check,
When the data taken out from the data check signal line is different from the data written at the time of writing the data, the data writing is performed again to correct the error.
An error correction method for a memory cell. When reading data,
The second transistor is turned on by a signal of the data check control line,
Controlling the first transistor based on the signal of the control line, taking out data based on the charge accumulated between the second electrode and the first electrode from the data signal line;
Perform error correction based on the error detection and correction code,
14. The memory cell error correction method according to claim 13.

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