JP6915372B2 - Error correction method for memory cells, memory modules, information processing devices, and memory cells - Google Patents

Description

The embodiments referred to in this application relate to memory cells, memory modules, information processing devices, and error correction methods for memory cells.

Conventionally, when reading data from a memory (for example, DRAM: Dynamic Random Access Memory), an error such as bit inversion due to disturbance is caused by adding an error detection and correction code (ECC: Error Check and Correct Code, Error Correction Code). I am trying to correct it.

By the way, due to the nature of the correction code, there is an upper limit to the number of correctable bits, and an error less than or equal to the correctable upper limit number of bits is called a correctable error (CE), and an error exceeding the correctable upper limit number of bits. Is called an uncorrectable error (UE). The CE and UE are detected by passing through a circuit (ECCD: ECC Decoder) that checks ECC at the time of reading.

Here, if it is CE, it can be corrected inside the ECCD and transferred to the CPU (Central Processing Unit). However, in the case of the UE, the ECCD sends an uncorrectable flag to the CPU and discards the error data. Then, the CPU that receives the uncorrectable flag from the ECCD interrupts the processing or re-executes the data that has become the UE from the memory write (hereinafter, also referred to as UE retry). At this time, the UE retry takes twice as long as the normal data transfer.

That is, because a common bus is used for writing and reading due to the structure of the memory, for example, reading of the UE determination and reading / writing of the original data cannot be processed in parallel. Further, since it is not possible to determine whether the UE has become a UE at the time of writing or at the time of reading, it is required to re-execute from writing to the memory in both the UE at the time of writing and the UE at the time of reading.

By the way, conventionally, various proposals have been made as a memory or a memory module having an improved structure of a memory cell.

Japanese Unexamined Patent Publication No. 06-119773 Japanese Unexamined Patent Publication No. 05-152537 Japanese Unexamined Patent Publication No. 2006-318132

As described above, for example, in order to avoid bus conflict between writing data from the CPU to the memory and reading data for UE determination, it is conceivable to provide a data check bus.

However, for example, if a data error check is performed after writing data to a memory (memory cell), the charge of the capacitor is discharged, so that a precharge process is performed. That is, for example, when the CPU reads data from the memory, the precharge process needs to be performed twice in total, after the data check and after the normal data read, which may lead to an increase in latency.

According to one embodiment, the laminated first electrode, second electrode, and third electrode are included, and a capacitor is charged between the first electrode and the second electrode, and between the second electrode and the third electrode. A memory cell having a storable capacitor, a first transistor, and a second transistor is provided.

The first transistor includes a control terminal connected to a control line, a first terminal connected to a data signal line, and a second terminal connected to the first electrode. The second transistor includes a control terminal connected to a data check control line, a first terminal connected to the second electrode, and a second terminal connected to a predetermined potential line. The third electrode is connected to a data check signal line. At the time of data writing, the second transistor is turned off by the signal of the data check control line, the first transistor is controlled based on the signal of the control line, and between the first electrode and the third electrode, It controls the accumulation of charges based on the difference voltage between the data signal line and the data check signal line. At the time of checking, the first transistor is turned off by the signal of the control line, the second transistor is controlled based on the signal of the data check control line, and the second electrode connected to the predetermined potential line and the said. Data based on the charge accumulated between the third electrodes is taken out from the data check signal line.

The disclosed memory cell, memory module, information processing device, and error correction method for the memory cell have an effect that an increase in latency can be suppressed by eliminating the need for a precharge operation after checking the writing of data to the memory.

FIG. 1 is a circuit diagram showing an example of a memory cell of a related technique. FIG. 2 is a block diagram showing an example of a memory cell array to which the memory cell shown in FIG. 1 is applied. FIG. 3 is a block diagram schematically showing a configuration example of a general memory module. FIG. 4 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 2 is applied. FIG. 5 is a block diagram showing another example of the memory cell array to which the memory cell shown in FIG. 1 is applied. FIG. 6 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 5 is applied. FIG. 7 is a circuit diagram showing a memory cell of this embodiment. FIG. 8 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. FIG. 9 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. 7. FIG. 10 is a diagram for explaining a data writing operation in the memory to which the memory cell shown in FIG. 1 is applied. FIG. 11 is a diagram for explaining a data read operation in the memory to which the memory cell shown in FIG. 1 is applied. FIG. 12 is a diagram for explaining a data writing operation in the memory to which the memory cell shown in FIG. 7 is applied. FIG. 13 is a diagram for explaining a data read operation in the memory to which the memory cell shown in FIG. 7 is applied. FIG. 14 is a block diagram showing an example of the information processing apparatus of this embodiment. FIG. 15 is a block diagram showing another example of the information processing apparatus of this embodiment.

First, before detailing an example of a memory cell, a memory module, an information processing device, and an error correction method for the memory cell, an example of the memory cell, a general memory module, and a modified example thereof are shown in FIGS. This will be described with reference to 6.

FIG. 1 is a circuit diagram showing an example of a memory cell of a related technique, and shows an example of a memory cell mc capable of avoiding bus contention. That is, the memory cell mc shown in FIG. 1 includes two transistors 101 and 102 and a capacitor 103, and for example, there is a bus conflict between writing data from the CPU to the memory and reading data for determining a UE (uncorrectable error). It is designed to avoid. Here, the transistors 101 and 102 are formed of n-channel MOS transistors, respectively, and the capacitor 103 is formed so as to sandwich the dielectric layer 133 between the two electrodes 131 and 132, but is not limited thereto. ..

A control line wl is connected to the gate G of the transistor 101, and a data signal line bl is connected to the source S of the transistor 101. Further, one electrode 131 of the capacitor 103 and the source S of the transistor 102 are connected to the drain D of the transistor 101. Further, a data check control line cwl is connected to the gate G of the transistor 102, and a data check signal line cbl is connected to the drain D of the transistor 102. The other electrode 132 of the capacitor 103 is grounded (GND).

That is, for example, the memory cell mc is provided with a data writing bus (data signal line bl) and a check bus (data check signal line cbl) from the CPU to the memory (DRAM), and are controlled by transistors 101 and 102, respectively. Will be done.

FIG. 2 is a block diagram showing an example of a memory cell array to which the memory cell shown in FIG. 1 is applied, and shows a configuration example of a memory array having a data check dedicated line (cbl, cwl). Although only three memory cells mc1 to mc3 are drawn in FIG. 2, it goes without saying that a large number of memory cells mc are actually arranged in a matrix.

The memory cell array shown in FIG. 2 performs memory address control for data access by the control lines wl (wl1 to wl3) in the same manner as a normal memory (DRAM). Further, after writing to the memory cells mc (mc1 to mc3) by the data signal line bl (bl1 to bl3), the data check control line cwl (cw1 to cw3) and the data check signal line cbl (cbl1 to cbl3) ) To check the memory. In this way, by dividing the signal line into a data signal line bl and a data check signal line cbl, bus contention is avoided.

FIG. 3 is a block diagram schematically showing a configuration example of a general memory module, and FIG. 4 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 2 is applied. Note that FIGS. 3 and 4 schematically show DIMMs (Dual Inline Memory Modules), in which 11 data signal lines bl (data check signal lines cbl) are drawn and control lines wl (data check) are drawn. The control line cwl) is drawn as one line.

As described with reference to FIGS. 1 and 2, four types of signal lines bl, wl, cbl, and cwl are used in the memory cell mc that can avoid bus contention. Therefore, as shown in FIG. 4, in the memory module to which the memory cell array shown in FIG. 2 is applied, twice the signal line is used as compared with the general memory module in FIG. 3, and the bus width is doubled. Will come to an increase.

This is not only required to increase the number of pins of the memory module (DIMM), but also to increase the number of buses in the CPU, for example. Further, even when it is applied as a built-in memory, the bus width is similarly increased, which leads to an increase in cost due to an increase in chip area.

FIG. 5 is a block diagram showing another example of a memory cell array to which the memory cell shown in FIG. 1 is applied, and shows a memory cell array incorporating a check circuit (checksum generation circuit) CC. FIG. 6 is a block diagram schematically showing an example of a memory module to which the memory cell array shown in FIG. 5 is applied.

As is clear from the comparison between FIGS. 5 and 6 and FIGS. 2 and 4 described above, in a memory module (DIMM) to which a memory cell array with a built-in check circuit CC is applied, for example, 11 data check signal lines are used. It can be seen that the cbl can be reduced to one. That is, by adding a checksum generation circuit (check circuit) in the memory module, a plurality of cbl (cbl1 to cbl3) are collectively connected to the CPU in one signal line cl in the memory module. By applying this method, the number of pins of the memory module (CPU bus width) can be reduced. For example, it is only necessary to add a small number of signal lines to the general DIMM shown in FIG. It will be good.

Furthermore, by using two types of error check codes, ECC (error detection and correction code) and checksum, it is possible to isolate an error when writing data to the memory and an error when reading data from the memory. .. That is, if an error is detected at the time of inspection by the checksum, it can be determined that it is an error at the time of writing, and if an error is detected by ECC, it can be determined that it is an error at the time of reading.

However, applying the memory cells shown in FIG. 1 does not fundamentally solve the increase in latency caused by, for example, data error checking. That is, when performing a data error check in the memory cell of FIG. 1, the charge of the capacitor 103 is discharged, so that a precharge process is required, and during this period, it becomes difficult to execute a normal data read / write process. Become. In other words, when the memory cell structure shown in FIG. 1 is applied, for example, when the CPU reads data from the memory, precharge processing is required twice in total, after the data check and after the normal data read, resulting in latency. It will lead to an increase.

Hereinafter, examples of a memory cell, a memory module, an information processing device, and an error correction method for the memory cell will be described in detail with reference to the accompanying drawings. FIG. 7 is a circuit diagram showing a memory cell of this embodiment. As shown in FIG. 7, the memory cell MC of this embodiment includes two transistors 1 and 2 and a capacitor 3 having a triple structure.

That is, the capacitor 3 has a triple structure including the laminated first electrode (conductor) 31, the second electrode 32, and the third electrode 33, and a first dielectric material is provided between the first electrode 31 and the second electrode 32. A layer 34 is provided, and a second dielectric layer 35 is provided between the second electrode 32 and the third electrode 33. Here, the electrodes 31 to 33 are formed of, for example, a metal such as aluminum or copper, or a conductive material such as polysilicon, and the dielectric layers 34 and 35 are dielectrics such as silicon oxide or silicon nitride. Formed of body material.

The transistor (first transistor) 1 and the transistor (second transistor) 2 are formed of, for example, an n-channel type MOS transistor, but the transistor is not limited to this, of course. In transistor 1, the gate (control terminal) G is connected to the control line wl, the source (first terminal) S is connected to the data signal line bl, and the drain (second terminal) D is the capacitor 3. It is connected to the first electrode 31. Further, in the transistor 2, the gate G is connected to the data check control line cwl, the source S is connected to the second electrode 32 of the capacitor 3, and the drain D is connected to the ground line (predetermined potential line) GND. It is connected. Here, the third electrode 33 of the capacitor 3 is connected to the data check signal line cbl.

FIG. 8 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. 1, and FIG. 9 is a diagram for explaining the transition of the charge state in the memory cell shown in FIG. 7. That is, the operation of the memory cell MC of the present embodiment shown in FIG. 7 will be described in comparison with the operation of the memory cell of the related technique shown in FIG. Here, FIGS. 8 (a) and 9 (a) show the charging state before the data check, and FIGS. 8 (b) and 9 (b) show the discharging state after the data check. c) shows the charge state after precharging , and FIGS. 8 (d) and 9 (c) show the discharge state after reading the data. In the following description, the transistors 1, 2, 101, and 102 will be described as n-channel type MOS transistors, but the conductive type and type of the transistor, the level of the control signal, and the like can be variously modified and changed. Needless to say.

First, the operation of the memory cell mc shown in FIG. 1 of the electrodes 131 and 132 having two capacitors 103 will be described with reference to FIGS. 8 (a) to 8 (d). First, in the data writing, for example, the data check control line cwl is set to the low level "L" and the transistor 102 is turned off. Then, as in a general DRAM cell, the control line wl is set to a high level "H", the transistor 101 is turned on, and the electric charge is accumulated in the capacitor 103 due to the potential difference between the data signal line bl and the ground line GND to write data. Is performed, and this state is set as the initial state. After writing the data to the memory cell mc, the wl is set to "L" and the transistor 101 is also turned off. That is, as shown in FIG. 8A, in the initial state, for example, it is in a charging state corresponding to the data “1” (charging state before the data check), and is between the electrodes 131 and 132 of the capacitor 103. Charges are accumulated in (dielectric layer 133).

Further, in order to check the error of the data written in the memory cell mc, the data in the memory cell mc is read out. That is, the transistor 102 is turned on while the wl is set to "L" and the cwl is set to "H", and the electric charge accumulated in the capacitor 103 is taken out from the data check signal line cbl. As a result, as shown in FIG. 8B, the electric charge between the electrodes 131 and 132 of the capacitor 103 is discharged, and the state is discharged after the data check.

Therefore, the precharge process is executed with wl set to "L" and wl set to "H" to recharge the capacitor 103. That is, as shown in FIG. 8 (c), the charge is accumulated between the electrodes 131 and 132 by the precharge process to be in the charged state after the precharge , and for example, the data of the memory cell (memory) is read from the CPU. It becomes possible.

Similar to the data writing, the memory data reading is performed by turning on the transistor 101 with wl set to "H" and reading the charge accumulated in the capacitor 103 from bl while keeping the transistor 102 turned off with cwl set to "L". As a result, as shown in FIG. 8D, the electric charge between the electrodes 131 and 132 of the capacitor 103 is discharged, and the state is discharged after reading the data.

Next, the operation of the memory cell MC shown in FIG. 7 in which the electrodes of the capacitor 3 have a triple structure (electrodes (conductors) 31 to 33) will be described with reference to FIGS. 9 (a) to 9 (c). First, for data writing, for example, the control line cwl for data check is set to "L", the transistor 2 is turned off, the central (second) electrode 32 is set to a floating state, and in this state, the control line wl is set to "H". Turn on transistor 1. Then, an electric charge is accumulated in the capacitor 3 by the potential difference between the data signal line bl and the data check signal line cbl to write data, and this state is set to the initial state (charging state corresponding to the data "1": charging before the data check. State). In other words, in the capacitor 3, the second electrode is in a floating state, and writing is performed by the first electrode 31 and the third electrode 33. That is, as shown in FIG. 9A, in the initial state, between the electrodes 31 and 32 of the capacitor 3 (first dielectric layer 34) and between the electrodes 32 and 33 (second dielectric layer 35). ), Each charge is accumulated.

Further, in order to perform an error check of the data written in the memory cell MC, the data of the memory cell MC (the electric charge accumulated in the second dielectric layer 35) is read out. That is, the transistor 2 is turned on with cwl set to "H", the second electrode 32 is connected to the ground wire GND, the transistor 1 is turned off with wl set to "L", and the electric charge accumulated in the second dielectric layer 35 is transferred. Take out from the data check signal line cbl. As a result, as shown in FIG. 9B, in the capacitor 3, the electric charge between the second electrode 32 and the third electrode 33 (second dielectric layer 35) is discharged, but the electric charge is discharged from the first electrode 31. The electric charge between the second electrodes 32 (first dielectric layer 34) is retained as it is.

Then, the data read of the memory reads the data of the memory cell MC (the electric charge accumulated in the first dielectric layer 34). That is, the transistor 2 is turned on with cwl set to "H", the second electrode 32 is connected to the ground wire GND, the transistor 1 is turned on with wl set to "H", and the electric charge accumulated in the first dielectric layer 34 is charged. Take out from the data signal line bl. As a result, as shown in FIG. 9C, in the capacitor 3, the electric charge between the first electrode 31 and the second electrode 32 (first dielectric layer 34) is discharged, and the state of discharge after reading the data is obtained. Become. That is, the capacitor 3 is completely discharged.

As described above, by applying the memory cell of the present embodiment shown in FIG. 7, for example, when the memory cell of the related technique shown in FIG. 1 is applied, the precharge process after the data check can be eliminated. .. That is, according to this embodiment, it is possible to reduce the time required for the precharge process after the data check, and for example, it is possible to suppress an increase in latency when accessing the memory from the CPU.

FIG. 10 is a diagram for explaining a data writing operation in the memory to which the memory cell shown in FIG. 1 is applied, and FIG. 11 is a diagram for explaining a data reading operation in the memory to which the memory cell shown in FIG. 1 is applied. It is a figure. In FIGS. 10 and 11, reference numeral 104 indicates a CPU, 141 indicates a MAC (Memory Access Controller), 142 indicates an ECCD (Error Correction Code Decoder), 105 indicates a memory, and 151 indicates a cell array. ..

First, as shown in FIG. 10, in data writing, for example, two types of signals, write data address information using wl and write information using b1, are transferred from MAC 141 to the cell array (memory cell array) 151. Then write the data.

Further, as shown in FIG. 11, for data reading, for example, a signal of read data address information using wl is transmitted from MAC 141 to the cell array 151 (P11). Based on this, the cell array 151 transfers read information (check data) to the ECCD 142 of the CPU 104 via b1 (P12). In the CPU 104, the ECCD 142 performs an error check of the read information, and then transfers the checked information to the MAC 141 (P13).

Next, a data writing operation and a data writing operation in the memory to which the memory cell of this embodiment shown in FIG. 7 is applied will be described with reference to FIGS. 12 and 13. FIG. 12 is a diagram for explaining a data writing operation in the memory to which the memory cell shown in FIG. 7 is applied, and is for explaining a data writing operation using a checksum dedicated line and a check circuit in a memory module. be. Further, FIG. 13 is a diagram for explaining a data read operation in the memory to which the memory cell shown in FIG. 7 is applied, and is for explaining a data read operation using the checksum dedicated line and the check circuit in the memory module. It is a thing.

Here, in FIGS. 12 and 13, a checksum dedicated line (data check signal line cbl) is provided between the CPU 4 and the memory 5, and the memory 5 has a built-in check circuit 52. In FIGS. 12 and 13, reference numeral 4 indicates a CPU, 41 indicates a MAC (memory access control circuit), 42 indicates an ECCD, 43 indicates a comparison circuit, 5 indicates a memory, 51 indicates a cell array, and 52 check circuits.

As shown in FIG. 12, for writing, for example, two types of signals, write data address information using wl and write information using b1, are transferred from the MAC 41 of the CPU 4 to the cell array 51 of the memory 5. (P1). Further, the MAC 41 calculates the checksum of the data written in the memory 5 (cell array 51) and transmits it to the comparison circuit 43 of the CPU 4. At the same time, the address information of the data to be checked is sent to the cell array 51 via the cwl. Is transmitted (P2).

The cell array 51 calculates the checksum of the target data using the check circuit 52 based on the address information received via the cwl, and the check circuit 52 calculates the checksum of the calculated target data via the cbl. Is transmitted to the comparison circuit 43 of the CPU 4 (P3). The comparison circuit 43 detects data corruption by comparing the checksum from the MAC 41 with the checksum from the memory 5 (check circuit 52). Then, when the comparison circuit 43 detects data corruption in the checksum from the comparison, the CPU 4 immediately rewrites the data. At the same time, the data to be written from bl is stored based on the address information from wl.

Further, as shown in FIG. 13, for data reading, for example, a signal of read data address information using wl is transmitted from the MAC 41 to the cell array 51 (P4). Based on this, the cell array 51 transfers the read information to the ECCD 42 of the CPU 4 via b1 (P5). After performing an error check of the read information, the ECCD 42 transfers the checked information to the MAC 41 (P5). As described above, according to the memory to which the memory cell MC of the present embodiment shown in FIG. 7 is applied , it can be seen that the precharge operation after the data write check to the memory is unnecessary and the increase in latency can be suppressed.

In the above, the memory to which the memory cell MC of this embodiment is applied is, for example, various memory modules such as the DIMM shown in FIG. 4, the DIMM provided with the check circuit 52 (CC), or the HBM (High Bandwidth Memory). Can be applied to. Further, it goes without saying that the memory to which the memory cell MC of this embodiment is applied is not limited to the one provided as a memory module, and can be used, for example, as a built-in memory of a semiconductor integrated circuit.

FIG. 14 is a block diagram showing an example of the information processing apparatus of this embodiment. In FIG. 14, reference numeral 6 is an information processing device, 61 is a power supply circuit, 62 is a hard disk drive (HDD) / solid state drive (SSD), 63 is a chipset, 64 is a CPU, and so on. , 65 represent DIMM / HBM. That is, the information processing device 6 shown in FIG. 14 includes a power supply circuit 61, an HDD / SSD 62, a chipset 63, a CPU 64, and a DIMM / HBM 65. The memory cell MC (memory module) of the present embodiment described above is applied to the DMM / HBM65.

FIG. 15 is a block diagram showing another example of the information processing apparatus of this embodiment, and corresponds to the configuration in which four information processing apparatus 6 shown in FIG. 14 described above are provided. That is, the information processing device 60 shown in FIG. 16 includes four block circuits 6a to 6d, and each of the block circuits 6a to 6d connects the mutual block circuits to the information processing device 6 shown in FIG. The switch chip 66 for this purpose is built in. The memory cell MC of the present embodiment described above is applied to the DMM / HBM 65 in the respective block circuits 6a to 6d.

As described above, the memory cell MC and the memory module of this embodiment can be applied to various information processing devices 6 and 60. Further, as described above, this can be applied not only as a memory module such as DIMM or HBM but also as a built-in memory of various semiconductor integrated circuits.

Although the embodiments have been described above, all the examples and conditions described here are described for the purpose of assisting the understanding of the concept of the invention applied to the invention and the technology, and the examples and conditions described in particular are described. It is not intended to limit the scope of the invention. Nor does such a statement in the specification indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various modifications, replacements and modifications can be made without departing from the spirit and scope of the invention.

1 transistor (first transistor)
2 transistors (2nd transistor)
3 Capacitor 4,64 CPU
5 Memory 6,60 Information processing device 6a to 6d Block circuit 31 Electrode (1st electrode)
32 electrode (second electrode)
33 Electrode (3rd electrode)
34 Dielectric layer (first dielectric layer)
35 Dielectric layer (second dielectric layer)
41 MAC
42 ECCD
43 Comparison circuit 51 Cellular array 52 Check circuit 61 Power supply circuit 62 HDD / SSD
63 Chipset 65 DIMM / HBM

Claims (14)

A capacitor that includes a laminated first electrode, second electrode, and third electrode and is capable of accumulating charges between the first electrode and the second electrode, and between the second electrode and the third electrode.
A first transistor including a control terminal connected to a control line, a first terminal connected to a data signal line, and a second terminal connected to the first electrode.
It has a control terminal connected to a data check control line, a first terminal connected to the second electrode, and a second transistor including a second terminal connected to a predetermined potential line.
The third electrode is connected to a data check signal line and is connected to the data check signal line .
When writing data
The second transistor is turned off by the signal of the data check control line, and the second transistor is turned off.
The first transistor is controlled based on the signal of the control line, and the accumulation of electric charge based on the difference voltage between the data signal line and the data check signal line is controlled between the first electrode and the third electrode. death,
At the time of check
The first transistor is turned off by the signal of the control line, and the first transistor is turned off.
The second transistor is controlled based on the signal of the control line for data check, and the data based on the electric charge accumulated between the second electrode and the third electrode connected to the predetermined potential line is obtained as the data. Take out from the check signal line ,
A memory cell characterized by that. The capacitor is further
A first dielectric layer provided between the first electrode and the second electrode,
A second dielectric layer provided between the second electrode and the third electrode is included.
The memory cell according to claim 1. The first transistor and the second transistor are n-channel type MOS transistors.
The memory cell according to claim 1 or 2, wherein the memory cell is characterized in that. At the time of the check
If the data taken out from the data check signal line is different from the data to be written at the time of writing the data, the data is written again.
The memory cell according to any one of claims 1 to 3, wherein the memory cell is characterized in that. When reading data
The second transistor is turned on by the signal of the data check control line, and the second transistor is turned on.
The first transistor is controlled based on the signal of the control line, and the data based on the charge accumulated between the second electrode and the first electrode is taken out from the data signal line.
Memory cell according to any one of claims 1 to 4, characterized in that. The memory cell is a DRAM cell.
The memory cell according to any one of claims 1 to 5, wherein the memory cell. The memory cell according to any one of claims 1 to 6.
A memory module characterized by that. Moreover,
It has a check circuit for checking whether the data taken out from the data check signal line at the time of checking is different from the data written at the time of writing data.
The memory module according to claim 7. The memory module is a DIMM.
The memory module according to claim 7 or 8. A memory module according to any one of claims 7 to 9,
An information processing device characterized by this. A error correction method of the eye Moriseru,
The memory cell is
A capacitor that includes a laminated first electrode, second electrode, and third electrode and is capable of accumulating charges between the first electrode and the second electrode, and between the second electrode and the third electrode.
A first transistor including a control terminal connected to a control line, a first terminal connected to a data signal line, and a second terminal connected to the first electrode.
It has a control terminal connected to a data check control line, a first terminal connected to the second electrode, and a second transistor including a second terminal connected to a predetermined potential line.
The third electrode is connected to a data check signal line and is connected to the data check signal line.
When writing data
The second transistor is turned off by the signal of the data check control line, and the second transistor is turned off.
The first transistor is controlled based on the signal of the control line, and the accumulation of electric charge based on the difference voltage between the data signal line and the data check signal line is controlled between the first electrode and the third electrode. death,
At the time of check
The first transistor is turned off by the signal of the control line, and the first transistor is turned off.
The second transistor is controlled based on the signal of the control line for data check, and the data based on the electric charge accumulated between the second electrode and the third electrode connected to the predetermined potential line is obtained as the data. Take out from the check signal line
At the time of the check
If the data taken out from the data check signal line is different from the data to be written at the time of writing the data, the data is written again to correct the error.
A memory cell error correction method characterized by this. The capacitor is further
A first dielectric layer provided between the first electrode and the second electrode,
A second dielectric layer provided between the second electrode and the third electrode is included.
The memory cell error correction method according to claim 11. The first transistor and the second transistor are n-channel type MOS transistors.
The memory cell error correction method according to claim 11 or 12. When reading data
The second transistor is turned on by the signal of the data check control line, and the second transistor is turned on.
The first transistor is controlled based on the signal of the control line, and the data based on the charge accumulated between the second electrode and the first electrode is taken out from the data signal line.
Perform error correction based on the error detection correction code,
The memory cell error correction method according to any one of claims 11 to 13 , characterized in that.

Images