JP2828530B2 - Non-volatile storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line to which a plurality of memory cells each comprising one capacitor using a ferroelectric film and one MOS transistor are connected.
The present invention relates to a nonvolatile memory device in which a plurality of sense amplifiers connected to a book are arranged on a semiconductor substrate, and a polarization direction of a ferroelectric film of the capacitor is stored in correspondence with two pieces of information.

[0002]

2. Description of the Related Art One capacitor using a ferroelectric film and M
Writing and reading of binary data "1" and "0" in a memory cell composed of one OS transistor are performed according to the operation principle shown in FIGS. Hereinafter this operating principle consists of a capacitor 1 and MOS transistor 2, illustrating the memory cell 3 connected to the bit lines BL and word lines X ₀ as an example.

First, when writing data "1", as shown in FIG. 4, the power supply voltage V _CC is supplied to the bit line BL, the word line X0 is set to "H" level, and the MOS transistor 2 is turned on. Supplies the power supply voltage V _CC to one end of the capacitor 1. 1/2 on the other end of the capacitor 1
A voltage of V _CC is supplied. Therefore, in this case, a voltage of 1/2 V _CC is applied between both electrodes of the capacitor 1, and an electric field E _VCC corresponding thereto appears as shown in FIG. _S is accumulated.

[0004] After that, when turned off MOS transistors 2 in the "L" level to the word line X0, but external electric field is eliminated, charge P _r is the capacitor 1 due to the polarization of the ferroelectric film constituting the capacitor 1 Remains. This residual charge _Pr is retained even when the supply of the power supply voltage V _CC to the nonvolatile memory device is stopped and the voltage of 1/2 V _CC is not supplied to the other end of the capacitor 1. Therefore, according to the present nonvolatile memory device, information can be held in a nonvolatile manner.

As shown in FIG. 6, the reading of data "1" is performed by precharging the bit line BL to the _Vcc level prior to the reading operation. Subsequently, from this state, the word line X0 is set at "H" level to turn on the MOS transistor 2. As a result, the electric charge of the bit line BL precharged to the power supply voltage V _CC is supplied to the capacitor 1 to cause charge sharing.

Here, since the capacity of the bit line BL is generally considered to be ten times or more larger than the capacity of the capacitor 1 of the memory cell 3, a voltage close to the power supply voltage V _CC level is applied to one end of the capacitor 1. Will be supplied. Therefore, when data "1" is read, a voltage close to 1/2 V _CC is applied between both electrodes of the capacitor 1, so that
As shown in FIG. 7, an electric field E _VCC corresponding to this appears, and the electric charge P _s is accumulated in the capacitor 1. At this time, the amount of charge transferred from bit line BL to the capacitor 1 becomes P _s -P _r.

Assuming that the capacity of the bit line BL is C _B and the capacity of the capacitor 1 is C _S , the voltage level V _BIT1 of the bit line BL when data “1” is read is given by the following equation (1). .

That is, since the relationship of V _cc · C _B- (P _S -P _r ) = V _BIT1 · (C _B + C _S ) is established, if this is expanded, V _BIT1 = (V _CC · C _B- to become _{(P S -P r)) /} (C B + C S) ··· (1).

On the other hand, the writing of data "0", as shown in FIG. 8, supplies a GND level (0V) to the bit lines BL, word lines X ₀ in the "H" level MO
The S transistor 2 is turned on, thereby supplying the GND level to the other end of the capacitor 1. At this time, the capacitor 1
Since a voltage of -1 / 2V _CC is applied between both electrodes,
It appears an electric field E _GND corresponding thereto as shown in FIG. 9, the charge -P _s is stored in the capacitor 1.

[0010] After that, when turned off MOS transistors 2 in the "L" level of the word line X _0, but external electric field is eliminated, charges -P _r for polarization of the ferroelectric film remains. The supply of the power supply voltage V _CC to the nonvolatile memory device is stopped, and the residual charge −P _r is 1 /
Even if the voltage of 2V _CC is not supplied, it is maintained
Information can be held in a nonvolatile manner.

For reading data "0", as shown in FIG. 10, the bit line BL is precharged to the _Vcc level prior to the read operation. Subsequently, the word line X _{0 is set} to “
H level to turn on the MOS transistor 2. Thereby, the bit line B precharged to the power supply voltage V _CC
The charge of L is supplied to the capacitor 1 to cause charge sharing. As described above, since the capacity of the bit line BL is generally considered to be ten times or more larger than the capacity of the capacitor 1 of the memory cell 3, power close to the power supply voltage V _CC is supplied to one end of the capacitor 1. Will be.

Since a voltage close to 1/2 V _CC is applied between both electrodes of the capacitor 1, an electric field E _VCC corresponding thereto appears as shown in FIG. 11, and the charge P _S is accumulated in the capacitor 1. . At this time, the amount of charge transferred from bit line BL to the capacitor 1 becomes P _s + P _r. Similarly to the above, if the capacity of the bit line BL is C _B and the capacity of the capacitor 1 is C _S ,
The voltage level V _BIT0 of the bit line BL when data “1” is read is given by the following equation (2).

That is, since the relationship of V _CC · C _B- (P _S + P _r ) = V _BIT0 · (C _B + C _S ) is established, V _BIT0 = (V _CC · C _B- (P _S + P _r ). / (C _B + C _S ) (2)

One capacitor using a ferroelectric film and an MO
As a conventional example of a nonvolatile memory device using a memory cell constituted by one S-transistor and in which binary data “1” and “0” are written / read based on the above-mentioned operation principle, There is a nonvolatile memory device proposed in Japanese Patent Application No. 3-252038. FIG. 12 shows a part of the circuit configuration of this nonvolatile memory device, that is, two of a plurality of bit lines wired in the column direction and the peripheral configuration thereof.

One end of two adjacent bit lines BL and / BL is connected to a sense amplifier 30 for amplifying and detecting a potential difference between the two bit lines BL and / BL. A plurality of word lines Xi and Yi (i = 0 to n) are arranged in a row direction orthogonal to the bit lines BL and the bar BL. The word line Xi indicates a word line connected to the gate of the memory cell 3 connected to one bit line BL, and the word line Yi connects to the gate of the memory cell 3 connected to the other bit line BL. FIG.

The memory cells 3 and 3 have bit lines BL and bar B
A capacitor 1 using a ferroelectric film and an N-channel MOS disposed in a region surrounded by L and word lines Xi and Yi.
It is composed of a transistor 2. Specific connection modes between the memory cells 3 and 3 and the word lines Xi and Yi and the bit lines BL and / BL are as follows.

That is, as word lines Xi and Yi, X
0, Y0 as an example, one memory cell 3
Has a drain connected to the bit line BL, a source connected to one end of the capacitor 1, and a gate connected to the word line X0. In the other memory cell 3, the drain of the MOS transistor 2 is connected to the bit line bar BL, the source is connected to one end of the capacitor 1, and the gate is connected to the word line Y0.
The other end of the capacitor 1,1, 1/2 of the voltage of the power supply voltage V _CC, that is, the voltage of 1 / 2V _CC is adapted to be supplied from the outside.

In addition to the above configuration, two dummy cells are connected to each bit line BL and bar BL. That is,
Dummy cells 17a and 17b are connected to the bit line BL, and dummy cells 17c and 17d are connected to the bit line bar BL. These dummy cells 17a, 17b, 17
c and 17d are dummy capacitors 17 using a ferroelectric film.
0 and a MOS transistor 171. The capacity of the dummy capacitor 170 is the capacitor 1 of the memory cell 3.
, That is, as shown in the figure, C _D = 1 /
It has become 2C _S. The MOS transistors 171 are all N-channel MOS transistors.

These dummy cells 17a, 17b, 17
c and 17d are also dummy cell word lines DXi and DYi
(I = 0, 1). Dummy cells 17a, 17
Specific connection modes of b, 17c, 17d and bit lines BL, bar BL and dummy cell word lines DXi, DYi are as follows.

That is, in the dummy cell 17a, the drain of the MOS transistor 171 is connected to the bit line BL, the source is connected to one end of the dummy capacitor 170, and the gate is connected to the dummy cell word line DX0. On the other hand, in the dummy cell 17b, the drain of the MOS transistor 171 is connected to the bit line BL, the source is connected to one end of the dummy capacitor 170, and the gate is connected to the dummy cell word line DX1. Also, the dummy cell 17c
The drain of the OS transistor 171 is connected to the bit line bar BL.
The source is connected to one end of the dummy capacitor 170, and the gate is connected to the dummy cell word line DY0.
On the other hand, in the dummy cell 17d, the drain of the MOS transistor 171 is connected to the bit line bar BL, the source is connected to one end of the dummy capacitor 170, and the gate is connected to the dummy cell word line DY1. The other ends of the four dummy capacitors 170, 170, 170, 170 are supplied with a voltage of 1/2 V _CC from outside.

Further, a bit line equalizing circuit 13 is provided between the sense amplifier 30 between the bit lines BL and / BL and the memory cell 3 adjacent thereto. The bit line equalizing circuit 13 is composed of three P-channel MOS transistors 10, 11 and 12, and the gates of these MOS transistors 10, 11 and 12 are all connected between the sense amplifier 30 and the adjacent word line X0. _Is connected to the bar Φ _BEQ signal line 21. Also,
The sources of MOS transistors 10 and 12 are connected to V _CC , and the drains are connected to bit line BL and bar B, respectively.
L. On the other hand, the drain of the MOS transistor 11 is connected to the bit line BL, and the source is connected to the bit line bar BL.

[0022] Sense amplifier 30 is the bit line BL as described above, is connected to the bar BL, a circuit for detecting and amplifying a small potential difference appearing bit lines BL, between bars BL, [Phi _s signal instructing the start amplification That is, when the "H" level Φ _s signal is input, the amplification operation starts.

Next, a data reading procedure in the nonvolatile memory device will be described with reference to FIG. First, FIG.
(B), which is connected to the dummy cell word line DX0, DY1 at the timing shown in (e) is set to "H" level (= V _CC + △ V level), each bit line BL, the bar BL two each Dummy cells 17a, 17b, 17c, 17d
Of the dummy cells 17a and 17d are polarized to ferroelectric films of the dummy capacitors 170 and 170 of the dummy cells 17a and 17d.

Subsequently, the potentials of the bit lines BL and / BL are inverted, and the dummy cell word lines DX1 and DY0 are set to the "H" level (= V _CC +) at the timings shown in FIGS.
ΔV level) and the other dummy cells 17b and 17c connected to the bit line BL and bar BL
L, writing is performed from the bar BL, and the dummy cell 17 is written.
Polarize the ferroelectric films of the dummy capacitors 170, 170 of b, 17c. Since writing is performed in a state where the potentials of the bit lines BL and / BL are inverted, such writing before data reading causes the dummy cells 17a and 1
The polarization directions of the ferroelectric films of the dummy capacitors 170 and 170 of 7b are opposite to each other. Similarly, the dummy capacitors 170, 170 of the dummy cells 17c and 17d are also provided.
The polarization directions of the ferroelectric films are also opposite to each other.

Subsequently, as shown in FIG. 13A, the bit line equalizing circuit 13 _{applies a} signal from the bar Φ _BEQ signal line 21 to the bit line equalizing circuit 13.
An L ″ level (= GND level) bar Φ _BEQ signal is input, and the bit line equalizing circuit 13 is operated.
The MOS transistors 10, 11, and 12 are turned on, and the bit lines BL and / BL are precharged to the _Vcc level.

Subsequently, at the timing shown in FIG. 13 (f), the word line Xi (or the word line Yi) goes high (= high).
When becomes V _CC + △ V level), as shown in FIG. 13 (d), (e), at the same time a dummy cell word line DY0,
DY1 (or DX0, DX1) becomes "H" level. As a result, the polarization charge from the selected memory cell 3 is read out to one bit line BL (or bar BL) of the two bit lines BL and / BL connected to the sense amplifier 30, and the other bit line BL (or / BL). Bit line bar BL (or BL) has two dummy cells 17c, 17d (or 17) in which the polarization directions of the ferroelectric films of the dummy capacitors 170 are opposite to each other.
a, 17b).

FIG. 13H shows a change in voltage level appearing on the bit lines BL and / BL when data "1" is read, and FIG. 13I shows a bit line when data "0" is read. Changes in voltage levels appearing on BL and bar BL are shown. This read operation is performed in the same manner as the nonvolatile memory device previously proposed by the present applicant. Therefore, the bit line BL from which the polarization charge has been read from the memory cell 3
(Or bar BL), when data “1” is read, a voltage level V _BIT1 expressed by the above equation (1) appears.
In the case of reading data “0”, a voltage level V _BIT0 expressed by the above equation (2) appears. On the other hand, the dummy cell 17
A voltage level V _BITD expressed by the following equation (3) appears on the bit line BL (or BL) from which the polarization charges from c and 17d (or 17a and 17b) are read.

[0028] That _{is, V CC · C B - (} P S -P r) / 2- (P S + P r) / 2 = V
Since the relationship between the _{BITD · (C B + C S} ) is _{satisfied, V VITD = (V CC ·} C B -P S) / (C B + C S) ··· (3) to become.

From the above results, when data "1" is read, the potential difference of ΔV ₁ = V _BIT1 −V _BITD becomes the input of the sense amplifier 30, and when the Φ _S signal is inputted, the sense amplifier 30 makes this potential difference. ΔV ₁ is amplified and detected.

Similarly, when data "0" is read, the potential difference of ΔV ₀ = V _BITD −V _BIT0 is applied to the sense amplifier 3.
When the Φ _S signal is input, the sense amplifier 30 amplifies and detects the potential difference ΔV ₀ . From the above equations (1), (2) and (3), the potential differences ΔV ₁ and ΔV ₀ are expressed by the following equations (4) and (5), respectively.

[0031] _{ΔV 1 = (V CC · C} B - (P S -P r)) / (C B + C S) - (V CC · C B -P S) / (C B + C S) = P r / (C _B + C _S ) (4) ΔV ₀ = (V _CC · C _B- (P _S + P _r )) / (C _B + C _S ) = (C _B + C _S ) (5) According to the non-volatile memory device described above, at the time of reading data "1" and data "0", it is possible to obtain a detection signal having opposite polarities and equal absolute values, so that data "1" and data "0" are obtained. , That is, accurate reading can be performed.

[0032]

According to the above-described nonvolatile memory device, the memory cell 3 is composed of one capacitor 1 and two MOS transistors 1 in total. An efficient layout is possible as compared with the device. However, since two dummy cells must be connected to one bit line, a total of four elements (two capacitors and two MOS transistors) are required for one bit line, and the chip area is reduced. At present, there is still room for improvement.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a nonvolatile memory device which can further simplify the device configuration of the nonvolatile memory device and can further reduce the chip area. Aim.

[0034]

According to the present invention, there is provided a nonvolatile memory device comprising: a bit line to which a plurality of memory cells each including one capacitor using a ferroelectric film and one MOS transistor are connected; What is claimed is: 1. A nonvolatile memory device, comprising: a plurality of sense amplifiers connected to two bit lines arranged on a semiconductor substrate; and storing a polarization direction of a ferroelectric film of the capacitor in correspondence with two pieces of information. Is connected to each of the two bit lines, and the two bit lines are precharged to a predetermined voltage level before the polarization charge from the capacitor to the bit line is read out. In addition, at the same time as reading out the polarization charge from the capacitor to one of the bit lines connected to the sense amplifier,
The voltage level of the one bit line is boosted by the dummy capacitor connected to the one bit line to the precharge level or more when the polarization direction of the ferroelectric film of the capacitor is one direction. On the other hand, when the polarization direction of the ferroelectric film is on the other side, the voltage is not boosted to the precharge level, and between the one bit line and the other bit line where the precharge level is maintained as it is. The sense amplifier amplifies the appearing potential difference to read data, thereby achieving the above object.

Further, the nonvolatile memory device according to the present invention includes one capacitor using a ferroelectric film and one MOS transistor.
A plurality of bit lines each having a plurality of memory cells connected thereto and a plurality of sense amplifiers connected to the two bit lines are arranged on a semiconductor substrate, and the polarization direction of the ferroelectric film of the capacitor is set to two. A non-volatile memory device for storing information corresponding to information, wherein one dummy capacitor using a dielectric film is connected to each of the two bit lines, and a polarization charge to the bit line is read from the capacitor. Before the two bit lines are precharged to a preset voltage level, the polarization charge from the capacitor is read out to one of the bit lines connected to the sense amplifier while the other bit line is connected to the other bit line. When the polarization direction of the ferroelectric film of the capacitor is one direction, the voltage level of the other bit line is lower than that of the one bit line by the dummy capacitor. When the polarization direction of the ferroelectric film is the other, the voltage is not lowered to a voltage level lower than that of the one bit line, and the potential difference appearing between the two bit lines is amplified by the sense amplifier. Then, data is read out, thereby achieving the above object.

[0036]

As described above, in the present invention, a capacitor using a ferroelectric film is not used as a dummy cell, but one capacitor using a normal ferroelectric film is connected to each bit line. By boosting (or stepping down) the bit line connected to the dummy cell, the same function as that of the conventional dummy cell including four elements (the details of which will be described in detail in Examples) can be exhibited. it can.

This means that one element that has conventionally required four elements for one bit line can be replaced with one element. Therefore, according to the present invention, the number of elements can be significantly reduced.

[0038]

Embodiments of the present invention will be described below.

FIG. 1 shows a part of the circuit configuration of the nonvolatile memory device according to the present invention, that is, two of the bit lines wired in the column direction and the peripheral configuration thereof. One end of two adjacent bit lines BL and / BL has a sense amplifier 30 for amplifying and detecting a potential difference between the two bit lines BL and / BL.
Is connected. A plurality of word lines Xi and Yi (i = 0) are arranged in a row direction orthogonal to the bit lines BL and / BL.
To n) are wired. The word line Xi indicates a word line connected to the gate of the memory cell 3 connected to one bit line BL, and the word line Yi connects to the gate of the memory cell 3 connected to the other bit line BL. FIG.

The memory cells 3 and 3 have bit lines BL and bar B
A capacitor 1 using a ferroelectric film and an N-channel MOS disposed in a region surrounded by L and word lines Xi and Yi.
It is composed of a transistor 2. Specific connection modes between the memory cells 3 and 3 and the word lines Xi and Yi and the bit lines BL and / BL are as follows.

That is, as word lines Xi and Yi, X
0, Y0 as an example, one memory cell 3
Has a drain connected to the bit line BL, a source connected to one end of the capacitor 1, and a gate connected to the word line X0. In the other memory cell 3, the drain of the MOS transistor 2 is connected to the bit line bar BL, the source is connected to one end of the capacitor 1, and the gate is connected to the word line Y0.
The other end of the capacitor 1,1, 1/2 of the voltage of the power supply voltage V _CC, that is, the voltage of 1 / 2V _CC is adapted to be supplied from the outside.

Further, a bit line equalizing circuit 13 is provided between the sense amplifier 30 between the bit lines BL and / BL and the memory cell 3 adjacent thereto. The bit line equalizing circuit 13 is composed of three P-channel MOS transistors 10, 11 and 12, and the gates of these MOS transistors 10, 11 and 12 are all connected between the sense amplifier 30 and the adjacent word line X0. _Is connected to the bar Φ _BEQ signal line 21. Also,
The sources of MOS transistors 10 and 12 are connected to V _CC , and the drains are connected to bit line BL and bar B, respectively.
L. On the other hand, the drain of the MOS transistor 11 is connected to the bit line BL, and the source is connected to the bit line bar BL.

The sense amplifier 30 is the bit line BL as described above, is connected to the bar BL, a circuit for detecting and amplifying a small potential difference appearing bit lines BL, between bars BL, [Phi _s signal instructing the start amplification That is, when the "H" level Φ _s signal is input, the amplification operation starts.

The above configuration is described in Japanese Patent Application No. Hei.
The configuration of the nonvolatile memory device is the same as that of the nonvolatile memory device proposed in Japanese Patent No. 2038.
Is different.

That is, the dummy cell 5 of the nonvolatile memory device of the present invention is composed of one dummy capacitor 4 using a normal dielectric film, and the dummy cell 5 is connected to the bit line BL,
The circuit configuration is connected to the bar BL. The specific connection mode is as follows.

One dummy capacitor 4 has one end connected to the dummy cell word line DX and the other end connected to the bit line BL. One end of the other dummy capacitor 4 is connected to the dummy cell word line DY, and the other end is connected to the bit line bar BL.

In the nonvolatile memory device of the present invention having the above structure, writing of the binary data "1" and "0" is performed by setting the word lines Xi and Yi to the "H" level and selecting the MOS transistor 2 of the selected memory cell 3. Is turned on, and the bit lines BL and / BL are set to a predetermined level (V _CC level or GN level).
D level) and apply 1 / 2V between both electrodes of the capacitor 1.
A voltage of _CC or -1 / 2V _CC is applied to make the polarization direction of the ferroelectric film correspond to the binary information.

Next, the data read operation will be specifically described with reference to FIG. Prior to reading, the [Phi _BEQ signal given from [Phi _BEQ signal line 21 to the bit line equalizing circuit 13 is set to "L" level (GND level),
The MOS transistors 8, 9 and 10 are turned on to precharge the bit lines BL and / BL to the _Vcc level (FIG. 2).
(See (a) and (g)).

Subsequently, at the timing shown in FIG. 2B, the word line Xi changes from "L" level (GND level) to "H".
Level ( _Vcc + △ V level), the memory cell 3 connected to the word line Xi and the bit line BL
Is selected, and the polarization charges from the selected memory cell 3 are read out to the bit line BL of the two bit lines BL and / BL connected to the sense amplifier 30. On the other hand, the selection of the memory cell 3 connected to the word line Yi and the bit line bar BL is performed at the timing shown in FIG. 2C. At this time, the memory cell 3 selected by the bit line bar BL is selected. The polarization charge from is read out.

The bit line BL (or bar BL) from which the polarization charge has been read from the memory cell 3 is read "1".
In this case, the voltage V _BIT1 expressed by the above equation (1) appears. In the case of reading “0”, the voltage V _BIT0 expressed by the above equation (2) appears.

Subsequently, the dummy cell word line DX is
When the potential is raised from the “L” level (GND level) to the “H” level (V _CC level) at the timing shown in FIG. 4D, the bit line BL is utilized by utilizing the charge accumulated in the dummy capacitor 4 of the dummy cell 5. Voltage level is increased.
The arrow A in FIG. 2G indicates this state, and the voltage level indicated by the solid line in the figure, which appears on the bit line BL, is set higher than the precharge level (= V _CC level) at the above timing, that is, the voltage is boosted. You can see that it is. At this time, as indicated by a broken line in the figure, the voltage level of the other bit line / BL connected to the sense amplifier 30 is maintained at the precharge level. At this time, the sense amplifier 30 amplifies and detects the potential difference appearing between the bit lines BL and / BL at the timing indicated by the arrow C in FIG.

On the other hand, when the dummy cell word line DY rises at the timing shown in FIG. 2E, the bit line BL at the above timing as shown by the arrow B in FIG.
Is boosted to a level slightly lower than the precharge level. At this time, on the contrary, the voltage level of the bit line BL is maintained at the precharge level. At this time, the sense amplifier 30 amplifies and detects the potential difference appearing between the bit lines BL and / BL at the timing indicated by the arrow D in FIG.

When data "1" is read out to the bit line BL, the voltage level V of the bit line BL after being boosted.
_BIT1B is _expressed by the following equation (6). When data "0" is read out to the bit line bar BL, the bit line bar BL
The voltage level V _BIT0B after the boosting is expressed by the following equation (7).

That is, (C _B + C _S + C _D ) · V _BIT1 = (C _B + C _S ) · V _BIT1B +
The relation of _{(V BIT1B -V CC) · C} D is _{established, V BIT1B = V BIT1 + V} CC · C D / (C B + C S + C D) = (V CC · C B - (P S + P r) ) / (C _B + C _S ) + V _CC · C _D / (C _B + C _S + C _D ) (6)

Also, (C _B + C _S + C _D ) · V _BIT0 = (C _B
+ C _S ) · V _BIT0B + (V _BIT0B −V _CC ) · C _D holds, so V _BIT0B = V _BIT0 + V _CC · C _D / (C _B + C _S + C _D ) = (V _CC · C _B) - the _{(P S + P r))} / (C B + C S) + V CC · C D / (C B + C S + C D) ··· (7).

[0056] However, C _D is the capacitance of the dummy capacitor 4.

As described above, at this time, the other bit line BL (or bit line B) connected to the sense amplifier is connected.
L) maintains the V _CC level, so that in the case of reading data “1”, the potential difference of ΔV _1B = V _BIT1B −V _CC becomes the input of the sense amplifier 30, and the timing shown in FIG. in the "H" level of the [Phi _S signal is inputted, the sense amplifier 30 detects and amplifies the potential difference [Delta] V _1B.

[0058] Similarly, in the case of a read of data "0", ΔV _0B = V _CC -V _BIT0B potential of the sense amplifier 3
0 at the timing shown in FIG.
When the H level Φ _S signal is input, the sense amplifier 3
0 amplifies and detects this potential difference ΔV _0B . The following (8)
Equations (9) and (9) show specific values of the potential differences ΔV _1B and ΔV _0B .

[0059] _{ΔV 1B = -V CC + (V} CC · C B - (P S -P r)) / (C B + C S) + V CC · C D / (C B + C S + C D) ··· ( _{8) ΔV OB = V CC -} (V CC · C B - (P S + P r)) / (C B + C S) -V CC · C D / (C B + C S + C D) ··· (9) As can be seen from the above equations (8) and (9), the polarity is opposite when reading data "1" and data "0" in the nonvolatile memory device of the present invention, as in the nonvolatile memory device. As a result, a detection signal having the same absolute value can be obtained, so that data "1" and "0" can be identified, that is, accurate reading can be performed.

[0060] Here, by setting the capacitance C _D of the dummy capacitors 4 so that ΔV _1B = ΔV _OB, data "1"
A margin can be secured when reading both data and data “0”. The value of C _D at this time is expressed by the following equation (10).

C _D = (V _CC · C _S + P _S ) · (C _B + C _S ) / (V _CC · C _B -P _S ) (10) FIG. 3 shows another embodiment of the present invention. Show. In this embodiment, unlike the above embodiment, when reading data "1" and "0", the other bit line BL (or bit line bar B) is read.
A reading method in which the voltage level of L) is stepped down using the charge of the dummy capacitor 4 is adopted. The details will be described below. However, (a), (b) and (c) in the timing chart shown in FIG.
Since they are the same as (b) and (c), a specific description is omitted.

In the same manner as in the above embodiment, the bit line BL (or bar B) from which the polarization charge is read from the memory cell 3 is read.
L), the voltage V _BIT1 expressed by the above equation (1) appears in the case of reading “1”. In the case of reading “0”, the voltage V _BIT0 expressed by the above equation (2) appears.

Subsequently, the dummy cell word line DY is
When the voltage falls from the “H” level to the “L” level at the timing shown in (e), the voltage level of the other bit line BL is reduced using the charge accumulated in the dummy capacitor 4. The arrow A in FIG. 3G indicates this state, and the voltage level indicated by the broken line in the figure appearing on the bit line bar BL is slightly lower than the precharge level indicated by the solid line in the figure appearing on the bit line BL. It can be seen that the voltage is lower than (low value). At this time, the sense amplifier 30 amplifies and detects the potential difference appearing between the bit lines BL and / BL at the timing indicated by the arrow C in FIG.

On the other hand, when the dummy cell word line DX falls at the timing shown in FIG. 3D, the voltage level of the bit line BL is lowered in this case, as shown by the arrow B in FIG. However, the voltage is not reduced below the voltage level of the other bit line bar BL. At this time, the sense amplifier 30 amplifies and detects the potential difference appearing between the bit line BL and the bar BL at the timing indicated by the arrow D in FIG.

As described above, in this embodiment, the bit line B corresponding to the polarization direction of the capacitor 1 of the memory cell 3 is set.
The voltage level of L (or bar BL) is lowered and data
It is configured to read 1 ”and“ 0 ”.

At this time, the potential V _BITDM of the stepped down bit line BL (or bar BL) is expressed by the following equation (11).

That is, since the relationship of V _CC · (C _B + C _S ) = V _BITDM · (C _B + C _S + C _D ) is satisfied, V _BITDM = V _CC · (C _B + C _S ) / (C _B + C). _S + C _D ) (11)

In the case of reading data “1”, ΔV
The potential difference of _1D = V _BIT1 -V _BITDM is input to the sense amplifier 30, and the "H" level Φ _S signal is input at the timing shown in FIG. 3 (f). The sense amplifier 30 amplifies this potential difference ΔV _1D . To detect. Similarly, data "0"
, The sense amplifier 30 outputs ΔV _0D = V
_BITDM- V _Amplifies and detects the potential difference of _BIT0 .

The specific values of the potential differences ΔV _1D and ΔV _0D are expressed by the following equations (12) and (13), respectively.

[0070] _{ΔV 1D = (V CC · C} B - (P S -P r)) / (C B + C S) -V CC · (C B + C S) / (C B + C S + C D) ··· (12) ΔV _0D = V _CC · (C _B + C _S ) / (C _B + C _S + C _D )-(V _CC · C _B- (P _S + P _r )) / (C _B + C _S ) 13) As can be seen from the above equations (12) and (13), in the case of the nonvolatile memory device of the present embodiment, similarly to the nonvolatile memory device, when reading data “1” and data “0”, , A detection signal having the opposite polarity and the same absolute value can be obtained, so that the data "1" and "0" can be identified, that is, accurate reading can be performed.

[0071] Also in this embodiment, by setting the C _D such that [Delta] V _1D = [Delta] V _0D, can secure a margin in the case of both the read data "1" and "0".
The value of C _D at this time is expressed by the following equation (14).

C _D = (V _CC · C _S + P _S ) · (C _B + C _S ) / (V _CC · C _B + P _S ) (14)

[0073]

According to the nonvolatile memory device of the present invention described above, one dummy capacitor formed of an ordinary dielectric film is connected to two bit lines, respectively.
The same function as a conventional dummy cell having a circuit configuration of a total of four elements composed of two MOS transistors and two dummy capacitors using a ferroelectric film can be exhibited. Therefore, the data "1" and "0" can be reliably identified and accurate reading can be performed, and the number of elements can be greatly reduced. Therefore, the device configuration can be simplified and the chip area can be further increased. There is an advantage that the size can be further reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a nonvolatile memory device of the present invention.

FIG. 2 is a timing chart showing data read timing according to one embodiment of the nonvolatile memory device of the present invention.

FIG. 3 is a timing chart showing data read timing according to another embodiment of the nonvolatile memory device of the present invention.

FIG. 4 shows data of a memory cell composed of one capacitor using a ferroelectric film and one MOS transistor.
Drawing for explaining operation at the time of 1 "writing.

FIG. 5 is a diagram showing a change in stored charge of a memory cell when data “1” is written.

FIG. 6 is a diagram for explaining an operation when data “1” is read from a memory cell.

FIG. 7 is a diagram showing a change in stored charge of a memory cell when data “1” is read.

FIG. 8 is a diagram for explaining an operation at the time of writing data “0” of a memory cell.

FIG. 9 is a diagram showing a change in stored charge of a memory cell when data “0” is written.

FIG. 10 is a diagram for explaining an operation when data “0” is read from a memory cell;

FIG. 11 is a diagram showing a change in stored charge of a memory cell when data “0” is read.

FIG. 12 is a circuit diagram showing a nonvolatile memory device previously proposed by the present applicant.

13 is a timing chart showing data read timings in the nonvolatile memory device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Capacitor using ferroelectric film 2 MOS transistor 3 Memory cell 4 Capacitor using normal dielectric film 5 Dummy cell 13 Bit line equalizing circuit 30 Sense amplifier BL, bar BL Bit line Xi, Yi (i = 0 to n) ) Word line DX, DY Dummy cell word line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/822 H01L 27/10 681G 21/8242 27/04 C 27/04 G11C 11/34 352A 27/10 451 352E 27/108 29/788 29/792 (58) Fields investigated (Int.Cl. ⁶ , DB name) H01L 21/8247 G11C 11/22 G11C 11/401 G11C 14/00 G11C 17/04 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/10 H01L 27/108 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] A capacitor using a ferroelectric film and an MO
A plurality of bit lines connected to a plurality of memory cells each including one S transistor, and a plurality of sense amplifiers connected to the two bit lines are arranged on a semiconductor substrate, and polarization of a ferroelectric film of the capacitor is arranged. What is claimed is: 1. A non-volatile memory device for storing directions in correspondence with two pieces of information, comprising: connecting a dummy capacitor using a dielectric film to each of said two bit lines; Before reading the charge, the two bit lines are precharged to a preset voltage level, and while the polarization charge from the capacitor is read to one bit line connected to the sense amplifier, one of the bit lines is simultaneously read. The voltage level of the one bit line is adjusted by the dummy capacitor connected to the bit line, and the precharge level is set when the polarization direction of the ferroelectric film of the capacitor is one direction. When the polarization direction of the ferroelectric film is the other, the voltage is not increased to the precharge level, and the one bit line and the other bit that maintains the precharge level are not changed. A non-volatile memory device in which data is read out by amplifying a potential difference appearing between the line and the sense amplifier by the sense amplifier. 2. A single capacitor using a ferroelectric film and an MO
A plurality of bit lines connected to a plurality of memory cells each including one S transistor, and a plurality of sense amplifiers connected to the two bit lines are arranged on a semiconductor substrate, and polarization of a ferroelectric film of the capacitor is arranged. What is claimed is: 1. A non-volatile memory device for storing directions in correspondence with two pieces of information, comprising: connecting a dummy capacitor using a dielectric film to each of said two bit lines; Before reading the charge, the two bit lines are precharged to a preset voltage level, and the polarization charge from the capacitor is read to one bit line connected to the sense amplifier while the other bit line is read. The voltage level of the other bit line is changed by the dummy capacitor connected to the one bit line when the polarization direction of the ferroelectric film of the capacitor is one direction. In addition, when the polarization direction of the ferroelectric film is the other, the voltage is not lowered to a voltage level lower than that of the one bit line, and the potential difference appearing between the two bit lines is reduced. A nonvolatile memory device configured to read data by amplifying the data with the sense amplifier.