JPH10334672A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a multi-level operation semiconductor memory device which performs the memory operation, by storing n-bit information. (>=2) to one memory cell when a ferro-electric material is used for a capacitor. SOLUTION: The bit line pair BL, BLB are divided to n divided bit line pairs BL1, BL1B,..., BLn, BLnB and sense amplifier circuits SA1,..., SAn are connected to such divided bit line pairs. Moreover, capacitance elements Cc1,..., (Ccn-1) are connected between the divided bit lines. Using this capacitance element, the sense amplification of each bit is performed sequentially to the least significant bits BLn, BLnB from the most significant bits BL1, BL1B, while changing the sense level of lower bits depending on the sense result of the upper bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device for a multi-valued memory cell.

[0001]

2. Description of the Related Art In recent years, the size of semiconductor devices has been further reduced, and this tendency has been increasing. For this reason, a multi-valued memory capable of storing multi-bit information in one memory cell has been developed in order to reduce the size of a storage device which is a kind of semiconductor device.

This multi-valued memory is capable of storing information of one bit or more in one memory cell by changing the threshold value of a memory cell in an EEP-ROM in multiple steps.
There are various methods such as a method in which a charge stored in a memory cell in a RAM is divided into multiple stages so that information of one bit or more in one memory cell can be stored.

In a semiconductor memory device using these multi-level memory cells, multi-level information can be stored in one cell. Therefore, a cell that can store only 1-bit information in one cell (hereinafter referred to as 1). The number of memory cells can be reduced as compared with a conventional storage device including bit cells.), And thus, the size of the storage device and, consequently, the size of a semiconductor device including the storage device as a component can be reduced. Things.

However, a semiconductor memory device using a multi-valued cell must use a circuit configuration different from a conventional circuit configuration for driving a 1-bit cell due to the uniqueness of the cell.

For example, in a one-bit cell, one sense amplifier is usually provided for one bit line. However, a DRAM using a quaternary multi-value cell is disclosed in
As described in JP-A-149900, three sense amplifiers are required for one bit line. This is shown in FIG.

The operation of the conventional example shown in FIG. 13 will be briefly described below.

Each of the memory cells connected to word lines WL0 to WL255 has 0,
(1/3) Vcc, (2/3) Vcc, Vcc, total 4
Information is stored. The dummy cells connected to the dummy word lines DWL1 and DWL2 have (1/6) Vcc and the dummy word lines DWL3 and DWL4.
And (5/6) Vcc are stored in advance in the dummy cells connected to the dummy word lines DWL5 and DWL6.

Here, the operation of reading data stored in the cell 1 comprising an n-type MOS transistor and a capacitor will be described. The cells in the figure, including the dummy cells, have the same configuration as the cell 1.

First, the gate selection line TG goes high (hereinafter referred to as H level), and the word lines WL0 to WL85.
And region 1 consisting of dummy word lines DWL1 and DWL2, region 2 consisting of word lines WL86-171 and dummy word lines DWL3-4, and region 3 consisting of word lines WL172-255 and dummy word lines DWL5-6. , Are connected to bit lines BL1 and BLB1.

After the precharge, the word line WL0 goes high, and the information in the cell 1 is read out to the bit line BL1. Here, the information in the cell 1 is, for example, (2/3) Vc
c.

Thereafter, gate select line TG attains a low level (hereinafter, referred to as an L level), and regions 1, 2 and 3 are electrically separated from each other.

Thereafter, the bit line BL connected to the cell 1 is
The dummy cell connected to the bit line BLB1 corresponding to 1 is activated, and the information of the dummy cell is read. That is, the dummy word lines DWL2, DWL4, DWL6 go to the H level.

Next, the sense amplifier activating signal SEN becomes H
Level, and the sense amplifiers SA11, SA12, SA
13 is activated. Thus, in the area 1, the data of the bit line BL1 is (2/3) Vcc, and the data of the bit line BLB1 is the data of the dummy cell (1/1).
6) Since it is Vcc, the sense amplifier SA11 outputs an H level to the data line D1, and outputs an L level to the data line D1 bar. Similarly, in the region 2, the data on the bit line BL1 is (2/3) Vcc and the data on the bit line BLB1 is (1/2) Vcc, which is the data of the dummy cell. Therefore, the sense amplifier SA12 is connected to the data line D2. Output an H level and output an L level to the data line D2 bar. In the area 3, the data of the bit line BL1 is (2
/ 3) Vcc and the data on the bit line BLB1 is (5/6) Vcc, which is the data of the dummy cell. Therefore, the sense amplifier SA13 outputs an L level to the data line D3 and an H level to the data line D3 bar. Output. That is, the data lines D1, D2, and D3 respectively have H, H,
An L-level signal is output.

The data on these data lines is processed by a data output circuit from 3-bit information to 2-bit information and output to an external device as 2-bit information. This is because the amount of information stored in the memory cell is quaternary, and the information can be originally expressed by 2 bits.

With the above description, the read operation of the conventional example shown in FIG. 13 is completed. The description of the write operation and the like is omitted.

[0016]

By the way, although a multi-valued cell has been developed, a sense amplifier having the same sensitivity as that of the conventional one is currently used. That is, the sense amplifier used in the 1-bit cell DRAM is used as it is. Therefore, assuming that the sense amplifier can sense when the difference between the memory cell information and the dummy cell information is equal to or more than ΔV, the capacity of the capacitor of the multi-level cell is, for example, three times the capacity of the 1-bit cell in the case of the 4-level cell. Is required.

In order to realize three times the capacity,
A configuration as shown in FIG. 15 is conceivable. This will be described in comparison with the configuration of the 1-bit cell shown in FIG.

In FIG. 8, a 2 × 2 area is secured for one cell. And, of these, the area of 1 × 1 becomes the capacitor. Note that the distance between the capacitors is set to one. The configuration shown in FIG. 15 realizes a triple capacity by utilizing this cell arrangement as it is. That is, one quaternary cell is realized with a cell area of two 1-bit cells in FIG. Here, the area of the capacitor is 1 × 3, and therefore, a capacity three times as large as one bit cell can be obtained.

However, this configuration is not sufficient to reduce the size of the device. That is, in the configuration as shown in FIG. 16, the capacitance of the capacitor is root 3 × root 3, and one cell area is (1 + root 3) ×
(1 + route 3), that is, an area of about 7.5. This is smaller than one cell area of 2 × 4 in FIG. 15, which contributes to downsizing of the device.

However, even if the cell configuration shown in FIG. 15 is used, the configuration shown in FIG. 13 in which three sense amplifiers are provided for one bit line causes an increase in area, and consequently the use of multi-valued cells is not possible. The merit was not fully exhibited.

This will be described below with reference to FIGS. 17 and 18. FIG. 17 is a schematic diagram of a configuration in which quaternary information is stored using 1-bit cells. in this case,
Two 1-bit cell groups are formed, and two sense amplifiers are provided. Here, since the ratio of the area of the cell array section to the area including the sense amplifier section and the I / O outlet is usually 5: 1 to 3: 1, the ratio is described so as to be reflected. FIG. 18 is a schematic configuration diagram in the case where the same amount of information as in FIG. 17 is realized by a quaternary cell. In FIG. 18, since three sense amplifiers are required for one bit line, three sense amplifiers are provided. The cell area ratio in FIGS. 17 and 18 is the same as the cell area ratio in FIGS. 14 and 16, and the same sense amplifier is used in both FIGS. 17 and 18.

As is apparent from a comparison between FIGS. 17 and 18, the area of FIG. 17 is (4 × 1) × 2 + (1 × 1) × 2
= 10, and the area of FIG. 18 is 7.5+ (1 × 1) ×
3 = 10.5.

That is, when quaternary information is required,
It can be seen that the device may be downsized when the device is configured using 1-bit cells.

That is, a conventional DRAM using a multi-level cell
Then, in some cases, the size of the apparatus may be increased contrary to the purpose of developing the multi-value cell.

Accordingly, an object of the present invention is to provide a semiconductor device that meets the purpose of developing a multi-level cell, that is, a semiconductor device that uses a multi-level cell and is smaller than a semiconductor device using a 1-bit cell.

[0026]

To this end, a semiconductor device according to the present invention comprises a first conductive means connected to form a conductive path between a first wiring and a second wiring. A second conductive means connected to form a conductive path between the third wiring and the fourth wiring, one end connected to the first wiring, and the other end connected to the fourth wiring. Connected first
A second capacitor having one end connected to the second wiring and the other end connected to the third wiring;
A first input terminal is connected to the first wiring, a second input terminal is connected to the third wiring, and applied to the first and second input terminals according to a first signal. Compare the potentials,
First comparing means for outputting the result to the first wiring and outputting an inverted signal of the result to the third wiring;
Is connected to the second wiring, a fourth input terminal is connected to the fourth wiring, and a potential applied to the third and fourth input terminals in response to a second signal is Comparing the result to the second wiring, and outputting an inverted signal of the result to the fourth wiring, the first and second conductive means comprising: In response to the third signal,
The method is characterized in that the conductive path is formed.

[0027]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a sense amplifier circuit (including a bit line-pair portion and a memory cell array portion) of a semiconductor memory device according to a first embodiment (corresponding to claims 1 and 2) of the present invention. It is shown. The circuit in FIG. 1 is divided into a sense amplifier circuit section and a memory cell array section.

In FIG. 1, a pair of bit lines BL and BLB
Are n divided bit line pairs BL1, BL1B,..., BL
n, BLnB, and (n−
1) Transfer gates SWT1,..., SWTn
They are connected by -1. Each divided bit line pair BLi,
BLiB (i = 1,..., N) is a sense amplifier circuit SA
i (i = 1,..., n). Each divided bit line pair BLi, BLiB (i = 1,..., N) has a memory cell array section, and CBi (i = 1,
.., N). B between each divided bit line pair
Li and BLi-1B, BLiB and BLi-1 (i = 2,
,..., N) are connected to a capacitive element Ci-1 (i = 2,..., N). In the case of FIG. 1, the divided bit line pair BL
n and BLnB are assigned to the most significant bit, and BL1 and BL1B are assigned to the least significant bit.

In the semiconductor memory device of the present invention, a memory operation is performed by allocating n bits to one memory cell. Before describing the operation, the amount of signal charges read from the memory cell will be described.

FIG. 2 is a circuit diagram showing the connection of the memory cells of the semiconductor memory device of the present invention. Memory cell MC
Are formed by a switching transistor Tr and a capacitor C having one electrode connected to one of the source and the drain of the transistor Tr.
The other electrode is connected to the plate line PL, the gate of the transistor Tr is connected to the word line WL, and the other of the source and drain is connected to the bit line BL.
In FIG. 2, it is assumed that the capacitor C is composed of (2 @ n -1) domains having mutually different coercive voltages. In this case, as shown in FIG. 3, Vc (1) <Vc (2) <... <Vc (j) <... <Vc
It is expressed as a parallel connection of (2 n -1) ferroelectric capacitors C (1),..., C (j),.

FIGS. 4A and 4B show the characteristics (polarization characteristics) of the polarization amount P with respect to the voltage V between both electrodes of each ferroelectric capacitor C (j). In the initial state, the polarization amount P exists at point e, and the direction of polarization is the first direction.
When the voltage V between the two electrodes becomes equal to or higher than the coercive voltage Vc (j), the polarization amount P changes from point e to point f to point g, and the polarization direction is changed to the second direction.
Orientation. Conversely, in the initial state, the polarization amount P exists at point a, and the direction of polarization is the second direction. When the voltage V between both electrodes becomes equal to or lower than the voltage −Vc (j), the polarization amount P is changed to the point a →
Point b changes to point c, and the polarization direction becomes the first direction.
Thus, each ferroelectric capacitor C (j) has a hysteresis characteristic with respect to the voltage V between both electrodes.

In the semiconductor memory device of the present invention, the 2 @ n states of one memory cell are associated with the polarization directions of each ferroelectric capacitor C (j) as shown below (type 1 and type 2). There are two types).

(1) Type 1 For data 0: C (1), C (2),..., C (2 n −
If all of 1) are in the first orientation data 1: C (1) is in the second orientation, C (2),
, C (2 @ n -1) is the first... Data j: C (1),..., C (j) are in the second direction, and C (j + 1),. ... For data 2n -1: C (1), C (2), ..., C
All of (2n -1) are in the second direction. (2) In the case of type 2 data 0: C (1), C (2), ..., C (2n-
If all of 1) are in the second orientation data 1: C (1) is in the first orientation, C (2),
, C (2n-1) is the second data j: C (1),..., C (j) is in the first direction, and C (j + 1),. ... For data 2n -1: C (1), C (2), ..., C
When all of (2 n -1) are of the first orientation type 1, after applying a positive voltage V + (j) given by the following equation (1) between both electrodes of the capacitor C, the voltage is reduced to 0V By returning, data j can be realized.

V + (0) <Vc (1) Vc (j) ≦ V + (j) <Vc (j + 1) (j = 1
.., 2n-2) Vc (2n-1) ≤V + (2n-1) In this case, the word line WL shown in FIG. 2 is set to the high level to turn on the transistor Tr, and between the bit line BL and the plate line PL. When the voltage V between both electrodes of the capacitor C is -Ve
When a voltage that satisfies (−Ve <−Vc (2 n −1)) is applied, in the case of reading data j, a charge amount Q + (j) given by the following equation (II) is obtained via the bit line BL. Will be done.

Q + (j) = Q1 (1) +... + Q1 (j) + Q0 (j + 1) +... + Q0 (2 n -1) (II) In the case of type 2, the following equation is provided between both electrodes of the capacitor C. Data j can be realized by returning the voltage to 0 V after applying the negative voltage V- (j) given in (III).

−Vc (1) <V− (0) −Vc (j + 1) <V− (j) ≦ −Vc (j) (j = 1,..., 2n−2) V− (2n−1) ≦ -Vc (2n -1) (III) In this case, the word line WL shown in FIG. 2 is set to the high level to turn on the transistor Tr, and the voltage V between the two electrodes of the capacitor C is applied between the bit line BL and the plate line PL. Ve
When a voltage satisfying (Vc (2 @ n -1) <Ve) is applied,
In the case of reading data j, a negative charge Q- (j) given by the following equation (IV) is obtained via the bit line BL.

Q- (j) =-Q1 (1) -...- Q1 (j) -Q0 (j + 1) -...- Q0 (2n-1) (IV) In both types 1 and 2, Data is read out by amplifying the amount of charge read on the bit line BL in this manner by the sense amplifier circuit shown in FIG.

FIG. 5 shows an example (1) of an operation waveform at the time of reading data from the memory cell MC selected by the bit line BL and the word line WLk in the sense amplifier circuit shown in FIG. Operation example 1 will be described with reference to FIG.

First, the bit line BL is floated after being precharged to the GND level. At this time, the transfer gates SWT1 to SWTn-1 are all on.

Next, at time T1, the selected word line WLk rises to a high level according to the input address. Then, at time T2, the plate line rises from the GND level to the Vcc level. At this time, a voltage -Ve is applied between both electrodes of the capacitor C, and the bit line B is supplied from the memory cell MC in accordance with 2 @ n data j (j = 0,..., 2 @ n -1).
The signal charge is read on L. Since the capacitance of the bit line BL is CB = (CB1 + CB2 +... + CBn), the potential Vmem of the bit line BL at this time is
(J) is expressed by the following equation using equation (II).

Vmem (j) = Q + (j) / CB = (Q1 (1) +... + Q1 (j) + Q0 (j + 1) +.
+ Q0 (2n -1)) / (CB1 + CB2 + ... + CB
n) At this time, the reference potential Vref is output to the bit line BLB not connected to the memory cell MC by the reference potential generating circuit not shown in FIG.
The reference potential Vref includes a read potential Vmem (0) for data 0 and a read potential Vmem for data (2 n -1).
It is set to an intermediate potential of mem (2 @ n -1).

Next, at time T3, the transfer gates SWT1 to SWTn-1 are all turned off. Then, at time T4, the sense amplifier circuit SA1 is activated,
The divided bit line pair BL1, BL1B is sense-amplified.
When divided bit line BL1 is amplified to Vcc level,
BL2B is raised by xV due to the coupling capacitance Cc1. Conversely, when divided bit line BL1B is amplified to Vcc level, BL2 is raised by xV.

Next, at time T5, the sense amplifier circuit SA
2 is activated, and the divided bit line pair BL2, BL2B is sense-amplified. Also in this case, the coupling capacitance Cc
By the operation of 2, the potentials of the divided bit lines BL3 and BL3B fluctuate.

As described above, the result of the sense amplification of the upper divided bit line pair is fed back to the sense level of the lower divided bit line pair, so that the sense amplifier circuit SAn is activated at time T6. , The same sensing operation is performed.

Finally, at time T7 to T8, when n divided bit line pairs are selected by the column selection line CSL,
Data of the sense amplifier circuits SA1,..., SAn are transmitted to 10 bus pairs 1/01,.

FIG. 6 shows an example (part 2) of an operation waveform at the time of reading data from the memory cell MC. Operation example 2
The difference from the first is that the potential of the plate line PL is fixed at the Vcc level at the time of reading.

In the second case, first, the bit line BL
Are floated after being precharged to the GND level. At time T1, when the selected word line WLk rises to a high level in accordance with the input address, a voltage -Ve is applied between both electrodes of the capacitor C, and 2n data j (j = 0,... 2n -1),
The signal charge Q + (j) is read on the bit line BL.

FIG. 7 shows an example (part 3) of an operation waveform at the time of reading the memory cell MC. Operation example 3 will be described with reference to FIG.

First, the bit line BL is floated after being precharged to the Vcc level.

Next, at time T1, the selected word line WLk rises to a high level according to the input address. Then, at time T2, the plate line falls from the Vcc level to the GND level. At this time, a voltage Ve is applied between both electrodes of the capacitor C, and the bit line BL according to 2 n data j (j = 0,..., 2 n -1) is supplied from the memory cell MC.
Above, the minus signal charge Q- (j) is read. At this time, the potential Vmem (j) of the bit line BL is calculated by the equation (I
If V) is used, it is expressed as follows.

Vmem (j) = Vcc + Q- (j) / CB = Vcc- (Q1 (1) +... + Q1 (j) + Q0 (j +
1) + ... + Q0 (2 @ n -1) / (/ CB1 + CB2 + ...
+ CBn) At this time, the reference potential Vref is output to the bit line BLB not connected to the memory cell MC. The reference potential Vref is set to an intermediate potential between the read potential Vmem (0) of the data 0 and the read potential Vmem (2n-1) of the data (2n-1). The operation after the time T3 is performed in the same manner as the operation example 1 shown in FIG.

FIG. 8 shows an example (part 4) of an operation waveform at the time of reading data from the memory cell MC. Operation example 4
Is different from the third in that the potential of the plate line PL is fixed at the GND level at the time of reading.

In the case of the fourth case, similarly to the case of the third case, first, the bit line BL is precharged to the Vcc level, and then is brought into a floating state. At time T1, when the selected word line WLk rises to a high level in accordance with the input address, a voltage Ve is applied between both electrodes of the capacitor C, and 2 n data j (j = 0,..., 2 n) are supplied from the memory cell MC.
In response to -1), a negative signal charge Q- (j) is read on the bit line BL.

The second embodiment of the semiconductor memory device according to the present invention relates to a write system in which a memory operation is performed by allocating n bits to one memory cell in a semiconductor memory device using a ferroelectric capacitor. It is stated.

FIG. 9 shows the configuration of FIG.
This shows an example (part 1) of a write operation to the memory cell MC selected by the bit line BL.

First, the bit line BL is floated after being precharged to the GND level.

Next, at time T1, the selected word line WLk rises to a high level in accordance with the input address. Then, at time T2, the plate line falls from the GND level to the Vcc level. At this time, the voltage -Ve is applied between both electrodes of the capacitor C, and has different coercive voltages (2n-
1) The polarization direction of all domains is the first direction. The operation up to this point is the same as the first read operation example described with reference to FIG. Therefore, the operations subsequent to the first example of the write operation are also the rewrite operations of the first example of the read operation.

Next, at time T3, the write data j (j
= 0,..., 2n -1), the potential Vwbl (j) of the bit line BL connected to the memory cell MC is calculated by the equation (1).
Is set as given by the following equation using V + (j) given by

Vwbl (j) = V + (j) Next, at time T4, the plate line PL falls from the Vcc level to the GND level. At this time, the voltage V + (j) is applied to the capacitor C.

Next, at time T5, the bit line BL goes to GND.
Fall to the level.

Finally, at time T6, the selected word line WLk
Falls to a low level, ending the write operation.

FIG. 10 shows an example (part 2) of a write operation to the memory cell MC.

First, the bit line BL is floated after being precharged to the GND level. Further, plate line PL is set to the Vcc level.

Next, at time T1, the selected word line WLk rises to a high level in accordance with the input address. At this time, a voltage -Ve is applied between both electrodes of the capacitor C,
The polarization direction of all the domains of (2 @ n -1) having different coercive voltages is the first direction. The operation up to this point is the same as the second example of the read operation described in FIG. Therefore, the subsequent operations of the write operation example 2 are as follows.
This is also a rewrite operation of the second read operation example.

Next, at time T2, the potential of bit line BL is set to the Vcc level.

Next, at time T3, according to the write data j, the potential Vwbl (j) of the plate line PL is given by the following equation using V + (j) given by equation (1). Is set.

Vwbl (j) = Vcc-V + (j) Also in this case, the voltage V + (j) is applied to the capacitor C as in the first operation example.

Next, at time T4, the plate line PL becomes Vw
The voltage rises from bl (j) to the Vcc level.

Finally, at time 5, the selected word line WLk falls to the low level, and the write operation ends.

FIG. 11 shows an example (part 3) of a write operation to the memory cell MC.

First, the bit line BL is floated after being precharged to the Vcc level.

Next, at time T1, the selected word line WLk rises to a high level in accordance with the input address. Then, at time T2, the plate line falls from the Vcc level to the GND level. At this time, the voltage Ve is applied between both electrodes of the capacitor C, and has different coercive voltages (2n−
1) The polarization direction of all domains is the second direction. The operation up to this point is the same as the third read operation example described with reference to FIG. Therefore, the operation after the third example of the write operation is also the rewrite operation of the third example of the read operation.

Next, at time T3, in accordance with the write data j, the potential Vwbl (j) of the bit line BL connected to the memory cell MC is calculated using V- (j) given by equation (III). , Are set as given by:

Vwbl (j) = Vcc + V- (j) Next, at time T4, the plate line PL rises from the GND level to the Vcc level. At this time, a negative voltage V- (j) is applied to the capacitor C.

Next, at time T5, the bit line BL is set to Vwb.
It rises to the Vcc level from l (j).

Finally, at time 6, the selected word line WLk falls to low level, and the write operation ends.

FIG. 12 shows an example (part 4) of a write operation to the memory cell MC.

First, the bit line BL is floated after being precharged to the Vcc level. Further, the plate line PL is set to the GND level.

Next, at time T1, the selected word line WLk rises to a high level according to the input address. At this time, the voltage Ve is applied between the two electrodes of the capacitor C, and the polarization directions of all the (2 n -1) domains having different coercive voltages become the second direction. The operation up to this point is the same as the fourth read operation example described with reference to FIG. Therefore, the operation after the fourth example of the write operation is also the rewrite operation of the fourth example of the read operation.

Next, at time T2, the potential of bit line BL is set to the GND level.

Next, at time T3, the potential Vwbl (j) of the plate line PL is calculated according to the formula (II) according to the write data j.
Using V- (j) given by I), it is set as given by the following equation.

Vwbl (j) = Vcc + V- (j) Also in this case, a negative voltage V- (j) is applied to the capacitor C as in the third operation example.

Next, at time T4, the plate line PL becomes Vw
bl (j) falls to the GND level.

Finally, at time T5, the selected word line WLk
Falls to a low level, ending the write operation.

[0086]

As described above, by using the semiconductor memory device of the present invention, in a nonvolatile semiconductor memory device using a ferroelectric material for a capacitor, one memory cell has an integer of N or more, which is 2 or more. A multi-level operation of performing read and write operations by storing bit information becomes possible, and a semiconductor memory device with a higher degree of integration under the same device rules as in the past can be realized.

[Brief description of the drawings]

FIG. 1 shows a sense amplifier circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory cell using a ferroelectric capacitor and its connection, which exist in the embodiment shown in FIG. 1;

FIG. 3 is an equivalent circuit of a ferroelectric capacitor existing in the memory cell shown in FIG. 2;

FIG. 4 is a polarization characteristic diagram of a partial domain C (j) of the ferroelectric capacitor shown in FIG.

FIG. 5 is a circuit diagram showing an example 1 of a read operation of the embodiment shown in FIG. 1;

FIG. 6 is a circuit diagram showing a read operation example 2 of the embodiment shown in FIG. 1;

FIG. 7 is a circuit diagram showing a third read operation example of the embodiment shown in FIG. 1;

FIG. 8 is a circuit diagram showing a fourth read operation example of the embodiment shown in FIG. 1;

FIG. 9 is a circuit diagram showing a first example of a write operation of the embodiment shown in FIG. 1;

FIG. 10 is a circuit diagram showing a write operation example 2 of the embodiment shown in FIG. 1;

FIG. 11 is a circuit diagram showing a third example of the write operation of the embodiment shown in FIG. 1;

FIG. 12 is a circuit diagram showing a fourth example of the write operation of the embodiment shown in FIG. 1;

FIG. 13 is a circuit diagram showing a memory section and a sense amplifier section of a conventional semiconductor memory device.

FIG. 14 is a schematic diagram of a configuration of a conventional 1-bit cell.

FIG. 15 is a schematic diagram of a configuration of a 2-bit cell.

FIG. 16 is a schematic diagram of another 2-bit cell.

FIG. 17 is a schematic diagram of a configuration for obtaining 2-bit information using a conventional 1-bit cell.

FIG. 18 is a schematic configuration diagram of a conventional 2-bit memory cell array semiconductor memory device.

[Explanation of symbols]

WL0, ..., WLk, ... Word line WLk Selected word line BL, BLB Bit line pair BL1, BL1B, ..., BLn, BLnB Split bit line pair PL plate line SWT1, ..., SWTn-1 Transfer gate TG1, ..., TGn- 1 Transfer gate control signal lines SA1, SAn Sense amplifier circuit CSL Column selection lines 1/1, 1, ..., 1 / 0n 1/0 line MC memory cells CB1, ..., CBn Parasitic capacitance Cc1, ..., Ccn-1 of divided bit lines Coupling capacitance C Ferroelectric capacitor Tr Selection transistor C (j) Domain having coercive voltage Vc (j)

Claims (8)

[Claims] 1. A plurality of memory cells each having a switching transistor and one electrode connected to one of a source and a drain of the transistor and each including a capacitor formed of a ferroelectric material, in a row direction and a column. A memory cell array arranged in a direction, a source of a transistor of each memory cell in a corresponding column provided corresponding to each column of the plurality of memory cells,
A plurality of bit line pairs connected to the other of the drains to transmit write data and read data of the memory cells; and a memory of a corresponding row provided corresponding to each row of the plurality of memory cells. A plurality of word lines connected to the gates of the transistors of the cells to make the transistors conductive when the transistors are at a selected level; at least one plate line connected to the other electrode of the capacitor of each of the plurality of memory cells; A plurality of sense amplifier circuits that sense and amplify data read on the pair of bit lines; a reference potential generation circuit that generates a reference potential input to the plurality of sense amplifier circuits; An X decoder circuit for setting a predetermined word line to a selection level at a predetermined timing; A semiconductor memory device having a plate line potential generating circuit for applying a plate line potential to a line at a predetermined timing and storing n-bit information that is an integer of 2 or more in one memory cell; A semiconductor memory device wherein sense amplification of each bit is sequentially performed to a least significant bit, and a sense level of a lower bit is changed using a sense result of an upper bit. 2. The plurality of bit line pairs are each divided into n divided bit line pairs, each of the divided bit line pairs is connected to a sense amplifier circuit, and the divided bit line pairs are connected in tandem by a transfer gate. 2. The semiconductor memory device according to claim 1, wherein a capacitance element is connected between the complement of the pair of divided bit lines connected in cascade. 3. A switching transistor, and a plurality of capacitors each having one electrode connected to one of a source and a drain of the transistor and formed of a ferroelectric material and arranged in a row direction and a column direction. A memory cell array including memory cells of: a source of a transistor of each memory cell in a corresponding column provided corresponding to each column of the plurality of memory cells;
A plurality of bit line pairs connected to the other of the drains to transmit write data and read data of the memory cells; and a memory of a corresponding row provided corresponding to each row of the plurality of memory cells. A plurality of word lines connected to the gates of the transistors of the cells to make the transistors conductive when at a selected level; one or more plate lines connected to the other electrode of the capacitor of each of the plurality of memory cells; A plurality of sense amplifier circuits for sensing and amplifying data read on the plurality of bit line pairs; a reference potential generating circuit for generating a reference potential input to the plurality of sense amplifier circuits; and a plurality of word lines An X decoder circuit for setting a predetermined word line to a selected level at a predetermined timing; The predetermined plate line among the plurality of plate lines, and a plate line voltage generating circuit for applying a plate line voltage at a predetermined timing, n in one memory cell
In the semiconductor memory device storing bit information, the ferroelectric material in the memory cell has different coercive voltages from a first voltage to a (2n-1) th voltage (2n-1). A predetermined word line of the plurality of word lines to a selected level, a transistor of the selected memory cell to a conductive state, and the bit line and the plate line connected to the memory cell. In the meantime, by applying a negative voltage whose absolute value is equal to or greater than the coercive voltage, the polarization directions of all the domains are set to the first direction, and the bit line connected to the selected memory cell and the bit line are connected to each other. Between the plate lines, the (2n-2) th voltage ≦ V + (2n−2) <(2n−
1) A positive write voltage having a relationship of the following voltage is applied, and the polarization direction of the domain having a coercive voltage equal to or lower than the write voltage is changed to a second direction having a direction opposite to the first direction. The bit line and the plate line connected to the selected memory cell are set to the same potential, the predetermined word line is set to a non-selection level, and the transistor of the selected memory cell is turned off. A semiconductor memory device, wherein n-bit information is written in the memory cell. 4. The semiconductor memory device according to claim 3, wherein after the bit line connected to the selected memory cell falls to a low level, the bit line is floated, and the predetermined word line is Select level, turning on the transistor of the selected memory cell, raising the plate line connected to the selected memory cell from low level to high level, and transmitting data from the memory cell on the bit line. The potential of the bit line is set to the write voltage in accordance with the read and 2n write data, the potential of the plate line is dropped from a high level to a low level, and the potential of the bit line is dropped to a GND level. 4. The semiconductor memory device according to claim 3, wherein: 5. The method according to claim 1, wherein the plate line connected to the selected memory cell is set to a high level, and the bit line connected to the selected memory cell is lowered to a low level. A floating state, the predetermined word line is set to a selected level, a transistor of the selected memory cell is turned on, data is read from the memory cell on the bit line, and the bit line is raised to a high level. 4. The semiconductor memory according to claim 3, wherein the potential of said plate line is set to Vcc-V + (2 @ n -1) in accordance with 2 @ n write data, and the potential of said plate line is raised to a high level. apparatus. 6. A switching transistor and a plurality of capacitors each having one electrode connected to one of a source and a drain of the transistor and formed of a ferroelectric material and provided in a row direction and a column direction. A memory cell array including memory cells of: a source of a transistor of each memory cell in a corresponding column provided corresponding to each column of the plurality of memory cells;
A plurality of bit line pairs connected to the other of the drains to transmit write data and read data of the memory cells; and a memory of a corresponding row provided corresponding to each row of the plurality of memory cells. A plurality of word lines connected to the gates of the transistors of the cells to make the transistors conductive when at a selected level; one or more plate lines connected to the other electrode of the capacitor of each of the plurality of memory cells; A plurality of sense amplifier circuits for sensing and amplifying data read on the plurality of bit line pairs; a reference potential generating circuit for generating a reference potential input to the plurality of sense amplifier circuits; and a plurality of word lines An X decoder circuit for setting a predetermined word line to a selected level at a predetermined timing; The predetermined plate line among the plurality of plate lines, and a plate line voltage generating circuit for applying a plate line voltage at a predetermined timing, n in one memory cell
In the semiconductor memory device storing bit information, the ferroelectric material in the memory cell has different coercive voltages from a first voltage to a (2n-1) th voltage (2n-1). A predetermined word line of the plurality of word lines to a selected level, a transistor of the selected memory cell to a conductive state, and the bit line and the plate line connected to the memory cell. In the meantime, by applying a positive voltage equal to or higher than the coercive voltage, the polarization direction of all the domains is changed to the second direction, and the bit line and the plate line connected to the selected memory cell are selected. In the meantime, the (2n-1) th voltage <V- (2n-2) ≤ (2n-
2) A negative write voltage having a relationship of voltage is applied to each of the domains, and the domain having the coercive voltage equal to or less than the absolute value of the write voltage has a polarization direction opposite to the second direction. The bit line and the plate line connected to the selected memory cell are set to the same potential, the predetermined word line is set to a non-selection level, and the transistor of the selected memory cell is turned off. Thereby writing n-bit information into the memory cells. 7. After the bit line connected to the selected memory cell is raised to the Vcc level, the bit line is set in a floating state, the predetermined word line is set to a selection level, and the selected memory is selected. The transistor of the cell is turned on, the plate line connected to the selected memory cell falls from the Vcc level to the GND level, data is read from the memory cell on the bit line, and 2n write data are written. The potential of the bit line is set to Vcc + V (2 @ n -1), the potential of the plate line rises from a low level to a high level, and the potential of the bit line rises to a high level. Item 7. A semiconductor memory device according to item 6. 8. The method sets the plate line connected to the selected memory cell to a low level, raises the bit line connected to the selected memory cell to the Vcc level, and then sets the bit line to the low level. A floating state, the predetermined word line to a selected level, a transistor of the selected memory cell to a conductive state, reading of data from the memory cell on the bit line, a fall of the bit line to GND level, 7. The semiconductor memory device according to claim 6, wherein the potential of said plate line is set to -V (2 @ n -1) in accordance with 2 @ n write data, and the potential of said plate line falls to a GND level. .