GB2318230A

GB2318230A - A ferroelectric memory device and a nondestructive accessing method thereof

Info

Publication number: GB2318230A
Application number: GB9717915A
Authority: GB
Inventors: Byung-Gil Jeon; Chul-Sung Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1996-10-09
Filing date: 1997-08-22
Publication date: 1998-04-15
Anticipated expiration: 2017-08-22
Also published as: JPH10125078A; GB9717915D0; US5835400A; KR19980026421A; DE19739088A1; TW338155B; KR100206713B1; GB2318230B

Abstract

A ferroelectric memory device includes a plurality of memory cells each consisting of an access transistor (NO) having a drain connected to a bit line (BL1) and a gate connected to a word line (WL1), and a ferroelectric capacitor (C) having a predetermined hysteresis characteristic and a first plate connected to the source of the access transistor. The ferroelectric memory device further includes a sense amplifier (100n) for comparing a developed voltage level of the bit line (3Ln) with a predetermined reference voltage, to amplify a difference therebetween, in a read mode. The ferroelectric memory device further includes a pulse generator (20) for selectively supplying a write signal having a constant first level or one positive pulse of a second level to a second plate of the ferroelectric capacitor (C), in a write mode, and for supplying a nondestructive read signal having a positive pulse of a third level to the second plate, in a read mode.

Description

2318230 A FERROELECTRIC MEMORY DEVICE AND A NONDESTRUCTIVE ACCESSING

METHOD THEREOF The present invention relates to a semiconductor memory device, and more particularly, to a ferroelectric memory 5 device and a nondestructive accessing method thereof.

In general, a memory cell of a ferroelectric memory device includes a capacitor formed of a ferroelectric material, and the ferroelectric capacitor is comprised of two conductive layers with a ferroelectric material layer formed therebetween. The ferroelectric material has a hysteresis characteristic, and is in a certain polarization state even in the case that no power is supplied. The polarization state is stored in the ferroelectric material, and data is stored in the ferroelectric memory device according to the polarization state.

In an initial introduction of the ferroelectric memory device, after reading the state of a memory cell, i.e., the state of the respective ferroelectric capacitor, the polarization state of the ferroelectric capacitor is changed. This is called destructive read. Accordingly, additional time for returning to the initial polarization state is required. Therefore, cycle time is long. Also, fatigue, degradation and imprint are caused by changing the polarization state. These reduce the life span of the ferroelectric capacitor. To solve the above problems of the destructive read, there has been developed a nondestructive read method.

A conventional ferroelectric memory device having a nondestructive read scheme is disclosed in U.S. Patent No. 5,262,982, 11Nondestructive reading of a ferroelectric capacitor".

FIG. 1 is a circuit diagram showing a memory array and a sense amplifier of a ferroelectric memory device disclosed in the above Patent.

Referring to FIG. 1, the conventional ferroelectric memory device includes driving lines DLl through DLN; bit lines BL1 through BLN; at least one memory cell 100 each connected between one of the driving lines DLl through DLN and one of the bit lines BL1 through BLN, having an access transistor 102 and a ferroelectric capacitor 104 serially connected to the access transistor 102; word lines WL1 through WLN controlling the access transistor 102; a sense amplifying circuit 106; and a timing control circuit 130.

The ferroelectric memory device shown in FIG. 1 operates according to timing conditions shown in FIG. 2. Here, a positive pulse is applied to one electrode of a ferroelectric capacitor 104, and then the resultant state is stored in a capacitor 110. Subsequently, a bit line BL1 is precharged and a negative pulse is applied, and then the resultant state is stored in a capacitor 112. When a level of the capacitor 112 is stable, the levels of two capacitors 110 and 112 are summed. If the result is a positive value, it is stored in a latch 132 as logic 'high', however, if a negative value, it is stored in a latch 132 as logic low'. Then, data stored in the latch 132 is read through a data 2 output line DOUT-1.

Therefore, by the nondestructive read scheme of a conventional f erroelectric memory device as shown in FIG. 1, positive and negative pulses are applied in a constant time interval, so that each state is stored in one of two capacitors, respectively, and the levels of the two capacitors are summed, and then the sum of the levels of the two capacitors is sensed. Accordingly, read cycle time is increased, which causes deterioration in the performance. Also, the selected ferroelectric capacitor every data reading, alternately receives positive and negative pulses, which causes reduction in the life span.

According to a first aspect of the present invention, there is provided a ferroelectric memory device including a plurality of memory cells each consisting of an access transistor having a drain connected to a bit line and a gate connected to a word line, and of a ferroelectric capacitor having a predetermined hysteresis characteristic and a first plate connected to the source of the access transistor. The ferroelectric memory device further includes a sense amplifier in which a developed voltage level of the bit line is compared with a reference voltage, and the difference therebetween is amplified, in a read mode. The ferroelectric memory device further includes a pulse generator in which a write signal having a constant first level or one positive pulse of a second level is selectively supplied to a second plate of the ferroelectric capacitor, in a write mode, and a nondestructive read signal having a 3 positive pulse of a third level is supplied to a second plate, in read mode.

At this time, the third level of the nondestructive read signal, corresponds to a voltage level such that a polarization state of the ferroelectric capacitor is not changed. The positive pulse of the nondestructive read signal is generated in a time interval shorter than a time interval in which the word line is enabled. The first level of the write signal is a ground voltage level, and the second level is a power supply voltage level.

According to a second aspect of the present invention, there is provided a method of reading data of a semiconductor device having at least one memory cell consisting of an access transistor and a drain connected to a bit line and a gate connected to a word line, and a ferroelectric capacitor having a predetermined hysteresis characteristic, a first plate connected to the source of the access transistor and a second plate receiving a read pulse, comprising the steps of:

applying a voltage as the read pulse, having a voltage level such that the predetermined hysteresis characteristic of the ferroelectric capacitor is not changed, to the second plate during a time interval shorter than a time interval for which the word line is enabled; comparing a developed voltage level of the bit line with a predetermined reference voltage in a time interval for which the read pulse is applied, and amplifying the difference in voltage therebetween, to evaluate the data 4 level stored in the ferroelectric capacitor; and latching the evaluated data level, and then supplying it externally.

According to a third aspect of the present invention, there is provided a method of writing data of a semiconductor memory device including at least one memory cell consisting of an access transistor having a drain connected to a bit line and a gate connected to a word line, and a ferroelectric capacitor having a predetermined hysteresis characteristic, a first plate connected to the source of the access transistor and a second plate receiving a write pulse, comprising the steps of: supplying a voltage set according to the level of external data applied through a data input portion to the bit line; and is selectively supplying a signal, having a constant first level or one positive pulse of a second level, as the write signal to the second plate, for a time interval shorter than a time interval for which the word line is enabled, according to the external data level. 20 According to a fourth aspect of the present invention, there is provided a method of sensing data of a semiconductor memory device having a plurality of memory cells each consisting of an access transistor having a source connected to a bit line and a gate connected to a word line, and a ferroelectric capacitor having a predetermined hystersis characteristic and a first plate connected to a drain of the access transistor and a second plate receiving a read pulse, comprising the steps of:

applying a voltage as the read pulse such that the predetermined hysteresis characteristic of the ferroelectric capacitor is not changed, from the time in which the word line is enabled to the time in which the word line is disabled, to the second plate; and comparing a developed voltage level of the bit line with a reference voltage in a time interval for which the read pulse is applied, and amplifying the difference in voltage therebetween, to sense a data level showing the state of polarization of the ferroelectric capacitor.

An example of the present invention will now be described in detail with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram showing a memory array and a sense amplifier of a conventional ferroelectric memory device; FIG. 2 is a timing diagram of each signal of the ferroelectric memory device shown in FIG. 1; FIG. 3 is a graph showing a hysteresis characteristic of a ferroelectric capacitor of a ferroelectric memory device according to the present invention; FIG. 4 is a circuit diagram showing a memory array and a sense amplifier of a ferroelectric memory device according to the present invention; FIGS. 5 and 6 are timing diagrams of the read operations of the ferroelectric memory device of FIG. 4 in the cases that read data are 101 and Ill, respectively; 6 FIGS. 7 and 8 are timing diagrams of the write operations of the ferroelectric memory device of FIG. 4 in the cases that write data of '01 and 11', respectively, are externally' applied; and FIG. 9 is a circuit diagram showing the structure of a 5 sense amplifier of the ferroelectric memory device of FIG. 4.

FIG. 3 shows a hysteresis characteristic of a ferroelectric capacitor in a ferroelectric memory device according to the present invention.

When a voltage -Va, lower than a forced voltage -Vc which changes the polarity state of a capacitor, is applied to one electrode of the ferroelectric capacitor, i.e., one plate, an electric charge according to the voltage -Va is induced to the other electrode thereof, i.e., the other plate. If the initial state of the ferroelectric capacitor has polarization of node 'A', i.e., +Pr, an electric charge of dQ1 is induced to the other plate. However, if the initial state of the ferroelectric capacitor has polarization of node 'B', i.e., -Pr, an electric charge of dQO is induced to the other plate. The characteristic, that even though the same nondestructive voltage is applied, different electric charges can be obtained according to the initial state of the ferroelectric capacitor, is adapted for a principle of data sensing according to the present invention.

Referring to FIG. 4, a memory cell array is comprised of a plurality of unit memory cells each including an access 7 transistor NO having a drain terminal connected to a bit line BL1 and a gate terminal connected to a word line WL1, and a ferroelectric capacitor CO having a first plate connected to a source terminal of the access transistor NO. In FIG. 4, dotted lines indicate connections to n horizontal unit memory cells and m vertical memory cells. The ferroelectric capacitor in each of the unit memory cells has the predetermined hysteresis characteristic as shown in FIG. 3. Also, the access transistor in each of the unit memory cells is comprised of an NMOS transistor, and electrically connects one plate of the capacitor to the bit line corresponding thereto, in response to the enabling of the corresponding word line. Also, one sense amplifier is connected to one bit line corresponding thereto. That is, a sense amplifier 100 is connected to a bit line BL1, and a sense amplifier 100n is connected to a bit line BLn. In the read mode, each of the sense amplifiers which is operationally connected to the bit line corresponding thereto, compares a developed voltage level of the bit line to reference. voltages ref through refn, respectively, and amplifies a difference therebetween, to thereby sense a data level indicating the polarization state of the ferroelectric capacitor.

A pulse generator 20 connected between a decoder 10 and a data input portion 30 selectively supplies a nondestructive read signal, or write signals of first and second levels, to the second plate of the capacitor during a time interval shorter than a time interval in which a word 8 line, selected by a decoding operation of the decoder 10, is enabled. That is, the pulse generator 20, in a write mode, selectively supplies a write signal having one positive pulse of a constant f irst level or a second level to the second plate of the ferroelectric capacitor, and in a read mode, supplies a destructive read signal having a positive pulse of a third level to the second plate. Accordingly, in the write mode, external data applied through the data input portion 30 is written to the memory cell, and in the read mode, the sensed data level is read nondestructively from the sense amplifier without changing the polarization state of the ferroelectric capacitor.

FIG. 9 is a circuit diagram showing an example of sense amplifiers 100 through 100n of the ferroelectric memory device shown in FIG. 4. Referring to FIG. 9, the sense amplifier includes a driving portion 110 and a latch sensing portion 120. The driving portion 110 is comprised of two inverters 111 and 112 which are connected in series with each other. The latch sensing portion 120 is comprised of two PMOS and two NMOS transistors 121 through 124 having gate terminals which are cross-coupled.

FIG. 5 is a timing diagram of a read operation, showing each signal of the ferroelectric memory device shown in FIG. 4, in the case of reading data of '01.

Referring to FIG. 5, a signal having a waveform SA is supplied by the decoder 10 to one selected from word lines WL1 through WLm connected respectively to gates of the NMOS access transistors of FIG. 4. A nondestructive read signal 9 PL, as shown in a pulse waveform 5B, is supplied by the pulse generator 20 to the second plate of the ferroelectric capacitor connected to the selected NMOS access transistor. Also, when a sensing operation signal SA is applied to a sense amplifier 100 according to timing as shown in a waveform 5C, electric potential of two input terminals BL and ref of the sense amplif ier shown in FIG. 9 have a waveform 5D, and the output of the sense amplifier 100 shows a waveform SE, in which data '0' is shown. This is because in the case that the initial state of the ferroelectric capacitor is of the polarization node B of FIG. 3, a pulse waveform 5B having a voltage level as high as that of the nondestructive voltage level Va, is supplied during a period of tl-t3. In FIG. 5, during a period of ti-t2, a change of electric charge dQO corresponding to the nondestructive voltage level Va in the state B of the ferroelectric capacitor, is transmitted to the selected bit line. Accordingly, levels of the two input portions BL and ref of the sense amplifier are separated by a small difference as shown in waveform 5D. Subsequently, during a period of t2- t3, the sense amplifier 100, which performs a sensing operation according to the sensing operation signal SA, compares a voltage dVO corresponding to charge dQO supplied to the input terminal BL with a reference voltage supplied to the input terminal ref, amplifies the difference between the two levels, and evaluates the data as '01. At this time, the reference voltage ref increases to a predetermined level with reference to a ground voltage level, i.e., the level of the bit line of 0 [volt]. Here, it is preferable that the level of the reference voltage ref is set to half of the level obtained by summing a voltage dVO, induced by charge dQO in the case of data of logic level '0', with a voltage dV1 induced by the charge dQ1 in the case of data of logic level 'l'.

Referring to FIG. 6, a signal having a waveform as shown in 6A is supplied to one selected by a decoder 10 from word lines WL1 through WLm connected respectively to gates of the NMOS access transistors of FIG. 4. A nondestructive read signal PL, as shown in waveform 6B, is supplied by the pulse generator 20 to the second plate of the ferroelectric capacitor connected to the selected NMOS access transistor. Also, when a sensing operation signal SA is applied to a sense amplifier 100 according to timing as shown in a waveform 6C, electric potential of two input terminals BL and ref of the sense amplifier of FIG. 9 have a waveform 6D, and the output of the sense amplifier 100 shows a waveform 6E, in which data ' 1 1 is shown. This is because in the case that an initial state of the ferroelectric capacitor is of the polarization node A of FIG. 3, a pulse waveform 6B, having a voltage level as high as that of the nondestructive voltage level Va, is supplied during a period of tl-t3. In FIG. 6, during a period of tlt2, a change of electric charge dQl, corresponding to the nondestructive voltage level Va in the state A of the ferroelectric capacitor, is transmitted to the selected bit line. Accordingly, levels of the two input terminals BL and ref of the sense amplifier 11 are separated by a small difference as shown in waveform 6D. Subsequently, during the period of t2-t3, the sense amplifier 100 starts a sensing operation according to the sensing operation signal SA, compares a voltage dvl corresponding to charge dQ1 supplied to the input terminal 5 BL with a reference voltage supplied to the input terminal ref, amplifies the difference between the two levels, and evaluates the data as 111. At this time, the voltage of the bit line increases to a predetermined level with reference to a ground voltage level, i.e., a level of the reference voltage ref of Mvolt]. In FIGS. 5 and 6, the level of the nondestructive read signal PL around a point of time t3 descends to O[volt] to generate a refresh operation to realize the nondestructive read of the ferroelectric capacitor. That is, when the level of the nondestructive read signal PL descends to Mvolt] after the point of time t3, the potential difference between the plates of the ferroelectric capacitor CO becomes a voltage as high as a saturation voltage Vs of FIG. 3. Accordingly, the capacitor is refreshed to its initial state by the saturation voltage, to maintain the capacitor in a stable state. According to the operational principle based on the pulse response characteristic of the capacitor, the nondestructive read signal is supplied only to the second plate of the capacitor during the read mode, in a time interval shorter than the time interval in which a word line selected by a decoder 10 is enabled, to thereby read the level of the =destructively- sensed data without changing the state of 12 polarization of the ferroelectric capacitor. Accordingly, read cycle time for reading data is reduced, to realize a read operation at a high speed.

Referring to FIG. 7, a signal having a waveform 7A is supplied to one selected by a decoder 10 from word lines WL1 through WLm connected respectively to gates of the NMOS access transistors of FIG. 4. A write signal PL of a constant level, for example, 0 [volt], is supplied by the pulse generator 20 to the second plate of the ferroelectric capacitor connected to the selected NMOS access transistor, the waveform of which is shown in 7B. Also, when a sensing operation signal SA of the sense amplifier 100 is fixed at O[volt] as in the waveform 7C, electric potential of the bit line receiving the output voltage of the data input portion 30 becomes a high level as in the waveform 7D, to thereby place the ferroelectric capacitor in the state of polarization of node A of FIG. 3, regardless of the initial state. This means a write operation of data 'l' to the ferroelectric capacitor occurs during a period of tl- t2.

Referring to FIG. 8, a signal having a waveform 8A is supplied to one selected by a decoder 10 from word lines WL1 through WLm connected respectively to gates of the NMOS access transistors of FIG. 4. A write signal PL having a pulse of a second level, for example, a power supply voltage Vcc, is supplied by the pulse generator 20 to the second plate of the ferroelectric capacitor connected to the selected NMOS access transistor, the waveform of which is shown in 7B, during a period of tl-t2. Also, when a sensing 13 operation signal SA of the sense amplifier 100 is fixed at 0 [volt] as in the waveform 8C, electric potential of the bit line receiving the output voltage of the data input portion 30 becomes O[volt] as in the waveform 8D, to thereby place the ferroelectric capacitor in a state of polarization of node 'B' of FIG. 3, regardless of the initial state. This means a write operation of data '0' to the ferroelectric capacitor occurs during a period of ti-t2.

In the above write mode, the level of the write signal PL is the first or second level according to the logic state of data to be written, so that the potential difference between the first plate of the ferroelectric capacitor, connected through the drain/source channel of the NMOS access transistor, and the second plate facing the first plate, has a level of saturation voltage Vs or -Vs.

is In the present invention, only a single pulse is supplied during the read mode, to nondestructively sense data without changing a state of polarization of the f erroelectric capacitor. Therefore, read cycle time for reading data is reduced. Also, due to the single pulse, the life span of the ferroelectric capacitor can increase.

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Claims

1. A semiconductor memory device comprising: a plurality of memory cells each consisting of an access transistor having a drain connected to a bit line and a gate connected to a word line, and a ferroelectric capacitor having a predetermined hysteresis characteristic and a first plate connected to the source of the access transistor; a sense amplifier for comparing a developed voltage level of the bit line with a reference voltage to amplify a voltage difference therebetween, while in a read mode; and a pulse generator for selectively supplying a write signal having a constant first level or one positive pulse of a second level to a second plate of the ferroelectric capacitor, while in a write mode, and for supplying a nondestructive read signal having a positive pulse of a third level to the second plate, while in a read mode.

2. The semiconductor memory device of claim 1, wherein the third level of the nondestructive read signal is a voltage level such that a polarization state of the ferroelectric capacitor is not changed.

3. The semiconductor memory device of claim 1, wherein the positive pulse of the nondestructive read signal is generated during a time interval shorter than the time interval for which the word line is enabled.

4. The semiconductor memory device of claim 1, wherein the nondestructive read signal having the positive pulse of a third level is supplied to the second plate in the read mode regardless of a level of data stored in the ferroelectric capacitor.

5. The semiconductor memory device of claim 1, wherein the first level of the write signal is a ground voltage level, and the second level thereof is a power supply level.

6. The semiconductor memory device of claim 1, wherein in the case that data having a high level is written in the write mode, a write signal having the constant first level is supplied to the second plate.

is

7. The semiconductor memory device of claim 1, wherein in the case that data having a low level is written in the write mode, a write signal having the positive pulse of the second level is supplied to the second plate.

8. The semiconductor memory device of claim 1, wherein a sensing operation of the sense amplifier is performed during the time interval of the positive pulse of the third level.

9. The semiconductor memory device of claim 1, wherein due to the predetermined hysteresis characteristic of the ferroelectric capacitor, although the same voltage is 16 applied to the second plate, electric charge on the bit line differs according to the initial state of stored data.

10. A method of reading data of a semiconductor memory device including at least one memory cell consisting of an access transistor having a drain connected to a bit line and a gate connected to a word line, and a ferroelectric capacitor having a predetermined hysteresis characteristic, a first plate connected to the source of the access transistor and a second plate receiving a read pulse, comprising the steps of:

applying a voltage as the read pulse, having a voltage level such that the predetermined hysteresis characteristic of the ferroelectric capacitor is not changed, to the second plate during a time interval shorter than a time interval for which the word line is enabled; comparing a developed voltage level of the bit line with a predetermined reference voltage in a time interval for which the read pulse is applied, and amplifying the difference in voltage therebetween, to evaluate the data level stored in the ferroelectric capacitor; and latching the evaluated data level, and then supplying it externally.

11. The method of reading data of claim 10, wherein due to the predetermined hysteresis characteristic of the ferroelectric capacitor, although the same voltage is applied to the second plate, electric charge on the bit line 17 differs according to the initial state of stored data.

12. A method of writing data of a semiconductor memory device including at least one memory cell consisting of an access transistor having a drain connected to a bit line and a gate connected to a word line, and a ferroelectric capacitor having a predetermined hysteresis characteristic, a first plate connected to the source of the access transistor and a second plate receiving a write pulse, comprising the steps of:

supplying a voltage set according to the level of external data applied through a data input portion to the bit line; and selectively supplying a signal, having a constant first level or one positive pulse of a second level, as the write signal to the second plate, for a time interval shorter than a time interval for which the word line is enabled, according to the external data level.

13. The method of writing data of claim 12, wherein the constant first level of the write signal is a ground voltage level, and the second level thereof is a power supply voltage level.

14. The method of writing data of claim 12, wherein in the case that the level of the external data is logic high in a write mode, a write signal having the constant first level is supplied to the second plate.

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15. The method of writing data of claim 12, wherein in the case that the level of the external data is logic low in a write mode, a write signal having a positive pulse of the second level is supplied to the second plate.

16. A method of sensing data of a semiconductor memory device having a plurality of memory cells each consisting of an access transistor having a source connected to a bit line and a gate connected to a word line, and a ferroelectric capacitor having a predetermined hystersis characteristic and a first plate connected to a drain of the access transistor and a second plate receiving a read pulse, comprising the steps of:

17. The method of sensing data of claim 16, wherein due to the predetermined hysteresis characteristic of the ferroelectric capacitor, although the same voltage is applied to the second plate, electric charge on the bit line differs according to the initial state of stored data.

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