JPH08263989A - Ferroelectric memory - Google Patents

Abstract

PURPOSE: To obtain a ferroelectric memory in which design of timing is easy when there is read-out and operational speed is high. CONSTITUTION: When read-out operation is started, first, after data '0' is written in a reference memory cell RMC, switching transistors Tr1 and RTr1 of a memory cell MC1 and a reference cell RMC1 making a pair, or switching transistors Tr2 and RTr2 of a memory cell MC2 and a reference cell RMC2 are controlled to a continuity state. Also, plate lines PL and RPL are set to the prescribed voltage, a potential appearing between bit lines BL1, BL2 making a pair is detected by a sense amplifier SA, and data is read out. After this, data of the memory cell MC1 or MC2 is rewritten successively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device utilizing polarization reversal of a ferroelectric substance.

[0002]

2. Description of the Related Art Various ferroelectric non-volatile memories for storing binary data by utilizing polarization reversal of a ferroelectric having a hysteresis characteristic as shown in FIG. 7 are currently proposed. However, as a typical one among them, one that configures one bit by two switching transistors and two ferroelectric capacitors (2Tr-2
(Cap method)) and one switching transistor and one ferroelectric capacitor constitute one bit (1Tr-1Cap method).

In the ferroelectric non-volatile memory, when the stored data is read, the polarization state of the memory cell is changed before and after reading the data. Will need to be written again. This is because the memory cell is 1Tr
It needs to be performed regardless of the -1Cap method and the 2Tr-2Cap method. Hereinafter, it will be described with reference to FIG. 7 that the polarization state of the memory cell is changed by reading this data.

When a voltage is first applied to a ferroelectric substance,
Since it is not in a polarized state, the origin O is the starting point and changes along the curve OD as the voltage increases. At point D, the polarization is saturated, and thereafter, the charge Q does not change significantly even if the voltage increases. Next, when the voltage is reduced, the voltage does not return to the point O, but passes through the point A and the point P1 to reach the point B. After that, the polarization is saturated similarly to the point D. When the voltage is increased from point B, C
Through the point, the point reaches the point D through the point P2, and the hysteresis characteristic is exhibited. The data stored in the memory cell corresponds to points A and B, where point A is data “1”.
Then, point B corresponds to data “0”. Therefore, for example, in the case of reading data "1", first, the reading operation based on a predetermined bias condition changes from point A (data "1") to point P1 to point B. That is, the polarization is inverted by the read operation. Therefore, rewriting is subsequently performed based on a predetermined bias condition, and point B (data “0”) → point C → point P2 → point D → point A (data “1”).
It is necessary to make a transition to and return to the state before reading.

Among such ferroelectric non-volatile memories, the 2Tr-2Cap type non-volatile memory can operate at a low voltage, but in terms of high integration, 1Tr-1Ca.
A non-volatile memory adopting the p method is suitable. next,
A basic configuration example and a specific read operation of the ferroelectric non-volatile memory adopting the 1Tr-1Cap method will be described with reference to the drawings.

FIG. 8 is a diagram showing a basic 1-bit configuration of a ferroelectric nonvolatile memory adopting the 1Tr-1Cap system. As shown in FIG. 8, this memory cell MC1 has a switching transistor Tr1 composed of an n-channel MOS transistor having a drain connected to the bit line BL1 and a ferroelectric having one electrode connected to the source of the switching transistor Tr1. Body capacitor F
1 bit is configured by C1, the gate of the switching transistor Tr1 is connected to the word line WL1, and the other electrode (plate electrode) of the ferroelectric capacitor FC1 is connected to the plate line PL.

In the non-volatile memory adopting the 1Tr-1Cap method, the reference switching transistor RTr1 having a drain connected to the bit line BL2 paired with the bit line BL1 and the source of the switching transistor RTr1 A reference cell RMC1 constituted by a reference ferroelectric capacitor RFC1 to which an electrode of is connected is provided, the gate of the switching transistor RTr1 is connected to the reference word line RWL1, and the ferroelectric capacitor R
The other electrode of FC1 is the reference plate line RPL
It is connected to the. It should be noted that a ferroelectric substance deteriorates with a decrease in the electric charge generated in the electrode as the number of polarization changes increases (Fat
igue) occurs. Therefore, the reference cell RCM1
Is controlled so that data "0" is always written and deterioration is unlikely to occur.

Next, regarding the data read operation in the non-volatile memory adopting the 1Tr-1Cap system,
This will be described with reference to the timing chart of FIG.

First, "0" V is applied to the bit lines BL1 and BL2 by a column control system (not shown), and then the bit lines BL1 and BL2 are opened. Then, (V _CC + αV, for example, α is 1V) is applied to word line WL1 by a row control system (not shown). As a result, the switching transistor Tr1 becomes conductive. Similarly, the word line RWL for referenceless
(V _CC + 1V) is applied to 1. As a result, the switching transistor RTr1 becomes conductive. In addition,
Set the set level of the word lines WL1 and RWL1 to (V _CC +1
The threshold voltage Vth of the switching transistor is set to “V” because the threshold voltage Vth of the switching transistor is 1 V or less, and thus “+1 V” is set to prevent a voltage drop due to the transistor.

Next, the power supply voltage V _CC is applied to the plate lines PL and RPL for a predetermined time. As a result, the potentials of the bit lines BL1 and BL2 change according to the polarization states of the ferroelectric capacitors FC1 and RFC2. And
Bit line BL2 to which the reference cell RMC1 is connected
Bit line BL1 connected to the potential of the memory cell MC1
The difference between the potential and the potential depending on the polarization state is detected by a sense amplifier (not shown). The reference cell RMC
Since 1 is used without reversing the polarization, the reference word line RWL1 rises to 0 V earlier than the reference plate line RPL in order not to enter the rewriting operation, that is, in order to write the “0” data. It is set to go down. That is, the reference plate line RPL is lowered to 0V after the switching transistor RTr1 is turned off.

On the normal memory cell MC1 side, since the above-mentioned rewriting is performed after the data is read, the word line WL1 is changed from (V _CC + 1V) to 0 V after the voltage is lowered to 0 V almost at the same time as the reference plate line RPL. It can be stopped. As a result, the switching transistor Tr
1 becomes non-conductive, and the read operation ends.

Further, FIG. 10 is a proposal in response to the reduction of the read margin in the circuit of FIG. 8 at the time of low voltage operation, and a ferroelectric non-volatile memory in which a preset transistor PRT1 is added to the reference cell. 3 is a circuit diagram showing a configuration example of FIG. Preset transistor PR
T1 is an n-channel MOS transistor, and is connected to the source of the switching transistor RTr1 and the reference potential line V.
It is connected between ss and the gate, and the gate is connected to the supply line of the signal RBP.

FIG. 11 is a timing chart during the read operation of the circuit of FIG. As shown in FIG. 11, in the circuit of FIG. 10, after the read operation is completed and the reference word line RWL1 is lowered from (V _CC + 1V) to 0V, the signal RPB is raised from 0V to (V _CC + 1V). Then, the preset transistor PRT1 is turned on to hold one electrode side of the ferroelectric capacitor RFC1 at the Vss level (0V), and then the reference plate line R
PL can be lowered to 0V. During this period, the data “0” is written in the reference cell RMC1. The subsequent operation is similar to that of the circuit of FIG. 8, and the plate line PL is set to 0V.
Then, the word line WL1 is lowered to 0V,
Rewriting of data in the normal memory cell MC1 is performed.

[0014]

However, in the circuits of FIGS. 8 and 10 described above, in the data read operation, the reference cell R is read in the latter half of the read cycle.
Since it is necessary to write “0” data in MC1 and then rewrite the normal memory cell MC1,
There are problems that control of each signal voltage is complicated, it is difficult to secure a margin, and high-speed operation is difficult.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a ferroelectric memory device which can be easily designed in timing and whose operating speed can be increased.

[0016]

In order to achieve the above object, the present invention provides a switching transistor connected to either one of a first bit line and a second bit line, a first electrode, a second electrode and both electrodes. A ferroelectric having a ferroelectric disposed between the first electrode and the switching transistor, and storing binary data according to the polarization direction of the ferroelectric according to the voltage applied to both electrodes. A memory cell including a capacitor and a reference cell having the same configuration as the memory cell and having a switching transistor connected to a bit line different from the bit line to which the memory cell is connected are provided. A ferroelectric memory device that reads the data by detecting the potential difference between both bit lines when the transistor is conductive. A means for applying a first voltage to a first electrode and a second voltage to a second electrode of the ferroelectric capacitor of the reference cell to write reference data in the reference cell during a read operation, After writing the reference data, the switching transistors of the memory cell and the reference cell are turned on, and the second voltage is applied to the second electrodes of the ferroelectric capacitors of the memory cell and the reference cell to read the data. And then rewriting data by applying a first voltage to the second electrode of the memory cell.

Further, in the ferroelectric memory device of the present invention, the means for writing the reference data includes means for precharging at least the bit line connected to the reference cell to the first voltage, and the bit line is connected to the bit line. Pre-charging is performed to make the switching transistor of the reference cell conductive, and the first voltage is applied to the first electrode.

Further, in the ferroelectric memory device of the present invention, the means for writing the reference data is a preset connected between the first electrode of the ferroelectric capacitor of the reference cell and the first voltage source. The transistor has a transistor, the preset transistor is turned on, and a first voltage is applied to the first electrode.

[0019]

According to the ferroelectric memory device of the present invention, during the read operation, first, the first voltage is applied to the first electrode of the ferroelectric capacitor of the reference cell and the second voltage is applied to the second electrode. A voltage is applied and reference data, for example, “0” data, is written in the reference cell. And
After writing the reference data to the reference cell, the switching transistors of the memory cell and the reference cell are controlled to be in the conductive state, and the second voltage is applied to the second electrodes of the ferroelectric capacitors of the memory cell and the reference cell. . Then, the potential difference between both bit lines appearing at this time is detected and the data is read. Next, after this data is read, the first voltage is applied to the second electrode of the memory cell to rewrite the data in the memory cell to be read.

[0020]

1 is a circuit diagram showing a basic 2-bit configuration of a ferroelectric non-volatile memory adopting the 1Tr-1Cap method according to the present invention, and the same configuration part as FIG. 8 showing a conventional example. Are denoted by the same reference numerals. That is, MC
1, MC2 are memory cells, RMC1, RMC2 are reference cells, BL1, BL2 are bit lines, WL1, WL
2 is a word line, PL is a plate line, RWL1, RWL2
Is a reference word line, RPL is a reference plate line, PCT1 and PCT2 are precharge transistors connected in series between bit lines BL1 and BL2, and PCL is a supply line of a precharge signal PC. Vss is a reference potential line, and SA is a sense amplifier to which the bit lines BL1 and BL2 are connected.

In this circuit, the memory cell MC1 and the reference cell RMC2 are connected to the bit line BL1.
The memory cell MC2 and the reference cell RMC1 are connected to the bit line BL2. Specifically, the drain of the switching transistor Tr1 of the memory cell MC1 is connected to the bit line BL1, and the drain of the switching transistor Tr2 of the memory cell MC2 is connected to the bit line BL.
Connected to 2. Similarly, the reference cell RMC
The drain of the first switching transistor RTr1 is connected to the bit line BL2, and the drain of the switching transistor RTr2 of the reference cell RMC2 is connected to the bit line BL1. The gate of the switching transistor Tr1 is connected to the word line WL1,
The gate of the switching transistor Tr2 is the word line W
L2, the gate of the switching transistor RTr1 is connected to the reference word line RWL1,
The gate of the switching transistor Tr2 is connected to the reference word line RWL2.

Further, this circuit adopts a divided cell plate configuration, and the plate electrode of the ferroelectric capacitor FC1 of the memory cell MC1 and the plate electrode of the ferroelectric capacitor FC2 of the memory cell MC2 are common plate lines. It is connected to PL. Similarly, the reference cell R
The plate electrode of the reference ferroelectric capacitor RFC1 of MC1 and the plate electrode of the reference ferroelectric capacitor RFC2 of the reference cell RMC2 are connected to a common reference plate line RPL. Also, the precharging transistors PCT1 and PC
The gate of T2 is connected to the precharge signal supply line PCL, and the connection point between the precharging transistors PCT1 and PCT2 is connected to the reference potential line Vss.

The non-volatile memory having such a structure has a basic circuit structure similar to that of the circuit of FIG.
The read system is different from the circuit of FIG. Specifically, when the read operation is started, first, the reference cell RM
After writing "0" data to C, the switching transistors Tr1 and RTr1 of the paired memory cell MC1 and reference cell RMC1 or the memory cell MC
2 and the switching transistors Tr2 and RTr2 of the reference cell RMC2 are made conductive, and the plate amplifiers PL and RPL are set to a predetermined voltage to generate a potential difference between the paired bit lines BL1 and BL2 by the sense amplifier SA. It is configured to detect and read data, and then rewrite data in the memory cell MC1 or MC2.

As described above, in this nonvolatile memory, when the read operation is started, first, the reference cell RMC
In addition to the decoder circuit, the pulse signal AIi (i = 0 to n) is internally generated based on the change in the address signal or the control signal output from the control system (not shown) in addition to the decoder circuit. Is generated, and the precharge signal supply line P is generated based on the pulse signal AIi.
Pulse signals PC and RB to be applied to CL and the reference plate line RPL are generated.

2 and 3 show a concrete circuit configuration example of the internal pulse generating circuit, and FIG. 2 shows the pulse signal AI.
FIG. 3 shows a generation circuit 10 for i, and FIG. 3 shows a generation circuit 20 for pulse signals PC and PB.

As shown in FIG. 2, the pulse generation circuit 10 includes inverters 101 to 110 and two-input NAND gate 1
11, 112 and a 2-input NOR gate 113. The inverters 101 to 103 are connected in series, and the input of the inverter 101 and the NAND gate 111 are connected.
One input is connected to the input line of the input signal IN which is the address signal ADR or the control signal CTL such as the chip enable signal, the output of the inverter 103 is connected to the other input of the NAND gate 111, and the output of the NAND gate 111. Is connected to one input of the NOR gate 113 via the inverter 108. With the above configuration, the rising edge of the input signal IN is detected. Similarly, the inverters 105 to 107 are connected in series, the input of the inverter 104 is connected to the input line of the input signal IN, the output is connected to one input of the NAND gate 112 and the input of the inverter 105, and the output of the inverter 107 is It is connected to the other input of the NAND gate 112, and the output of the NAND gate 112 is connected to the other input of the NOR gate 113 via the inverter 109. With the above configuration, the fall of the input signal IN is detected. Then, the output of the NOR gate 113 is level-inverted by the inverter 110 and the internal pulse signal AIi is output.

As shown in FIG. 3, the pulse generating circuit 20 includes a p-channel MOS transistor 201 and n-channel MOS transistors 202-0, 202-1, 20.
2-2, ... (202-n), and an inverter 203. p-channel MOS transistor 2
The source of 01 is connected to the supply line of the power supply voltage V _CC , the drain is connected to the input of the inverter 203, and the gate is connected to the ground line. The sources of the n-channel MOS transistors 202-0 to (202-n) are connected to the ground line, and the drains are connected to the drain of the p-channel MOS transistor 201. The internal pulse signals AI0 to AIn generated by the pulse generation circuit 10 of FIG. 2 are supplied to the gates of the n-channel MOS transistors 202-0 to (202-n), and the pulse signal PC or the pulse signal PC corresponding to the gate input is supplied. PB is the inverter 204
Output from the precharge signal supply line PCL of FIG.
Alternatively, it is supplied to the reference plate line RPL.

Next, the read operation with the above configuration will be described with reference to the timing chart of FIG.
Note that, here, a case where the storage data of the memory cell MC1 is read will be described as an example.

First, an input signal IN such as an address signal or a control signal output from a control system (not shown) is input to the pulse generation circuit 10, and a pulse signal AIi (i = 0 to n) is generated based on the change. , To the pulse generation circuit 20. Then, the pulse generation circuit 20
Then, the pulse signals PC and RB to be applied to the precharge signal supply line PCL and the reference plate line RPL are generated based on the input pulse signal AIi.

Then, of the pulse signals PC and PB generated by the pulse generation circuit 20, first, the pulse signal P
C is applied to the supply line PCL as a precharge signal. As a result, the precharge transistor PCT
1, PCT2 becomes conductive, bit lines BL1, BL
2 is precharged to 0V which is a reference potential. Next, the pulse signal PB changes to the reference plate line RPL.
Is applied to As a result, the reference cell RMC
1, RMC2 ferroelectric capacitors RFC1, RFC2
The power supply voltage V _CC is applied to the plate electrode of.

Next, a voltage of (V _CC + 1V) is applied to the reference word line RWL1. As a result, the reference switching transistor RTr1 becomes conductive, and 0 V of the bit line BL2 is applied to one electrode of the ferroelectric capacitor RFC1. As a result, "0" data is written in the reference cell RMC1. Then, application of the pulse signals AIi and PC is stopped, that is, dropped to 0V, then the pulse signal PB is dropped to 0V, and then the applied voltage of the word line RWL1 is dropped from (V _CC + 1V) to 0V. Then, the write cycle of the “0” data ends. And
Data is normally read from the memory cell MC1.

That is, (V _CC + 1V) is applied to the word line WL1 by a row control system (not shown). As a result, the switching transistor Tr1 becomes conductive. Similarly, (V _CC
+1 V) is applied. As a result, the switching transistor RTr1 becomes conductive. Next, the power supply voltage V _CC is applied to the plate lines PL and RPL for a predetermined time.
Thereby, the ferroelectric capacitors FC1 and RFC2
The potentials of the bit lines BL1 and BL2 change according to the polarization state of. Then, the difference between the potential of the bit line BL2 connected to the reference cell RMC1 and the potential according to the polarization state of the bit line BL1 connected to the memory cell MC1 is detected by the sense amplifier SA.

Next, after the plate line PL and the reference plate line RPL are lowered to 0V almost at the same time, the word line WL1 and the reference word line R are
WL1 is lowered from (V _CC + 1V) to 0V. At this time, on the normal memory cell MC1 side, data rewriting after data reading is performed in a row between the time when the plate line is lowered to 0V and the time when the word line is lowered to 0V.

On the side of the reference cell RMC1,
Since "0" data is always written at the start of reading and then the data read operation is started, it is not necessary to write "0" data immediately before rewriting of a normal memory cell as in the conventional case. Therefore, the fall timing of the reference word line RWL1 does not necessarily have to be performed before the fall of the plate line RPL.
As shown in FIG. 7, the timing can be set to fall at the same timing as the word line WL1, which facilitates the timing design.

As described above, according to this embodiment,
When the read operation is started, first, "0" data is written in the reference cell RMC, and then the switching transistors Tr1 and RTr1 of the paired memory cell MC1 and reference cell RMC1 or the switching of the memory cell MC2 and reference cell RMC2. The transistors Tr2 and RTr2 are controlled to be conductive, the plate lines PL and RPL are set to a predetermined voltage, and the potential difference appearing between the paired bit lines BL1 and BL2 is detected by the sense amplifier SA to read data, After that, the data of the memory cell MC1 or MC2 is rewritten, which facilitates the timing design of the read control signal and eliminates the need for the dummy cycle even when "0" data is not written in the cell. ,
As a result, the speed can be increased. Further, since "0" data is written, there is no fear of deterioration due to change in polarization direction.

FIG. 5 shows a basic structure of a ferroelectric non-volatile memory adopting the 1Tr-1Cap method according to the present invention and adding a preset transistor to a reference cell.
11 is a circuit diagram showing a bit configuration, and the same components as in FIG. 1 and FIG. 10 showing a conventional example are denoted by the same reference numerals.

In the reference cell RMC1a,
The preset transistor PRT1 which is an n-channel MOS transistor is a switching transistor RTr.
1 and the reference potential line Vss, and the gate is connected to the supply line of the signal RBP. Similarly, in the reference cell RMC2a, the n-channel MOS is
Preset transistor PRT2 consisting of transistors
Is connected between the source of the switching transistor RTr2 and the reference potential line Vss, and the gate is connected to the supply line of the signal RBP.

Also in the non-volatile memory of FIG. 5, when the read operation is started during the read operation, as in the case of the non-volatile memory of FIG.
After writing "0" data to the pair of memory cells M
C1 and the switching transistors Tr1 and RTr1 of the reference cell RMC1a, or the memory cell MC
2 and the switching transistors Tr2 and RTr2 of the reference cell RMC2a are turned on, and the plate lines PL and RPL are set to a predetermined voltage to generate a potential difference between the paired bit lines BL1 and BL2 by the sense amplifier SA. The data is detected and read, and then the data in the memory cell MC1 or MC2 is rewritten.

Also in this case, the pulse generation circuit shown in FIGS. 2 and 3 causes the pulse signal AIi (i = 0 to n) to be generated inside the apparatus based on the change of the address signal or the control signal output from the control system (not shown). Pulse signals RBP and RB to be applied to the reference plate line RPL and the preset signal supply line based on the pulse signal AIi, and the pulse signals RBP and RB are generated.
Is used to write "0" data to the reference cell. The application timing is, as shown in FIG. 6, the same as in the case of FIG. 4 described above.

That is, of the pulse signals PB and RBP generated by the pulse generation circuit 20, first, the pulse signal PB is applied to the reference plate line RPL. As a result, the reference cells RMC1a, RMC
The power supply voltage V _CC is applied to the plate electrodes of the ferroelectric capacitors RFC1 and RFC2 of 2a. Then the signal R
BP is supplied to the gates of the preset transistors PRT1 and PRT2. As a result, the preset transistors PRT1 and PRT2 are turned on, and 0 V is applied to one electrode of the ferroelectric capacitors RFC1 and RMC2. As a result, the reference cells RMC1a, RMC
Data “0” is written in 2a. Then, the application of the pulse signal PB is stopped, that is, dropped to 0V, and then the pulse signal RBP is dropped to 0V, and the write cycle of the “0” data ends. Then, normal data reading from the memory cell MC1 is performed. The read control in this case is as shown in FIG.
This is performed in the same manner as in the case of the nonvolatile memory of FIG. 1 shown in FIG.

Also in the case of this example, as in the case of the nonvolatile memory of FIG. 1 described above, on the side of the reference cell RMC,
Since "0" data is always written at the start of reading and then the data read operation is started, it is not necessary to write "0" data immediately before rewriting of a normal memory cell as in the conventional case. Therefore, the fall timing of the reference word line RWL1 is the signal RB
It is not always necessary to carry out before the rise of P or the fall of the plate line RPL, and as shown in FIG. 6, it is possible to fall at the same timing as the word line WL1.
Timing design is easy. That is, also in the case of the memory of FIG. 5, the same effect as that of the memory of FIG. 1 described above can be obtained.

[0042]

As described above, according to the ferroelectric memory device of the present invention, the timing design of the read control signal is facilitated, and the dummy cycle is unnecessary even when the reference data is not written in the cell. Therefore, there is an advantage that the speed can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a ferroelectric nonvolatile memory adopting a 1Tr-1Cap method according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of an internal pulse generation circuit according to the present invention.

FIG. 3 is a circuit diagram showing a configuration example of an internal pulse generation circuit according to the present invention.

FIG. 4 is a timing chart of potentials applied to each terminal when reading the circuit of FIG.

FIG. 5 employs the 1Tr-1Cap method according to the present invention,
FIG. 3 is a circuit diagram showing a basic 2-bit configuration of a ferroelectric nonvolatile memory in which a preset transistor is added to a reference cell.

6 is a timing chart of a potential applied to each terminal when reading the circuit of FIG.

FIG. 7 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor.

FIG. 8 is a diagram showing a basic 1-bit configuration of a ferroelectric non-volatile memory adopting a 1Tr-1Cap system.

9 is a timing chart of the potential applied to each terminal when reading the circuit of FIG.

FIG. 10 is a circuit diagram showing a basic 1-bit configuration of a ferroelectric nonvolatile memory adopting the 1Tr-1Cap system and adding a preset transistor to a reference cell.

11 is a timing chart of a potential applied to each terminal when reading the circuit of FIG.

[Explanation of symbols]

MC1, MC2 ... Memory cells RMC1, RMC2, RMC1a, RMC2a ... Reference cells Tr1, Tr2 ... Switching transistors RTr1, RTr2 ... Reference switching transistors FC1, FC2 ... Ferroelectric capacitors RFC1, RFC2 ... Reference ferroelectric capacitors BL1, BL2 ... Bit line WL1, WL2 ... Word line RWL1, RWL2 ... Reference word line PL ... Plate line RPL ... Reference plate line 10, 20 ... Pulse generation circuit

Claims (3)

[Claims] 1. A switching transistor having a switching transistor connected to either one of a first bit line and a second bit line, and a ferroelectric substance arranged between the first and second electrodes and both electrodes. A first capacitor is connected to the first electrode, and a memory cell having a ferroelectric capacitor that stores binary data according to a polarization direction of the ferroelectric substance according to a voltage applied to both electrodes and a memory cell having the same configuration as the memory cell The switching transistor has a bit line to which the memory cell is connected and a reference cell connected to a different bit line, and a potential difference between the bit line when the switching transistor of the memory cell and the reference cell is in a conductive state. A ferroelectric memory device for detecting and reading data, wherein a ferroelectric memory device for inducing a reference cell during a read operation. Means for applying a first voltage to the first electrode and a second voltage to the second electrode of the body capacitor to write reference data in the reference cell, and the memory cell and the reference cell after writing the reference data. After making the switching transistor conductive, the second voltage is applied to the second electrodes of the ferroelectric capacitors of the memory cell and the reference cell to read the data, and then the second cell of the memory cell is read.
And a means for rewriting data by applying a first voltage to the electrodes of the ferroelectric memory device. 2. The means for writing the reference data includes means for precharging at least a bit line to which a reference cell is connected to a first voltage, precharging the bit line, and switching transistor of the reference cell. The ferroelectric memory device according to claim 1, wherein the first voltage is applied to the first electrode in a conductive state. 3. The means for writing the reference data has a preset transistor connected between a first electrode of the ferroelectric capacitor of the reference cell and a first voltage source, and the preset transistor is turned on. 2. The ferroelectric memory device according to claim 1, wherein in the state, a first voltage is applied to the first electrode.