JPH09139089A - Ferroelectric substance storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a ferroelectric substance storage device in which the power consumption can be reduced and the operational speed can be increased. SOLUTION: At the time of reading operation, '0' data is written in a reference cell by holding a potential of a bit line BL of a side to which a reference cell is connected at a voltage to which power source voltage Vcc is dropped by threshold voltage of a NMOS transistors NT 1, 2 of transmission gates TMG 1, 2. Thereby, the power consumption can be reduced, and the reading operation speed can be increased.

Description

Detailed Description of the Invention

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ferroelectric memory device utilizing polarization inversion of a ferroelectric.

[0002]

2. Description of the Related Art Various ferroelectric non-volatile memories for storing binary data by utilizing polarization reversal of a ferroelectric having a hysteresis characteristic as shown in FIG. 6 are currently proposed. However, as a typical one among them, one that configures one bit by two switching transistors and two ferroelectric capacitors (2Tr-2
(Cap method)) and one switching transistor and one ferroelectric capacitor constitute one bit (1Tr-1Cap method).

In the ferroelectric non-volatile memory, when the stored data is read, the polarization state of the memory cell is changed before and after reading the data. Will need to be written again. This is because the memory cell is 1Tr
It needs to be performed regardless of the -1Cap method and the 2Tr-2Cap method. The change in the polarization state of the memory cell by reading this data will be described below with reference to FIG.

For a ferroelectric, when a voltage is applied for the first time,
Since it is not in the polarization state, the origin O starts and changes along the curve OD as the voltage increases. At the point D, the polarization is saturated, and thereafter, even if the voltage increases, the charge Q does not largely change. Next, when the voltage is reduced, the voltage does not return to the point O but passes through the point A and reaches the point B via the point P1. Thereafter, the polarization saturates similarly to the point D. When the voltage is increased from point B, C
It passes through the point, passes through the point P2, reaches the point D, and exhibits hysteresis characteristics. The data stored in the memory cell corresponds to the points A and C. Here, the point A is set to the data “1”.
Then, the point C corresponds to the data “0”. Therefore, for example, in the case of reading data "1", first, the read operation based on a predetermined bias condition changes from point A (data "1") to point P1 to point B. That is, the polarization is inverted by the read operation. For this reason, rewriting is subsequently performed based on a predetermined bias condition, and point B → point C
(Data “0”) → point P2 → point D → point A (data “1”) must be transited to restore the state before reading.

Among such ferroelectric non-volatile memories, the 2Tr-2Cap type non-volatile memory can operate at a low voltage, but in terms of high integration, 1Tr-1Ca.
A nonvolatile memory employing the p-type is suitable. next,
A basic configuration example and a specific read operation of the ferroelectric non-volatile memory adopting the 1Tr-1Cap method will be described with reference to the drawings.

FIG. 7 is a diagram showing a basic 1-bit configuration of a ferroelectric nonvolatile memory adopting the 1Tr-1Cap system. As shown in FIG. 7, the memory cell MC1 includes a switching transistor Tr1 formed of an n-channel MOS transistor having a drain connected to the bit line BL1 and a ferroelectric having one electrode connected to the source of the switching transistor Tr1. Body capacitor F
1 bit is configured by C1, the gate of the switching transistor Tr1 is connected to the word line WL1, and the other electrode (plate electrode) of the ferroelectric capacitor FC1 is connected to the plate line PL.

In the non-volatile memory adopting the 1Tr-1Cap method, the reference switching transistor RTr1 having a drain connected to the bit line BL2 paired with the bit line BL1 and the source of the switching transistor RTr1 A reference cell RMC1 constituted by a reference ferroelectric capacitor RFC1 to which an electrode of is connected is provided, the gate of the switching transistor RTr1 is connected to the reference word line RWL1, and the ferroelectric capacitor R
The other electrode of FC1 is a reference plate line RPL
It is connected to the. Note that the ferroelectric material deteriorates (Fat
igue) occurs. Therefore, the reference cell RCM1
Is controlled so that data "0" is always written and deterioration is unlikely to occur.

Next, regarding the data read operation in the non-volatile memory adopting the 1Tr-1Cap system,
This will be described with reference to the timing chart of FIG.

First, "0" V is applied to the bit lines BL1 and BL2 by a column control system (not shown), and then the bit lines BL1 and BL2 are opened. Then, (V _cc + αV, for example, α is 1 V) is applied to the word line WL1 by a row control system (not shown). As a result, the switching transistor Tr1 becomes conductive. Similarly, the word line RWL for referentless
1 is applied with (V _CC + 1V). As a result, the switching transistor RTr1 becomes conductive. In addition,
The set level of the word lines WL1 and RWL1 is set to (V _CC +1
The reason for V) is that the threshold voltage Vth of the switching transistor is 1 V or less, so that it is set to "+1 V" to prevent a voltage drop due to the transistor.

Next, the power supply voltage V _CC is applied to the plate lines PL and RPL for a predetermined time. Thereby, the potentials of bit lines BL1 and BL2 change according to the polarization state of ferroelectric capacitors FC1 and RFC2. And
Bit line BL2 to which reference cell RMC1 is connected
Bit line BL1 connected to the potential of memory cell MC1
Is detected by a sense amplifier (not shown). Note that the reference cell RMC
Since 1 is used without reversing the polarization, the reference word line RWL1 rises to 0V earlier than the reference plate line RPL so as not to enter the rewrite operation, that is, to write "0" data. Set to go down. That is, after the switching transistor RTr1 is turned off, the reference plate line RPL falls to 0V.

On the normal memory cell MC1 side, since the above-mentioned rewriting is performed after the data is read, the word line WL1 is changed from (V _CC + 1V) to 0 V after the voltage is lowered to 0 V almost at the same time as the reference plate line RPL. It can be stopped. Thereby, the switching transistor Tr
1 becomes non-conductive, and the read operation ends.

[0012]

By the way, in the circuit shown in FIG. 7, the data "1" is read from the memory cell MC1.
For reading, the level of the bit line BL1 to which the memory cell MC1 is connected is latched by a sense amplifier (not shown), and then the level of the bit line BL2 to which the reference cell RMC1 is connected becomes 0V at the power supply voltage V _CC . In this case, the bit line BL1 is charged to V _CC , and the data can be restored by rewriting the data in the memory cell MC1 using this potential. Also, the bit line BL2
Since the potential of is 0V, data "0" can be written in the reference cell RMC1 connected to this bit line BL2. Therefore, in this case, charging of the bit line BL1 is necessary for rewriting data to the memory cell MC1.

On the other hand, when reading data "0" from the memory cell MC1, the level of the bit line BL1 connected to the memory cell MC1 is latched by a sense amplifier (not shown) and then the reference cell RMC1 is connected to 0V. The level of the bit line BL2 becomes the power supply voltage V _CC . However, in this case, even if the bit line BL2 is charged to V _CC and the data “1” is rewritten in the reference cell RMC1, as described above, the data “0” is always written in the reference cell RMC1 and the memory cell Since it is used as a reference for comparison with data, "0" must be written at the next timing. Therefore, even if the bit line BL2 connected to the reference cell RMC1 is charged to V _CC, the charge is discarded as it is not used. Therefore, the amplitude of the bit line to which the reference cell RMC1 is connected does not need to be fully swung up to V _CC, and as a result, the conventional circuit consumes unnecessary power and hinders the increase in read speed. Was there.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a ferroelectric memory device capable of reducing power consumption and increasing operating speed.

[0015]

In order to achieve the above object, the present invention provides a switching transistor connected to either one of a first bit line and a second bit line, a first electrode, a second electrode and both electrodes. A ferroelectric having a ferroelectric disposed between the first electrode and the switching transistor, and storing binary data according to the polarization direction of the ferroelectric according to the voltage applied to both electrodes. A memory cell including a capacitor and a reference cell having the same configuration as the memory cell and having a switching transistor connected to a bit line different from the bit line to which the memory cell is connected are provided. A ferroelectric memory device that reads the data by detecting the potential difference between both bit lines when the transistor is conductive. During a read operation, having a bit line amplitude adjusting means inhibits to be less than the maximum amplitude corresponding to the operating voltage of the bit line amplitude at least the reference cells are connected.

Further, in the present invention, the bit line amplitude adjusting means is connected between the first and second bit lines and a means for detecting a potential difference between these bit lines, and the gate is set to a predetermined voltage during operation. It consists of a biased n-channel field effect transistor.

Further, according to the present invention, there is provided a switching transistor connected to either one of the first and second bit lines, a first and a second electrode, and a ferroelectric substance arranged between the two electrodes. A memory cell comprising a ferroelectric capacitor having a first electrode connected to the switching transistor and storing binary data depending on a polarization direction of the ferroelectric according to a voltage applied to both electrodes; And a reference cell in which the switching transistor is connected to a bit line different from the bit line to which the memory cell is connected and the switching transistor of the memory cell and the reference cell is turned on by the latch type sense amplifier. A ferroelectric memory device that reads the data by detecting the potential difference between both bit lines at a certain time. In operation out, having a bit line amplitude adjusting means inhibits so that the sense amplifier to the drive voltage supplied by lowered a predetermined potential is smaller than the maximum amplitude corresponding to the bit line amplitude to the operating voltage.

According to the ferroelectric memory device of the present invention, at the time of read operation, at least the amplitude of the bit line to which the reference cell is connected is suppressed to be smaller than the maximum amplitude corresponding to the operating voltage. As a result, unnecessary power consumption is not performed when writing reference data, for example, “0” data in the reference cell, and the reading speed can be increased.

According to the ferroelectric memory device of the present invention, the latch type sense amplifier is supplied with, for example, a voltage obtained by reducing the power supply voltage by a predetermined voltage. This allows
During the read operation, at least the amplitude of the bit line connected to the reference cell is suppressed to be smaller than the maximum amplitude corresponding to the operating voltage.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a basic 2-bit configuration of a ferroelectric non-volatile memory adopting the 1Tr-1Cap method according to the present invention. The same components as those shown in FIG. 7 are represented by the same reference numerals. That is, MC1, MC2
Is a memory cell, RMC1 and RMC2 are reference cells, BL1 and BL2 are bit lines, WL1 and WL2 are word lines, PL is a plate line, RWL1 and RWL2 are reference word lines, RPL is a reference plate line, and TMG1 and TMG2 are Transmission gate,
SA is a sense amplifier to which the bit lines BL1 and BL2 are connected via transmission gates TMG1 and TMG2, and CTL is a control circuit.

In this circuit, the memory cell MC1 and the reference cell RMC2 are connected to the bit line BL1.
The memory cell MC2 and the reference cell RMC1 are connected to the bit line BL2. Specifically, the drain of the switching transistor Tr1 of the memory cell MC1 is connected to the bit line BL1, and the drain of the switching transistor Tr2 of the memory cell MC2 is connected to the bit line BL.
2 are connected. Similarly, the reference cell RMC
The drain of the first switching transistor RTr1 is connected to the bit line BL2, and the drain of the switching transistor RTr2 of the reference cell RMC2 is connected to the bit line BL1. The gate of the switching transistor Tr1 is connected to the word line WL1,
The gate of the switching transistor Tr2 is the word line W
L2, the gate of the switching transistor RTr1 is connected to the reference word line RWL1,
The gate of the switching transistor Tr2 is connected to the reference word line RWL2.

Further, in this circuit, a divided cell plate configuration is adopted, and the plate electrode of the ferroelectric capacitor FC1 of the memory cell MC1 and the plate electrode of the ferroelectric capacitor FC2 of the memory cell MC2 share a common plate line. Connected to PL. Similarly, the reference cell R
The plate electrode of the reference ferroelectric capacitor RFC1 of MC1 and the plate electrode of the reference ferroelectric capacitor RFC2 of the reference cell RMC2 are connected to a common reference plate line RPL.

The transmission gate TMG1 is n
The source and drain of the channel MOS (NMOS) transistor NT1 and the p-channel MOS (PMOS) transistor PT1 are connected to each other, and the bit line BL
1 and one input / output terminal of the sense amplifier SA. The gate of the NMOS transistor NT1 is connected to the output line of the control circuit CTL, and the PMO
The gate of the S transistor PT1 is connected to the reference word line RWL2.

The transmission gate TMG2 is N
The source and drain of the MOS transistor NT2 and the PMOS transistor PT2 are connected to each other, and are connected between the bit line BL2 and the other input / output terminal of the sense amplifier SA. The gate of the NMOS transistor NT2 is connected to the output line of the control circuit CTL, and the gate of the PMOS transistor PT2 is connected to the reference word line RWL1.

The control circuit CTL sets its output line to a high level (V _CC level) during a read / write operation.

Next, the read operation with the above configuration will be described with reference to the timing chart of FIG.
Note that, here, a case where the storage data of the memory cell MC1 is read will be described as an example.

In the read operation, the output signal of the control circuit CTL is set to the high level of the power supply voltage V _CC level and the transmission gates TMG1 and TMG2 have N levels.
It is supplied to the gates of the MOS transistors NT1 and NT2. Therefore, the NMOS transistors NT1 and NT2
Are held in conduction. At this time, for example, the reference word lines RWL1 and RWL2 are set to the high level, and the PMOS transistors PT1 and PT2 of the transmission gates TMG1 and TMG2 are held in the non-conductive state. As a result, the levels of the bit lines BL1 and BL2 connected to the sense amplifier SA are respectively the power supply voltage V
It is held at the level Vd which is lowered from _{CC by} the threshold voltage V _thn of the NMOS transistors NT1 and NT2.

In this state, an input signal IN such as an address signal or a control signal output from a control system (not shown) is input to a pulse generating circuit (not shown), an internal signal AI is generated based on the change, and a bit (not shown) is generated. It is output to the line precharge / equalize circuit, the row control system, and the like. A voltage of 0 V is applied to all the word lines WL and the reference word line RWL at the rising timing of the internal signal AI, and the bit lines BL1 and BL1 are set by the bit line precharge / equalize circuit (not shown).
2 is precharged to 0V, for example. In this case, as shown in FIG. 2, since the potentials of the bit lines BL1 and BL2 are held at Vd instead of the full swing V _CC , it takes time T3 when the bit line level is V _CC. , T1 is shortened by T2.

A voltage of (V _CC + 1V) is applied to the reference word line RWL1 within a predetermined time (within T1) from the rise of the internal signal AI. As a result, the reference switching transistor RTr1 becomes conductive. Then, the voltage of V _CC is applied to the reference plate line PRL. As a result, "0" data is written in the reference cell RMC1. Then, after the level of the reference plate line PRL is lowered to 0V, the level of the reference word line RWL1 is lowered to 0V, and the write cycle of "0" data is completed. This reference cell RMC1
The writing of "0" data to is performed while the internal signal AI is active (high level).

Then, after the internal signal AI is switched to the low level, normal data reading from the memory cell MC1 is performed.

That is, (V _CC + 1V) is applied to the word line WL1 by a row control system (not shown). As a result, the switching transistor Tr1 becomes conductive. Similarly, (V _CC
+1 V) is applied. As a result, the switching transistor RTr1 becomes conductive. Next, the power supply voltage V _CC is applied to the plate lines PL and RPL for a predetermined time.
Thereby, the ferroelectric capacitors FC1 and RFC2
The potentials of the bit lines BL1 and BL2 change according to the polarization state of. Then, the difference between the potential of the bit line BL2 connected to the reference cell RMC1 and the potential according to the polarization state of the bit line BL1 connected to the memory cell MC1 is detected by the sense amplifier SA.

Next, after the plate line PL and the reference plate line RPL are lowered to 0V almost at the same time, the word line WL1 and the reference word line R are
WL1 is lowered from (V _CC + 1V) to 0V. At this time, on the normal memory cell MC1 side, data rewriting after data reading is performed in a row between the time when the plate line is lowered to 0V and the time when the word line is lowered to 0V.

On the side of the reference cell RMC1,
Since "0" data is always written at the start of reading and then the data read operation is started, it is not necessary to write "0" data immediately before rewriting of a normal memory cell as in the conventional case. Therefore, the fall timing of the reference word line RWL1 does not necessarily have to be performed before the fall of the plate line RPL, and it can be made to fall at the same timing as the word line WL1, which facilitates the timing design.

As described above, according to this embodiment,
During the read operation, the potentials of the bit lines BL1 and BL2, particularly the potential of the bit line BL on the side to which the reference cell is connected, are changed from the power supply voltage V _CC to the transmission gate TM.
Since the "0" data is written to the reference cell by holding it at Vd lowered by the threshold voltage V _thn of the G NMOS transistor NT, the power consumption can be reduced and the read operation speed can be increased. Can be realized. In addition, since the data read operation is performed after always writing "0" data at the start of reading, it is not necessary to write "0" data immediately before rewriting a normal memory cell as in the conventional case, and the timing can be improved. There are advantages such as easy design.

In the first embodiment, the internal signal A
Before the change of I, the reference word lines RWL1, RW
Both L2 are set to the high level, and the PMOS transistors P of the transmission gates TMG1 and TMG2 are set.
Both T1 and PT2 are held in a non-conducting state, and both bit lines B
Although the potentials of L1 and BL2 are held at Vd, the present invention is not limited to this, and only the reference word line on the reference cell side that forms a pair with the read cell is set to the high level, and the reference cell is Power consumption can be reduced even if only the potential of the connected bit line BL is held at Vd.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the ferroelectric memory device according to the present invention. The second embodiment is different from the above-described first embodiment in that the transmission gates TMG1 and TMG2 are connected to the NMOS transistors NT1 and N.
It is composed of only T2, and both bit lines BL are always in operation.
This is to keep the potentials of 1 and BL2 at Vd.

According to the second embodiment, the above-mentioned first embodiment
The same effect as that of the embodiment can be obtained.

Third Embodiment FIG. 4 is a circuit diagram showing a third embodiment of the ferroelectric memory device according to the present invention. The third embodiment is different from the above-described first embodiment in that the PMOS transistors PT1 and P of the transmission gates TMG1 and TMG2 are different.
The gate of T2 is also the output line C2, C3 of the control circuit CTL.
To the address A in the control circuit CTL.
Reference cells RMC1 and RM depending on the input of DR
Transmission gate TMG1 or TMG2 connected to bit line BL1 or BL2 to which C2 is connected
Only one of the PMOS transistors PT1 and PT2 is held in the non-conducting state, and only the bit line potential to which the reference cell is connected is dropped to Vd.

According to the second embodiment, the reference
The amplitude of the bit line to which the cell is connected is V _CCUp to full swing
Not used, but set to Vd, which is a waste like the conventional circuit
Power consumption is not performed, and read speed can be increased.
You.

Fourth Embodiment FIG. 5 is a circuit diagram for explaining a fourth embodiment of the ferroelectric memory device according to the present invention. In the fourth form,
The high-level side of the driving voltage of the sense amplifier SA is set to Vd which is lowered from V _CC . Specifically, for example, a step-down circuit 1 including an NMOS transistor whose gate voltage is held at V _CC is provided, a driving voltage of Vd (= V _CC -V _thn ) is supplied to the sense amplifier SA, and the bit line amplitude is changed. The potential Vd is lower than the power supply voltage V _CC .

According to the fourth embodiment, for example, FIG.
As shown in, the power of the sense amplifier is activated to read the signal and the bit line is latched at 0 V / V _CC . However, if the high level side at this time is Vd instead of V _CC , the read time is , T6 to T4 compared to V _CC
And is shortened by T5. Along with this, the pulse width of the plate electrode for rewriting can be made to fall faster from the broken line to the solid line side. Similarly, the access time can be shortened.

The drop potential used in each of the above-mentioned embodiments must be a potential at which the hysteresis characteristic of the ferroelectric substance is saturated.

[0043]

As described above, according to the ferroelectric memory device of the present invention, there are advantages that the power consumption can be reduced and the operation speed can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a ferroelectric memory device adopting a 1Tr-1Cap method according to the present invention.

FIG. 2 is a timing chart of potentials applied to each terminal when reading the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of a ferroelectric memory device according to the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of a ferroelectric memory device according to the present invention.

FIG. 5 is a circuit diagram for explaining a fourth embodiment of the ferroelectric memory device according to the present invention.

FIG. 6 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor.

FIG. 7 is a diagram showing a basic 1-bit configuration of a ferroelectric memory device adopting a 1Tr-1Cap system.

8 is a timing chart of a potential applied to each terminal when reading the circuit of FIG.

[Explanation of symbols]

MC1, MC2 ... Memory cells RMC1, RMC2, RMC1a, RMC2a ... Reference cells Tr1, Tr2 ... Switching transistors RTr1, RTr2 ... Reference switching transistors FC1, FC2 ... Ferroelectric capacitors RFC1, RFC2 ... Reference ferroelectric capacitors BL1, BL2 ... Bit line WL1, WL2 ... Word line RWL1, RWL2 ... Reference word line PL ... Plate line RPL ... Reference plate line CTL ... Control circuit 1 ... Step-down circuit

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[Procedure amendment]

[Submission date] February 1, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction contents]

The control circuit CTL sets its output line to a high level ( for example, V _CC level) during a read / write operation.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0027

[Correction method] Change

[Correction contents]

In the read operation, the word lines WL1,
The reference word line RWL1 is simultaneously selected,
Alternatively, the word line WL2, the reference word line R
Adopts a configuration in which WL2 are selected at the same time, the output signal of the control circuit CTL is set to c Iberu supplied to the gate of the transmission gate TMG1, TMG2 of the NMOS transistors NT1, NT2. Therefore, the NMOS transistors NT1 and NT2 are kept conductive. In this case, for example, when either one of the reference word lines RWL1, RWL2 is Ru is set to the high level, the transmission gate TMG1, TM
The G2 PMOS transistors PT1 and PT2 are held in a non-conductive state. As a result, the bit line pair BL1, BL2
, The potential of one bit line connected to the memory cell is 0
V or power supply voltage Vcc, while reference
The potential of the other bit line connected to the cell is the high level of the CTL signal.
NMOS transition from level (usually power supply voltage Vcc)
The threshold voltage V _thn of the transistor NT1 or NT2.
The level drops to Vd or 0V.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction contents]

As described above, according to this embodiment,
During the read operation, the potentials of the bit lines BL1 and BL2, particularly the potential of the bit line BL on the side to which the reference cell is connected, are changed from the power supply voltage V _CC to the transmission gate TM.
The Rukoto is held by the NMOS transistor Vd that has been lowered by the threshold voltage V _thn amount of NT of G, since to carry out the "0" data write into the reference cell, the power consumption can be reduced, the read operation speed Can be speeded up. In addition, since the data read operation is performed after always writing "0" data at the start of reading, it is not necessary to write "0" data immediately before rewriting a normal memory cell as in the conventional case, and the timing can be improved. There are advantages such as easy design.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction contents]

In the first embodiment, the internal signal A
Before the change of I, the reference word lines RWL1, RW
One of L2 becomes high level, the PMOS transistors PT1 and PT2 of the transmission gates TMG1 and TMG2 are held in the non-conducting state, and the potentials of both bit lines BL1 and BL2 are held at Vd. The present invention is not limited to this, and only the reference word line on the reference cell side that forms a pair with the read cell is set to the high level, and only the bit line BL potential to which the reference cell is connected is held at Vd. Power consumption can be reduced.

Claims (3)

[Claims] 1. A switching transistor having a switching transistor connected to either one of a first bit line and a second bit line, and a ferroelectric substance arranged between the first and second electrodes and both electrodes. A first capacitor is connected to the first electrode, and a memory cell having a ferroelectric capacitor that stores binary data according to a polarization direction of the ferroelectric substance according to a voltage applied to both electrodes and a memory cell having the same configuration as the memory cell The switching transistor has a bit line to which the memory cell is connected and a reference cell connected to a different bit line, and a potential difference between the bit line when the switching transistor of the memory cell and the reference cell is in a conductive state. A ferroelectric memory device for detecting and reading data, wherein at least a reference cell is used during a read operation. The ferroelectric memory device having a bit line amplitude adjusting means inhibits to be less than the maximum amplitude corresponding to the operating voltage of the bit line connected to the amplitude. 2. The bit line amplitude adjusting means is connected between the first and second bit lines and means for detecting a potential difference between these bit lines, and has a gate biased to a predetermined voltage during operation. 2. The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device comprises a channel field effect transistor. 3. A switching transistor having a switching transistor connected to either one of the first and second bit lines, a first and a second electrode, and a ferroelectric substance arranged between the two electrodes. A first capacitor is connected to the first electrode, and a memory cell having a ferroelectric capacitor that stores binary data according to a polarization direction of the ferroelectric substance according to a voltage applied to both electrodes and a memory cell having the same configuration as the memory cell A switching transistor having a bit line to which the memory cell is connected and a reference cell connected to a different bit line, and the switching transistor of the memory cell and the reference cell are both turned on by a latch type sense amplifier. A ferroelectric memory device that reads a data by detecting a potential difference between bit lines. The driving voltage to the sense amplifier was fed only by lowering the predetermined potential, the ferroelectric memory device having a bit line amplitude adjusting means inhibits to be less than the maximum amplitude corresponding to the bit line amplitude to the operating voltage.