KR100256253B1 - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE: A nonvolatile semiconductor memory device is provided to reduce current consumed at a sense amplifier when amplifying a small signal induced to a bit line by that a cell capacitor and a bit line capacitor hold an electric charge in common by precharging a bit line in a semiconductor device using a ferroelectric capacitor to a half of the level of a power voltage and increase amplifying function by decreasing the coupling effect by a gate capacitance of a sense amplifier. CONSTITUTION: The memory device includes a sense amplifier(S1), a memory cell(M1), a plate driver(F1), a reference voltage generating portion(R1), a half power voltage generating device and a precharging circuit(P1). The sense amplifier senses a difference of a voltage between a bit line(BL) and a bit line bar(BLB) and amplifies the difference. The memory cell, in which a switching transistor and a ferroelectric capacitor are in series connected, stores a data. The plate driver is connected to the ferroelectric capacitor and drives a plate line applying a voltage to the ferroelectric capacitor. The reference voltage generating portion generates a reference voltage necessary for sensing and amplifying. The half power voltage generating device, to which a level of a power voltage is inputted, outputs a level of a half power voltage. The precharging circuit supplies the half power voltage inputted from the half power voltage generating device to the bit line and bit line bar in response to a signal for controlling a bit line.

Description

Nonvolatile Semiconductor Memory Device.

The present invention relates to a nonvolatile semiconductor device using ferroelectric capacitor memory cells.

Fig. 1 is a diagram showing the voltage-dependent relationship between the symbols of ferroelectric capacitors and the terminals of ferroelectric capacitors a and b, showing that there is a hysteresis relationship between the voltage across the capacitor and the amount of charged charges using the ferroelectric material as a dielectric. In the ferroelectric capacitor, when the voltage at both ends is "0" V, the amount of induced charge is present in two or two states, so that data in binary form can be stored without supply of power. By utilizing these characteristics, the ferroelectric capacitor is used as a storage means of the nonvolatile memory device. In addition, the polarization state in the ferroelectric is changed according to the magnitude of the voltage applied to both ends of the ferroelectric capacitor, and the amount of charge stored in the capacitor is changed. Then, as the capacitor is switched along the hysteresis curve of FIG. 1, the polarization state changes in the 'multi' direction, and when the negative voltage is removed to make the voltage across the capacitor to "0V", it moves to the "I" state. The information stored in the ferroelectric capacitor is data by detecting the degree of change in the amount of charge induced when a voltage is applied across the capacitor. FIG. 2 shows the state of charge when the voltage across the ferroelectric capacitor is applied to -V1 and to + V1. The state of the ferroelectric is defined as "1" and is defined as "1". Assuming that time is defined as '0' and then -V1 is applied to the capacitor, the ferroelectric transitions to the 'multi' state when the initial state is 'ga' and the change in charge amount by ΔQ1 is induced and the initial state is 'b' In this case, the amount of charge change by ΔQ0 is induced as the state transitions to 'multi' state. This amount of charge is charged and shared with the bit line capacitors of the memory cell array, causing a change in the bit line precharge potential. The change in the bit line potential causes a small signal induced in the bit line to be amplified and dataized by operating a sense amplifier.

3 is a conventional circuit for reading data stored in a cell in a memory using a ferroelectric capacitor, and includes a sense amplifier S1 and a switching transistor for sensing and amplifying a minute voltage difference between a bit line BL and a bit line bar BLB. A memory cell (M1) that stores one data and one ferroelectric capacitor, a reference voltage generator (R1) for generating a reference voltage for sense amplification, and a bit line (BL) and a bit line bar (BLB) ground level It consists of a precharge circuit P1 which precharges to low. The source of the switching transistor of the memory cell M1 is connected to the bit line, the gate of the switching transistor is connected to the word line, one side of the ferroelectric capacitor electrode is connected to the drain of the switching transistor, and the other is a plate for driving the ferroelectric capacitor. Connected by a line. The precharge circuit P1 is formed in series between the bit line BL and the bit line bar BLB, and consists of two enMOS transistors receiving the bit line precharge signal BLP as a gate input. The ground level is applied to the source of.

In the standby state, the bit line precharge signal BLP remains high to precharge the bit line BL and the bit line bar BLB to the ground level, and the bit line precharge signal BLP to read data stored in the cell. ) Becomes low to make the bit line floating. When the word line signal WL0 becomes high and the plate signal CP becomes high, the state of the ferroelectric capacitor CS shifts to the "multi" state and the amount of charge of ΔQ1 or ΔQ0 This bit line voltage is induced and the induced voltage is amplified by the sense amplifier S1. The reference voltage of the sense amplifier is generated from the reference ferroelectric capacitor CR by setting the reference word line RWL0 and the reference plate signal RCP of the reference voltage generator R1 high.

FIG. 4 is a circuit diagram of another conventional embodiment for reading data stored in a cell in a memory using a ferroelectric capacitor, and includes the sense amplifier S1, the memory cell M1, the reference voltage generator R1, and a bit. Two NMOS transistors that receive a bit line low precharge signal BLP and a bit line high precharge signal BHP as inputs of each gate in parallel between the line BL and the bit line bar BLB, and are connected in series with each other; It consists of two PMOS transistors. The ground level is applied to two NMOS transistor sources connected in series while receiving a bit line low precharge signal (BLP) as a gate input, and two PMOS transistor sources connected in series while receiving a bit line high precharge signal (BHP) as a gate input. The power supply voltage level is configured to be applied. The bit line BL is precharged to the ground level by turning the bit line low precharge signal BLP and the bit line high precharge signal BHP high in the standby state, and the bit line low precharge signal BLP in order to read data stored in the cell. ) And the bit line high precharge signal BHP low to precharge to the power supply voltage level. After precharging, the bit line high precharge signal BHP goes high to make the bit line BL floating, and the word line signal WL0 to high to make the ferroelectric capacitor CS a 'la' state. The amount of charge in ΔQ1 or ΔQ0 is induced to induce a change in the bit line potential. The potential induced in the bit line is amplified by operating the sense amplifier.

When precharging the bit line and the bit line bar to the ground level or the power supply voltage level in the precharge circuit as described above, the potential induced at the ground voltage level is grounded to the power supply voltage level or the power supply voltage level is grounded. Since it must be amplified to the voltage level, there is a problem that the current consumption increases during amplification. In addition, due to the influence of the coupling due to the gate capacitance of the sense amplifier transistor, the difference in voltage induced in the bit line and the bit line bar during amplification is reduced, resulting in a decrease in the amplification path.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In a semiconductor device using a ferroelectric capacitor, the bit line is precharged to a 1/2 power supply voltage level, and thus the charge is induced in the bit line by charge sharing between the cell capacitor and the bit line capacitor. The purpose of the present invention is to provide a nonvolatile semiconductor device which reduces the current consumed by the sense amplifier when amplifying the small signal, and improves the amplification capability by reducing the coupling effect of the sense amplifier's gator capacitance.

1 is a relation according to the voltage between the symbol of the ferroelectric capacitor and the terminals of the ferroelectric capacitor,

2 is a state of charge when the voltage across the ferroelectric capacitor is applied to -V1 and + V1,

3 is a conventional circuit for a read operation in a memory using a ferroelectric capacitor,

Figure 4 is another conventional embodiment circuit for a read operation in a memory using a ferroelectric capacitor,

5 is a circuit of the present invention for a read operation in a memory using a ferroelectric capacitor,

6 is a signal diagram for the read operation of FIG.

7A and 7B show a leakage current model from the storage node to the substrate,

8A is an embodiment for preventing potential reduction of a storage node;

FIG. 8B is a signal diagram of FIG. 8A;

9 is another embodiment for preventing potential reduction of a storage node;

Figure 10 is another embodiment of the present invention for a read operation in a memory using a ferroelectric capacitor.

The present invention for achieving the above object is a sense amplifier for sensing and amplifying the voltage difference between the bit line and the bit line bar, the switching transistor and the ferroelectric capacitor is connected in series with a memory cell for storing data, connected to the ferroelectric capacitor of the memory cell And a plate driver for driving a plate line for applying a voltage to the ferroelectric capacitor, and a reference voltage generating means for generating a reference voltage for sense amplification. A 1/2 power supply voltage generator for outputting a 2 power supply voltage level; And a precharge circuit configured to supply a 1/2 power voltage output from the 1/2 power voltage generator to a bit line and a bit line bar in response to a bit line control signal. It is done by

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a circuit of the present invention for reading data stored in a cell in a memory using a ferroelectric capacitor, and includes a sense amplifier S1 for sensing and amplifying a minute voltage difference between a bit line BL and a bit line bar BLB, and switching. A memory cell (M1) for storing data, a plate driver (F1) for driving a plate line, a reference voltage generator (R1) for generating a reference voltage for sensing amplification, and a memory cell (M1) including one transistor and one ferroelectric capacitor; It consists of a precharge circuit P1 which precharges the bit line BL and the bit line bar BLB to a 1/2 power supply voltage level. The precharge circuit P1 is formed in series between the bit line BL and the bit line bar BLB, and consists of two enMOS transistors receiving the bit line precharge signal BLP as a gate input. The power source is configured to apply a 1/2 power supply voltage level. FIG. 6 is a signal diagram for operating the circuit of FIG. 5, and the operation of FIG. 5 will be described with reference to FIG. In the standby state, the bit line precharge signal BLP of the precharge circuit P1 becomes high so that two NMOS transistors N1 and N2 turn on to precharge the bit line to 1/2 the supply voltage level. (Plate) is also maintained at 1/2 power supply voltage level. After the cell is read in the previous cycle, the word line WL0 is closed, and if the SN node is 1/2 of the supply voltage in the current cycle, the voltage difference across the ferroelectric capacitor is 0V, so it is present in the "ga" or "b" state of FIG. It is a state. The row address signal is input to read the cell stored outside the chip so that the word line is selected by the row decoder. The bit line BL is kept at 1/2 power supply voltage level before the word line is selected. Only in the floating state can the amount of charge stored in the cell be detected. To do this, the bit line precharge signal BLP must be low. After the bit line precharge signal BLP becomes low and the transistors N1 and N2 are turned off, the word line corresponding to the input row address is selected to bootstrap the word line voltage to the 3/2 power voltage level. When the word line is selected, the switching transistor of the memory cell is turned on, and when the plate line is driven, the amount of charge stored in the cell is loaded on the bit line BL. If the information stored in the C1 ferroelectric capacitor is read, the word line WL0 should be selected. In order to read the information stored in the C2 ferroelectric capacitor, the word line WL1 should be selected. When WL0 is selected, the switching transistor ST1 is turned on. When WL1 is selected, the switching transistor ST2 is turned on. At the same time when the word line is bootstrap, the plate line Plate is also driven from the plate driver F1 to the 3/2 power supply voltage level so that the charge and the bit line capacitor stored in the selected cell capacitor are charged and changed to change the bit line potential. At this time, the reference voltage generator R1 is also driven in the above manner to generate a reference voltage for changing the bit line potential. If the word line WL0 is selected by the address, the reference word line RWL0 of the reference voltage generator R1 is selected and is sensed by the sense amplifier S1 connected to the bit line BL and the bit line bar BLB. Make comparisons possible. The bit line potential developed by the reference voltage generation unit R1 becomes a middle of the bit line potential developed when '1' and '0' of the memory cell are stored to be detectable. After the plate line is driven and the development of the bit line potential is completed, the sense amplifier S1 connected to the bit line BL and the bit line bar BLB is operated to amplify the developed potential to make binary data. Send to output

Meanwhile, FIG. 7A illustrates a single switching transistor ST1 and one ferroelectric capacitor C1 from the memory cell M1 of FIG. 5. When the plate voltage driven from the plate driver F1 in the standby state is maintained at the 1/2 supply voltage level, the opposite SN node must also be maintained at the 1/2 supply voltage level. The ferroelectric capacitor C1 is shown in FIG. You can wait in the 'I' or 'I' state. After the read operation is completed, if the bit line precharge signal (BLP) is kept high and the potential of the bit line is maintained at the power supply level of 1/2, then the word line is turned off, the SN node is 1/2 even after the word line is closed. Maintain power supply voltage level. However, as shown in FIG. 7B, leakage current flows from the SN node to the substrate, thereby decreasing the potential of the SN node, and the ferroelectric capacitor C1 does not maintain the 'ga' or 'me' state in the standby state. To the side. In order to prevent such leakage current, a word line decoder D1 for receiving the first control signal REF, decoding the word line, and turning on the word line at a predetermined period is further configured as shown in FIG. 8A. As shown in the signal diagram of Fig. 8B, since the REF signal is generated at regular intervals in the standby state, the word lines of the cells are sequentially turned on, so that the bit lines are precharged to the 1/2 supply voltage level. 2 Make it possible to maintain the power supply voltage level. FIG. 9 illustrates another embodiment of preventing leakage current of an SN node, and receiving a second control signal SND at each SN node as a gate input, and an NMOS transistor N1 having a source connected to a half supply voltage. In the standby state, the SND signal goes high and is precharged to the 1/2 power supply voltage level, while it goes low during the read operation, so that potential reduction due to leakage current does not occur in the standby state.

As another embodiment of the present invention, it may be configured and operated as shown in FIG. FIG. 10 illustrates an output of the first block and the sense amplifier S1 for selectively transferring the reference voltage output from the reference voltage generator R1 to the bit line BL and the bit line bar BLB in the embodiment of the present invention. Receive a second block to send to the output stage is configured. The reference voltage generated by the reference voltage generator R1 is selectively transferred to the bit line BL and the bit line bar BLB by the third control signal RV0 and the fourth control signal RV1 in the first block. . If the information stored in the ferroelectric capacitor C1 is read, the RV0 signal is made high and the reference voltage is transmitted to the bit line bar BLB. If the information stored in the ferroelectric capacitor C2 is read, the RV1 signal is made high to bit the reference voltage. Pass on line BL.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention made as described above, the semiconductor device using the ferroelectric capacitor is precharged to the 1/2 power supply voltage level, thereby reducing the current consumed by the sense amplifier and improving the amplification capability of the sense amplifier.

Claims (4)

A sense amplifier that senses and amplifies the voltage difference between the bit line and the bit line bar, a switching cell and a ferroelectric capacitor connected in series to store data, and connected to a ferroelectric capacitor of the memory cell to apply voltage to the ferroelectric capacitor A nonvolatile semiconductor memory device comprising a plate driver for driving a plate line and a reference voltage generating means for generating a reference voltage for sensing amplification. A half power supply voltage generator for inputting a power supply voltage level and outputting a half power supply voltage level; And And a precharge circuit for supplying a 1/2 power voltage output from the 1/2 power voltage generator to a bit line and a bit line bar in response to a bit line control signal. The method of claim 1, Word line decoding means for receiving the first control signal and decoding the word line to turn on the word line at a predetermined period to prevent the potential of the storage node between the series-connected switching transistor and the ferroelectric capacitor from being reduced due to leakage current in a standby state. Non-volatile semiconductor memory device further comprises. The method of claim 1, A drain is connected to the storage node, a source is connected to a 1/2 power supply voltage, and a second control to prevent a potential decrease of the storage node between the series-connected switching transistor and the ferroelectric capacitor due to leakage current in a standby state. A nonvolatile semiconductor memory device comprising transistor means for receiving a signal as an input of a gate. The method of claim 1, And a first block for selectively transferring the reference voltage output from the reference voltage generating means to the bit line and the bit line bar, and a second block receiving the output of the sensing amplifier and outputting the output to the output terminal.

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