KR20130022540A - Data read circuit, nonvolatile memory device having the same and method for reading data of nonvolatile memory device - Google Patents

Data read circuit, nonvolatile memory device having the same and method for reading data of nonvolatile memory device Download PDF

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KR20130022540A
KR20130022540A KR1020110085146A KR20110085146A KR20130022540A KR 20130022540 A KR20130022540 A KR 20130022540A KR 1020110085146 A KR1020110085146 A KR 1020110085146A KR 20110085146 A KR20110085146 A KR 20110085146A KR 20130022540 A KR20130022540 A KR 20130022540A
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South Korea
Prior art keywords
sense amplifier
data
differential output
voltage
voltages
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KR1020110085146A
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Korean (ko)
Inventor
김찬경
황홍선
박철우
강상범
오형록
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삼성전자주식회사
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Priority to KR1020110085146A priority Critical patent/KR20130022540A/en
Priority claimed from US13/562,871 external-priority patent/US9042152B2/en
Priority claimed from DE102012107639A external-priority patent/DE102012107639A1/en
Publication of KR20130022540A publication Critical patent/KR20130022540A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1673Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1697Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • G11C11/2273Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225Auxiliary circuits
    • G11C11/2297Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0038Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits

Abstract

Disclosed are a data read circuit performing a data read operation using a plurality of reference voltages, a nonvolatile memory device including the same, and a data read method of a nonvolatile memory device. According to an embodiment of the present invention, a nonvolatile memory device includes a cell array including a nonvolatile memory cell, a bit line connected to the nonvolatile memory cell, and a data line to transfer a data voltage to the nonvolatile memory cell. And a sense amplifier circuit configured to receive at least two reference voltages through a second input unit, and differentially amplify input signals provided to the first and second input units during data read operation to generate read data. It is done.

Description

Data read circuit, nonvolatile memory device having same and data read method of nonvolatile memory device {Data read circuit, Nonvolatile memory device having the same and Method for reading data of nonvolatile memory device}
The present invention relates to a data read circuit, and more particularly, to a data read circuit performing a data read operation using a plurality of reference voltages, a nonvolatile memory device including the same, and a data read method of a nonvolatile memory device.
As a device for storing information, a semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device. The nonvolatile memory device may be a random change memory (RRAM) using a variable resistance characteristic material such as a phase change random access memory (PRAM), a complex metal oxide (Complex Metal Oxides), or a magnetic random access (MRAM) using a ferromagnetic material. Memory), a memory device such as a ferroelectric random access memory (FRAM) using a strong dielectric capacitor, and the like.
In the field of semiconductor memory devices, various researches have been attempted to improve performance, such as increasing integration, increasing operating speed, and securing data reliability. However, there is a problem of deterioration of performance due to various factors such as process variation of the semiconductor memory device or signal variation provided to various circuits for operating the semiconductor memory device (for example, a circuit for writing or reading data). May occur. There is a need for a design of a semiconductor memory device that can prevent performance degradation due to such various factors.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems. It is an object to provide a data read method.
In order to achieve the above object, a nonvolatile memory device according to an embodiment of the present invention, a cell array including a nonvolatile memory cell, a bit line connected to the nonvolatile memory cell to transfer a data voltage and Receives the data voltage through a first input unit, receives at least two reference voltages through a second input unit, and generates read data by differentially amplifying input signals provided to the first and second input units during a data read operation. And a sense amplifier circuit.
Meanwhile, the data read circuit according to an embodiment of the present invention includes a first input unit for receiving a data voltage from a nonvolatile memory cell and a second input unit for receiving first and second reference voltages. And a first sense amplifier configured to differentially amplify input signals provided to the second input unit to generate a differential output signal, and a second sense amplifier to sense and amplify the differential output signal to generate an amplified signal.
On the other hand, a nonvolatile memory device according to another embodiment of the present invention, a cell array including a plurality of memory cells and first and second reference cells for storing data of the first and second states, respectively, A first bit line connected to each of the memory cells, second and third bit lines connected to the first and second reference cells, and a plurality of sense amplifier circuits disposed corresponding to the plurality of memory cells, respectively. The sense amplifier circuit may receive a data voltage through the first bit line, receive first and second reference voltages through the second and third bit lines, and use the first and second reference voltages. And a sense amplifier circuit block for sensing and amplifying the data voltage.
The data read method of the nonvolatile memory device according to an embodiment of the present invention includes precharging a differential output terminal of a first sense amplifier, and converting a data voltage, a first and a second reference voltage into the first sense amplifier. Providing a differential output signal by performing a differential amplification operation using the data voltage and the first and second reference voltages, enabling a second sense amplifier after a predetermined delay time, and And generating read data by sensing and amplifying the differential output signal in a second sense amplifier.
According to the data read circuit of the present invention as described above, the nonvolatile memory device including the same, and the data read method of the nonvolatile memory device, the reliability of the read data in spite of various variations that may occur in the nonvolatile memory device. There is an effect to improve.
In addition, according to the data read circuit of the present invention, a nonvolatile memory device including the same, and a data read method of the nonvolatile memory device, an access time of stored data can be reduced, thereby storing a large amount of information in the nonvolatile memory device. In addition to the purpose, the memory device may be used for a memory that requires fast access, and an increase in access time may be prevented even when memory cells connected to one bit line are increased.
1 is a block diagram illustrating a memory system according to an example embodiment.
2A, 2B and 2C are block diagrams and circuit diagrams illustrating an example embodiment of the nonvolatile memory device of FIG. 1.
3 is a circuit diagram illustrating an embodiment of a data read circuit included in the nonvolatile memory device of the present invention.
4 is a block diagram illustrating another implementation of an MRAM device as an example of a nonvolatile memory device.
FIG. 5 is a circuit diagram illustrating an example embodiment of a data read circuit of the nonvolatile memory device of FIG. 4.
6 is a block diagram illustrating an embodiment of a sense amplifier circuit included in a data read circuit according to an embodiment of the present invention.
7 and 8 are circuit diagrams illustrating an embodiment of the sense amplifier circuit of FIG. 6.
9 and 10 are graphs showing examples of input and output waveforms of the sense amplifier circuit of FIG. 6.
FIG. 11A is a graph showing a comparison of a data signal waveform of a conventional data read circuit with a data signal waveform of a data read circuit in an embodiment of the present invention.
FIG. 11B is a graph illustrating an access time compared to a conventional case and a read operation according to an exemplary embodiment of the present invention. FIG.
12 and 13 are flowcharts illustrating a data reading method of a nonvolatile memory device according to an embodiment of the present invention.
14 is a circuit diagram illustrating an implementation of a data read circuit according to another embodiment of the present invention.
15 is a block diagram illustrating an implementation of a data read circuit according to another embodiment of the present invention.
16 and 17 are block diagrams illustrating an example of a layout of a nonvolatile memory device according to an embodiment of the present invention.
18 is a circuit diagram illustrating an example of a data read circuit of a nonvolatile memory device according to another exemplary embodiment of the present invention.
19 is a block diagram illustrating an application example of an electronic system having a nonvolatile memory device according to an embodiment of the present invention.
20 is a block diagram showing an application example of a single chip microcomputer having a nonvolatile memory device of the present invention.
21 is a block diagram illustrating an example of an information processing system equipped with a nonvolatile memory device according to the present invention.
In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.
The nonvolatile memory device may include a memory such as a phase change random access memory (PRAM), a reactive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), and the like. Nonvolatile memory devices such as PRAM, RRAM, and MRAM described above are all memory having low cost of DRAM, high capacity, operating speed of SRAM, and nonvolatile characteristics of flash memory. For example, as a kind of MRAM, the read access time of STT (STT Torque Transfer) -MRAM has recently been reduced to within 10 ns.
In order to improve performance, overcoming variations caused by various factors in memory has been raised as an issue. The nonvolatile memory device includes a read circuit for reading data of a memory cell, and the read circuit includes a sense amplifier for comparing the developer voltage of the memory cell with a reference voltage. In nonvolatile memory devices such as MRAM, PRAM, and RRAM, deviations in cell resistance values, bias current values of current sources, and bit line resistance components may occur, and are applied externally. Since the reference voltage is also transmitted globally throughout the memory area, deviations may occur. Since a problem of deterioration due to such a deviation may occur, it is necessary to design a semiconductor memory device capable of preventing performance deterioration due to such various factors.
1 is a block diagram illustrating a memory system according to an example embodiment. As illustrated in FIG. 1, the memory system 1000 may include a nonvolatile memory device 1100 and a controller 1200. The nonvolatile memory device 1100 may include a memory cell array including a plurality of nonvolatile memory cells, and a peripheral circuit for performing a read / write operation of the memory cell array. The controller 1200 generates a command / address CMD / ADD to control the nonvolatile memory device 1100, and also provides write data DATA to the nonvolatile memory device 1100 or read data DATA. ) Is received from the nonvolatile memory device 1100.
The controller 1200 may include a host interface 1210 for interfacing with the host HOST and a memory interface 1230 for interfacing with the nonvolatile memory device 1100. In addition, the controller 1200 may further include a control logic 1220 for controlling the overall operation of the controller 1200. For example, the control logic 1220 may transmit various control signals for read / write of the nonvolatile memory device 1100 through the memory interface unit 1230 according to a command input from the host HOST. ) RAM may be disposed inside the control logic 1220 or outside of the control logic 1220. The RAM may be temporarily stored in the RAM during the data write operation, or the read data may be RAM during the data read operation. (RAM) can be temporarily stored.
The names of the above configurations are one example that can be applied to the present invention. The nonvolatile memory device 1100 and the controller 1200 may be implemented as separate semiconductor chips, or may be implemented as separate semiconductor packages. Can be implemented. In addition, the nonvolatile memory device 1100 and the controller 1200 may be integrated on the same chip or in a single semiconductor package. In this case, the nonvolatile memory device 1100 may be a memory system and a memory device. It may be defined as including a controller. In addition, the memory system including the nonvolatile memory device 1100 and the controller 1200 may be implemented as a memory card such as an SD and an MMC.
2A, 2B and 2C are block diagrams and circuit diagrams illustrating an example embodiment of the nonvolatile memory device of FIG. 1. FIG. 2A is a block diagram illustrating an implementation of an MRAM device as an example of a nonvolatile memory device 1100, FIG. 2B is a circuit diagram illustrating a unit cell of FIG. 2A, and FIG. 2C is a MTJ (Magnetic) of the unit cell of FIG. 2B. Tunnel Junction).
An operation of the nonvolatile memory device 1100 will now be described with reference to FIGS. 2A, 2B and 2C. As shown in FIG. 2A, the nonvolatile memory device 1100 may include a cell array 1110 including a plurality of memory cells, a row decoder 1120 for selecting a word line of the cell array 1110, and a cell array. A column decoder 1130 for selecting a bit line of 1110, a precharge circuit unit 1140 that performs a precharge operation on the bit line, and a sense amplifier circuit block that senses / amplifies data of a bit line of a memory cell. 1150 may be provided. In addition, the nonvolatile memory device 1100 may include a current generator 1160 for generating a current supplied to a word line and / or a bit line, and a reference voltage for generating various reference voltages VREFL and VREFH for data sensing. The generators 1171 and 1172 may be provided. In FIG. 2A, as an example, a first reference voltage generator 1171 for generating a reference voltage VREFH having a high level, and a second reference voltage generator for generating a reference voltage VREFL having a low level ( 1172 is shown.
The cell array 1110 includes a plurality of memory cells (MRAM cells) 1111 formed at intersection points of word lines and bit lines. The memory cell 1111 may include one cell transistor CT and one MTJ. Although not shown in FIG. 2A, in the data write operation, the non-volatile memory device 1100 may further include digit lines and a digit line decoder for changing the direction of the magnetic field formed in the MTJ.
Meanwhile, the row decoder 1120 and the column decoder 1130 each include a plurality of switches based on MOS transistors, and the row decoder 1120 selects the word lines WL in response to the row address, and the column decoder 1 1130 selects the bit lines BL in response to the column address (not shown). The precharge circuit unit 1140 precharges the bit lines BL to a predetermined precharge level, and when the data is read, the voltages of the bit lines BL are developed according to the data value stored in the memory cell 1111. do. The sense amplifier circuit block 1150 includes a plurality of sense amplifier circuits corresponding to the bit lines BL, and senses and amplifies voltages of the developed bit lines BL.
In addition, the current generated by the current generator 1160 is provided to the bit lines BL as a constant value. The voltage levels of the bit lines BL may have a level based on a current value generated by the current generator 1160 and a data value stored in the memory cell 1111. For example, the MTJ of the memory cell 1111 has a relatively large resistance value or a small resistance value according to the written data value, and voltages having different levels according to the variation of the resistance value have bit lines BL. Are provided to the sense amplifier circuit block 1150 as a data voltage.
Meanwhile, according to an embodiment of the present invention, at least two reference voltages VREFL and VREFH are provided to the sense amplifier circuit block 1150. In FIG. 2A, the first and second reference voltages VREFL and VREFH are respectively generated by the first and second reference voltage generators 1171 and 1172 in the nonvolatile memory device 1100, respectively. The second reference voltages VREFL and VREFH may be generated by the controller 1200 and provided to the nonvolatile memory device 1100. The sense amplifier circuit block 1150 includes a plurality of sense amplifier circuits (not shown) corresponding to the bit lines BL, and each sense amplifier circuit includes a data voltage and first and second reference voltages VREFL and VREFH. ) Is received through the input terminal.
In addition, the sense amplifier circuit generates a differential output signal that is enveloped according to a voltage level difference between the data voltage and the first and second reference voltages VREFL and VREFH. That is, the differential output signal is generated by differentially amplifying the data voltage input as a single signal. In addition, the differential output signal may be generated by a capacitor (not shown) for storing a voltage corresponding to a level difference between the data voltage and the first and second reference voltages VREFL and VREFH, and thus the sense The amplifier circuit may include an integration circuit that accumulates a voltage using a predetermined capacitor. In addition, the read data is generated by sensing / amplifying the differential output signal at a predetermined time point. The detailed operation of the sense amplifier circuit block 1150 as described above will be described later.
FIG. 2B is a circuit diagram illustrating a unit cell of FIG. 2A, and as illustrated in FIG. 2B, the memory cell 1111 may include a magnetic tunnel junction (MTJ) and a cell transistor CT. The gate of the cell transistor CT is connected to the word line (eg, the first word line WL0), and one electrode of the cell transistor CT is connected to the bit line (eg, the first bitline BL0) through the MTJ. In addition, the other electrode of the cell transistor CT is connected to a source line (eg, the first source line SL0). Current for writing data may be transferred from the bit line to the source line direction or from the source line to the bit line direction. The direction of the vector formed in the MTJ is determined according to the direction in which the current is transmitted, and the resistance values formed in the MTJ according to the direction of the determined vector during the read operation have different values.
FIG. 2C is a cross-sectional view illustrating an example of a structure of a magnetic tunnel junction (MTJ) of the memory cell of FIG. 2B. As illustrated in FIG. And a tunnel layer 1111_3 disposed therebetween. In addition, the first electrode E1 in contact with the pinned layer 1111_1 and the second electrode E2 in contact with the free layer 1111_2 may be further provided. Although not shown in FIG. 2C, an anti-ferromagnetic layer (not shown) may be further provided between the first electrode E1 and the pinned layer 1111_1 to fix the magnetization direction of the pinned layer 1111_1. Can be.
The magnetization direction of the pinned layer 1111_1 is fixed, and the magnetization direction of the free layer 1111_2 may have the same magnetization direction as that of the pinned layer 1111_1 or may have an opposite direction. The write currents WC1 and WC2 may be applied between the first electrode E1 and the second electrode E2, and the magnetization direction of the free layer 1111_2 is determined according to the directions of the write currents WC1 and WC2. do. For example, when the write current WC1 is applied from the second electrode E2 to the first electrode E1, the free layer 1111_2 may be magnetized in the same magnetization direction as the pinned layer 1111_1.
The resistance value of the MTJ has a different value depending on the magnetization direction of the free layer 1111_2. For example, when the magnetization direction of the free layer 1111_2 is the same as the magnetization direction of the pinned layer 1111_1, the resistance value of the MTJ has a low value, which may correspond to storing data '0'. On the other hand, when the magnetization direction of the free layer 1111_2 has a direction opposite to the magnetization direction of the pinned layer 1111_1, the resistance value of the MTJ has a high value, which may correspond to storing data '1'.
3 is a circuit diagram illustrating an embodiment of a data read circuit included in the nonvolatile memory device of the present invention. The data read circuit may be defined as a concept including circuits disposed on a read path and involved in a read operation of data. The data read circuit 1300 may further include at least some of various components shown in FIG. 2A or other components not shown in FIG. 2A. 3 illustrates a data read circuit 1300 for reading data of any one memory cell 1111, a plurality of data read circuits for reading data of a plurality of memory cells in parallel are non-volatile memory. It may be provided in the device 1100.
A detailed configuration and operation of the data read circuit 1300 will be described with reference to FIGS. 1 and 3 as follows.
As shown in FIG. 3, the data read circuit 1300 is connected to a bit line, and a precharge circuit 1141 for precharging the bit line to a predetermined level, and a bit line selection circuit 1131 for selecting the bit line. ), A clamping circuit 1191 for clamping the bit line, a current source 1161 providing current to the bit line, a data voltage VSA and at least two reference voltages VREFH and VREFL and performing sensing / amplifying operations. It may include a sense amplifier circuit 1151 to perform. In addition, the resistor Rb1 shown in FIG. 3 represents a resistance component due to the bit line itself, and the output VOUT of the sense amplifier circuit 1151 is latched by a predetermined latch circuit (not shown) to be external as read data. It may be provided as.
Meanwhile, the precharge circuit 1141 may be disposed corresponding to each of the bit lines, and may be included in the precharge circuit unit 1140 of FIG. 2A. In addition, the bit line selection circuit 1131 is a circuit in which on / off is controlled in response to the decoding result of the column address, and may be included in the column decoder 1130 of FIG. 2A. Similarly, the clamping circuit 1191 may also be disposed corresponding to each of the bit lines, and the sense amplifier circuit 1151 is for sensing and amplifying the data voltage VSA of each of the bit lines. It may be included in block 1150.
The current source 1161 may be configured to be included in the current generator 1160 of FIG. 2A, or the current generated by the current generator 1160 may be commonly provided to a plurality of bit lines. In addition, although not shown in FIG. 3, an additional precharge circuit (not shown) for providing a predetermined level of voltage to a node between the memory cell 1111 and the bit line selection circuit 1131 is provided with a data read circuit 1300. It may be further provided to). Based on the operation of the additional precharge circuit (not shown), the provision of the predetermined level of voltage may be maintained at an unselected bit line, and the provision of the predetermined level of voltage may be blocked at the selected bit line.
According to an embodiment of the present invention, the nonvolatile memory device 1100 performs a sensing / amplifying operation using at least two reference voltages VREFH and VREFL when reading the data voltage VSA. In addition, an integration operation is performed according to a voltage level difference between the data voltage VSA and at least two reference voltages VREFH and VREFL, and differentially amplifies one data voltage VSA based on the integration operation. Generate a differential output signal (not shown). In addition, the output VOUT is generated by performing a sensing / amplification operation on the differential output signal. To this end, the sense amplifier circuit 1151 may sense a first sense amplifier for generating a differential output signal in response to a data voltage VSA and a second sense amplifier for sensing / amplifying the differential output signal to generate the output VOUT. (Above, not shown) may be included. In addition, the first sense amplifier may be implemented as an integrating circuit for performing differential amplification of input signals including a data voltage VSA and at least two reference voltages VREFH and VREFL.
A detailed operation of the data read circuit 1300 illustrated in FIG. 3 is as follows. The at least two reference voltages VREFH and VREFL are assumed to be first and second reference voltages VREFH and VREFL.
The bit line connected to the memory cell 1111 is precharged to a predetermined level, and then the bit line selection circuit 1131 is selected to read data of the memory cell 1111. The gate of the clamping circuit 1191 is provided with a constant voltage, and the current source 1161 also provides a current having a constant level to the first input terminal of the sense amplifier circuit 1151 (the input terminal receiving the data voltage VSA). do. The MTJ of the memory cell 1111 has a different resistance value according to the stored data, and the data voltage VSA of the first input terminal of the sense amplifier circuit 1151 is developed according to the resistance value of the MTJ.
The second and third input terminals of the sense amplifier circuit 1151 receive the first and second reference voltages VREFH and VREFL, respectively. As described above, the first and second reference voltages VREFH and VREFL may be generated in the nonvolatile memory device 1100 using a predetermined power supply voltage from an external source, or the first and second reference voltages. (VREFH, VREFL) can be provided directly from the outside.
In the sense amplifier circuit 1151, the data voltage VSA level is compared with the levels of the first and second reference voltages VREFH and VREFL, respectively, and generates a differential output signal by performing an integration operation according to the voltage level difference. Let's do it. In addition, the output VOUT is generated by sensing and amplifying the differential output signal at a specific time while the differential output signal is generated. The first and second reference voltages VREFH and VREFL may have a constant voltage level, and as the data voltage VSA is enveloped, between the data voltage VSA and the first and second reference voltages VREFH and VREFL. The difference in the voltage levels occurs.
FIG. 4 is a block diagram illustrating another implementation of an MRAM device as an example of a nonvolatile memory device, and FIG. 5 is a circuit diagram illustrating an embodiment of a data read circuit of the nonvolatile memory device of FIG. 4. In describing the structure and operation of the nonvolatile memory device of FIGS. 4 and 5, detailed descriptions of the same elements as those illustrated in FIGS. 2A, 2B and 3C will be omitted.
As shown in FIG. 4, the nonvolatile memory device 1100 includes a cell array 1110 for storing data, a row decoder 1120 for selecting a word line, and a column decoder 1130 for selecting a bit line. It includes. In addition, the nonvolatile memory device 1100 may include a precharge circuit 1140 for precharging a bit line to a predetermined level, a sense amplifier circuit block 1150 for sensing / amplifying data of a bit line of a memory cell, and a word. A current generator 1160 for generating a current supplied to the line and / or bit line is further provided. The cell array 1110 includes a plurality of memory cells (eg, MRAM cells 1111) that store data.
The nonvolatile memory device 1100 illustrated in FIG. 4 generates reference voltages (eg, first and second reference voltages VREFH and VREFL) from an MRAM cell for reading data. To this end, the nonvolatile memory device 1100 further includes a reference cell array 1180, and the reference cell array 1180 may include a plurality of reference cells that provide first and second reference voltages VREFH and VREFL. reference cell). The memory cell 1111 of the cell array 1110 storing data and the reference cell of the reference cell array 1180 may have the same cell structure.
Data corresponding to logic high or logic low may be stored in the reference cells 1181 and 1182 of the reference cell array 1180. For example, data of logic high is written in some cells (first cell, 1181) of the reference cell array 1180, and data of logic low is written in the remaining cells (second cell, 1182). The reference cell array 1180 may include a first reference cell 1181 and a second reference cell 1182 corresponding to at least some of the word lines, or the first reference cell 1181 for each of all word lines. ) And a second reference cell 1182 may be disposed. Accordingly, in the read operation of the cell array 1110, information recorded in the first and second reference cells 1181 and 1182 of the reference cell array 1180 is read together.
The write operation on the reference cells 1181 and 1182 may be performed together with the write operation on the memory cell 1111. The write operation for the reference cells 1181 and 1182 may be performed once for the first time, and the first and second reference voltages VREFH, may be repeated by repeatedly reading the reference cells 1181 and 1182 for which the write operation is performed once. VREFL) can be obtained. In addition, the reference cells 1181 and 1182 are selected together when the word line of the cell array 1110 is selected, and the reference cells 1181 and 1182 may be written together during the write operation on the corresponding word line of the cell array 1110. Can be. That is, each time data is updated, the write operation for the reference cells 1181 and 1182 may be repeatedly performed. In addition, when a memory such as an MRAM is applied, the data value (for example, the resistance value of the MTJ) stored in the memory cell 1111 or the reference cells 1181 and 1182 may fluctuate with time. Accordingly, an operation of re-writing data may be performed with respect to the memory cell 1111 according to a predetermined time period, and the reference cell 1181 and 1182 may be performed during the re-write operation with respect to the memory cell 1111. The re-write operation may also be performed.
A bit line is additionally disposed corresponding to the reference cell array 1180, and the precharge operation and the selection operation on the bit line are performed the same as or similar to the bit line corresponding to the cell array 1110 storing data. do. When reading data, the column decoder 1130 selects a bit line connected to the first reference cell 1181 and the second reference cell 1182. Voltages of the bit lines connected to the first reference cell 1181 and the second reference cell 1182 are enveloped, and the developed voltages are sense amplifier circuit blocks as the first and second reference voltages VREFH and VREFL, respectively. 1150). The sense amplifier circuit block 1150 includes a plurality of sense amplifier circuits, and each sense amplifier circuit receives the first and second reference voltages VREFH and VREFL together with a corresponding data voltage VSA.
The memory cell 1111 stores data of any one of logic high and logic low, the first reference cell 1181 stores data of logic high, and the second reference cell 1182 stores data of logic low. do. According to the data stored in the memory cell 1111, the data voltage VSA has approximately the same level as one of the first and second reference voltages VREFH and VREFL, and has a different level from the other. In performing the differential amplification operation according to the level difference between the data voltage VSA and the first and second reference voltages VREFH and VREFL, for example, when data of logic high is stored in the memory cell 1111, the data voltage ( A differential output signal is generated according to the level difference between VSA) and the second reference voltage VREFL.
Meanwhile, the configuration and operation of the data read circuit 1300 of FIG. 5 will be described below. The data read circuit 1300, along with a read path VSA path that generates a data voltage VSA according to data stored in the memory cell 1111, includes a first reference path that generates a first reference voltage VREFH. It may include a (VREFH Path) circuit and a second reference path (VREFL Path) circuit for generating a second reference voltage (VREFL). Various circuits included in the data path VSA path may be identically disposed in the first and second reference paths VREFH Path and VREFL Path. For example, as shown in FIG. 5, the first reference path circuit VREFH path includes a precharge circuit 1142, a bit line selection circuit 1132, a clamping circuit 1192, and a first circuit connected to the first reference cell 1181. And a second reference path circuit (VREFL Path) circuit, which may include a current source (1162), similarly connected to the second reference cell (1182), the precharge circuit 1143, the bit line selection circuit 1133, the clamping circuit ( 1193 and current source 1163. Although each of the current sources 1161 to 1163 is shown as being a different current source, current from any one common current source may be used.
The data voltage VSA is provided to the first input terminal of the sense amplifier circuit 1151 through a bit line (hereinafter, referred to as a first bit line) connected to the memory cell 1111. In addition, the first and second reference voltages VREFH and VREFL are sensed through bit lines connected to the first and second reference cells 1181 and 1182 (hereinafter, the first and second reference bit lines). The second and third input terminals of the amplifier circuit 1151 are provided respectively. The sense amplifier circuit 1151 generates an output VOUT based on the integral and sensing / amplifying operations as described above.
According to the configuration shown in FIG. 5, only a pair of first and second reference cells 1181 and 1182 may be disposed in correspondence with a plurality of memory cells of the cell array 1110. not big. For example, a plurality of memory cells and first and second reference cells 1181 and 1182 may be disposed in correspondence to one word line, and a plurality of sense amplifier circuits for sensing data of the memory cells may be formed. The first and second reference voltages VREFH and VREFL generated in the first and second reference cells 1181 and 1182 may be commonly used.
6 is a block diagram illustrating an embodiment of a sense amplifier circuit included in a data read circuit according to an embodiment of the present invention.
As illustrated in FIG. 6, the sense amplifier circuit 1151 may be disposed corresponding to each of the bit lines, and may include a first sense amplifier 2100 and a second sense amplifier 2200. In addition, a delay unit 2300 for controlling the enable timing of the first sense amplifier 2100 and / or the second sense amplifier 2200 may be further provided in the sense amplifier circuit 1151. The first sense amplifier 2100 receives the data voltage VSA and the first and second reference voltages VREFH and VREFL, and the level difference between the data voltage VSA and the at least two reference voltages VREFH and VREFL. Generates differential output signals (VOUT, VOUTb) that are then enveloped.
For example, when the first and second reference voltages VREFH and VREFL are generated by the reference cells as shown in FIG. 4, one of the first and second reference voltages VREFH and VREFL and the data voltage VSA may be used. Differential output signals (VOUT, VOUTb) are generated according to the level difference therebetween. In addition, the second sense amplifier 2200 senses / amplifies and outputs differential output signals VOUT and VOUTb. In FIG. 6, although the output terminals of the first and second sense amplifiers 2100 and 2200 are shared with each other, and the input terminal and the output terminal of the second sense amplifier 2200 are the same, an embodiment of the present invention is not limited thereto. There is no. For example, the second sense amplifier 2200 may output a signal obtained by sensing and amplifying the differential output signals VOUT and VOUTb through another output terminal.
A control signal Ctrl for enabling the first sense amplifier 2100 is provided to the first sense amplifier 2100, and the control signal Ctrl is passed through the delay unit 2300 to the second sense amplifier 2200. Is provided. Accordingly, the second sense amplifier 2200 is enabled after a predetermined delay. The differential output signals VOUT and VOUTb are enveloped according to the differential amplification operation, and the differential output signals VOUT and VOUTb are sensed / amplified as the second sense amplifier 2200 is enabled after a predetermined delay. Accordingly, the accuracy of the data can be improved by sensing / amplifying the fully developed differential output signals VOUT and VOUTb, and by latching the amplified differential output signals VOUT and VOUTb at a predetermined time point, It is possible to generate a data signal having a full digital voltage level.
7 and 8 are circuit diagrams illustrating an embodiment of the sense amplifier circuit of FIG. 6. FIG. 8 is a circuit diagram illustrating the first and second sense amplifiers 2100 and 2200 of FIG. 7 separated from each other. Referring to FIGS. 7 and 8, the configuration and operation of the sense amplifier circuit 1151 will be described below.
The sense amplifier circuit 1151 may include first and second sense amplifiers 2100 and 2200 and a delay unit 2300. The first sense amplifier 2100 may include a first input unit 2110 for receiving a data voltage VSA according to a data value stored in a memory cell, and a second input unit for receiving first and second reference voltages VREFH and VREFL. A bias unit 2130 for biasing the 2120 and the first sense amplifier 2100 may be provided. In addition, the first sense amplifier 2100 may include one or more capacitors 2141 and 2142 and a differential output terminal configured to store differential amplification signals of the data voltage VSA and the first and second reference voltages VREFH and VREFL. A precharge unit 2150 may be further provided for precharging at a level.
The first input unit 2110 includes a plurality of input terminals for receiving a data voltage VSA. As an example, the first input unit 2110 includes two MOS transistors in a stacked structure, and the data voltage VSA is provided to the gates of the two MOS transistors. In addition, the second input unit 2120 includes a plurality of input terminals for receiving the first and second reference voltages VREFH and VREFL. As an example, the second input unit 2120 also includes two MOS transistors in a stack structure. do. The first and second reference voltages VREFH and VREFL are provided to gates of two MOS transistors of the second input unit 2120, respectively. The first capacitor 2141 is connected to the first input unit 2110 through a first differential output terminal, and the second capacitor 2142 is connected to the second input unit 2120 through a second differential output terminal.
Before performing the read operation, the precharge unit 2150 of the first sense amplifier 2100 is activated in response to the control signal Ctrl, and the differential output terminal of the first sense amplifier 2100 is set to a predetermined precharge voltage. Precharged. Thereafter, a difference occurs in the value of the current through the differential output terminal according to the level difference between the data voltage VSA and the first and second reference voltages VREFH and VREFL provided to the first and second input units 2110 and 2120. In addition, the level of the voltage applied to the differential output stage is changed accordingly. The changed voltage is stored in the first and second capacitors 2141 and 2142.
For example, when the first and second reference voltages VREFH and VREFL are generated from the reference cell array and the data of the memory cell has a value corresponding to logic high, the data voltage VSA and the first reference voltage VREFH Have substantially the same level, and thus an integration operation is performed based on the level difference between the data voltage VSA and the second reference voltage VREFL. According to the integration result, the voltage difference between the differential output signals VOUT and VOUTb gradually increases.
The second sense amplifier 2200 is enabled after a predetermined delay time after the precharge unit 2150 of the first sense amplifier 2100 is enabled. For example, the control signal Ctrl provided to the precharge unit 2150 is provided to the bias unit 2220 of the second sense amplifier 2200 via the delay unit 2300. That is, the enable timing of the second sense amplifier 2200 is adjusted (or the sensing timing of the differential output signals VOUT and VOUTb) is adjusted to secure time for the integration operation of the first sense amplifier 2100. ). When the differential output signals VOUT and VOUTb are sufficiently developed as an output of the first sense amplifier 2100, the second sense amplifier 2200 is enabled, and the second sense amplifier 2200 is configured to output the differential output signals VOUT, Sense / amplify VOUTb) to generate amplified differential output signals VOUT and VOUTb.
In the example of FIG. 8, the delay unit 2300 is implemented using a plurality of inverters, and a sensing time point is adjusted by delaying a control signal Ctrl for controlling the precharge unit 2150 of the first sense amplifier 2100. Although an example is shown, embodiments of the invention need not be limited thereto. As an example, the precharge unit 2150 of the first sense amplifier 2100 and the bias unit 2220 of the second sense amplifier 2200 may be controlled by separate control signals, and the timing of activation of each control signal may be controlled. When adjusting, the delay unit 2300 may be omitted. In addition, in the case of the first and second sense amplifiers 2100 and 2200 for sensing / amplifying an input signal, the voltage gain is dependent on device characteristics such as MOS transistors constituting the first and second sense amplifiers 2100 and 2200. May vary accordingly. The output waveforms of the first and second sense amplifiers 2100 and 2200 may be varied by adjusting the voltage gain of the amplifying operation.
9 and 10 are graphs showing examples of input and output waveforms of the sense amplifier circuit of FIG. 6. FIG. 9 is a graph when first and second reference voltages VREFH and VREFL are generated from a reference cell array, and FIG. 10 is a diagram illustrating first and second reference voltages VREFH and VREFL generated from a reference voltage generator. Graph of the case. 7 to 10, the operation of the sense amplifier circuit 1151 will be described. It is assumed that data of logic high is stored in the memory cell.
The differential output signals VOUT and VOUTb of the first sense amplifier 2100 maintain the precharge level prech. Thereafter, when the memory cell is selected for the read operation, the data voltage VSA of the bit line connected to the memory cell is developed. As the memory cell is selected and the first and second reference cells are selected, the first and second reference voltages VREFH and VREFL are also developed. The data voltage VSA has a value substantially equal to the first reference voltage VREFH.
The differential output signals VOUT and VOUTb are developed according to the level difference between the data voltage VSA and the second reference voltage VREFL, and a sensing operation is performed after a predetermined delay time. The sensing operation may be performed by enabling the second sense amplifier 2200, and the differential output signals VOUT and VOUTb are amplified to a full digital level by the sensing. The amplified differential output signals VOUT and VOUTb are latched at a predetermined time point after the sensing operation, and the latched information is provided externally as read data.
Meanwhile, as shown in FIG. 10, the first and second reference voltages VREFH and VREFL generated from the reference voltage generator have a constant voltage level. When the memory cell is selected for the read operation, the data voltage VSA of the bit line connected to the memory cell is developed, and the level of the data voltage VSA gradually increases so that the level of the data voltage VSA at a predetermined time is increased. The level of the first reference voltage VREFH is exceeded.
Meanwhile, the differential output signals VOUT and VOUTb of the first sense amplifier 2100 maintain the precharge level, and the differential output signals VOUT and VOUTb are developed as the data voltage VSA changes. . After the differential output signals VOUT and VOUTb have been developed, a sensing operation is performed after a predetermined delay time. Preferably, the sensing operation is performed at a time when the data voltage VSA and the first reference voltage VREFH have the same level. Allow sensing operation to be performed within time. By the sensing, the differential output signals VOUT and VOUTb are amplified to a full digital level, and the amplified differential output signals VOUT and VOUTb are latched at a predetermined time point after the sensing operation.
FIG. 11A is a graph illustrating a comparison of a data signal waveform of a conventional data lead circuit and a data signal waveform of a data lead circuit according to an exemplary embodiment of the present invention, and FIG. It is a graph comparing the access time.
As shown in FIG. 11A, in a sense amplifier circuit according to an embodiment of the present invention, a differential output signal stored in an integrating capacitor is directly provided to an input of a sense amplifier for sensing / amplification, and thus a differential output signal. As is amplified to a large gain, it is possible to develop directly to the full digital level. Accordingly, when the embodiment of the present invention is applied, the development speed and the full digital voltage recovery capability are excellent compared to the data lead circuit of the conventional design.
On the other hand, Figure 11b shows the access time in the conventional case and the access time when the embodiment of the present invention is applied. The access time may be defined as a time from when the sense amplifier is enabled to when the development voltage difference reaches 100 mV. When the number of cells per bitline increases, the access time tends to increase overall. However, according to the embodiment of the present invention, the access time can be shortened to within 2 ns in the whole case.
12 and 13 are flowcharts illustrating a data reading method of a nonvolatile memory device according to an embodiment of the present invention.
According to the data read method, a data voltage resulting from any one memory cell and at least two reference voltages are provided to the sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier for differentially amplifying a voltage difference between the data voltage and the first and second reference voltages, and a second sense amplifier for receiving and sensing / amplifying an output of the first sense amplifier. can do. The first sense amplifier may be implemented as an integrated circuit that generates a differential output signal in response to one data voltage and outputs the differential output signal through the differential output terminal. In addition, the second sense amplifier may be implemented as an amplifier circuit for receiving and amplifying the differential output signal through the differential output stage, and outputting the amplified signal through the differential output stage.
As a predetermined control signal is provided to the first sense amplifier, the first sense amplifier is enabled (S11). The first sense amplifier may include a precharge unit for precharging the differential output terminal to a predetermined level, and the predetermined control signal may be a precharge control signal for activating the precharge unit. In addition, the memory cell is selected according to a result of decoding the address provided from the outside (S12). A data voltage corresponding to data stored in the selected memory cell is generated, and first and second reference voltages are generated to read data stored in the memory cell (S13). The first and second reference voltages may be generated from a reference voltage generator that generates a predetermined DC voltage value as in the above-described embodiments, or reference cells for storing information corresponding to logic high and logic low. It may be a voltage developed by.
The first sense amplifier receives the data voltage, the first and second reference voltages, and generates a differential output signal obtained by amplifying a level difference between the data voltages and the first and second reference voltages (S14). The first sense amplifier may include two input terminals for receiving a data voltage in common, and two input terminals for receiving the first and second reference voltages, respectively. In addition, the first sense amplifier may be implemented as an integration circuit that performs an integration operation using at least two capacitors, and stores a voltage according to the integration operation in the at least two capacitors. The voltage level stored in each of the at least two capacitors varies according to the data voltage and the level difference between the first and second reference voltages. For example, when the first and second capacitors are provided in the first sense amplifier, the first capacitor The voltage at one node of and the voltage at one node of the second capacitor may be generated as a differential output signal.
After the predetermined delay time has elapsed, the second sense amplifier is enabled (S15). The delay time can be adjusted by delay means such as an inverter chain or the like. The delay time may be a time between when the first sense amplifier is enabled (or when the precharge part of the first sense amplifier is activated) and when the bias voltage is applied to the second sense amplifier. In this case, a signal obtained by delaying the precharge control signal may be used as a control signal for controlling the bias of the second sense amplifier.
The second sense amplifier is connected to the differential output terminal of the first sense amplifier to receive the differential output signal. In addition, when the second sense amplifier is enabled, the differential output signal is sensed and the amplified differential output signal is generated as read data (S16). The output terminal of the second sense amplifier may be commonly connected to the differential output terminal of the first sense amplifier, and thus the read data may be output through the differential output terminal.
FIG. 13 is a flowchart illustrating specific operations of the first and second sense amplifiers of FIG. 12. As shown in FIG. 13, the precharge operation of the first sense amplifier is performed by the precharge control signal (S21). The precharge operation may be performed by precharging the level of the differential output stage to a predetermined level.
As the data voltage and the first and second reference voltages are provided to the first sense amplifier, an operation of integrating the level difference between the data voltage and the first and second reference voltages is performed (S22). When the first and second reference voltages are generated from the reference cells, the level of one reference voltage has a value substantially equal to that of the data voltage, and the level of the other reference voltage is different from the level of the data voltage. Have For example, when data corresponding to logic high is stored in the memory cell, the data voltage is approximately equal to the first reference voltage and its level, and the level difference between the data voltage and the second reference voltage is integrated. The first sense amplifier generates a differential output signal according to the integration operation (S23).
After a predetermined delay time after the precharge time, the second sense amplifier is activated (S24). The second sense amplifier receives the differential output signal from the first sense amplifier, senses the differential output signal after the predetermined delay time, and generates an amplified differential output signal (S25). The amplified differential output signal is latched at a predetermined time point after the start of the amplification operation (S26), and the latched differential output signal is output as read data (S27).
14 is a circuit diagram illustrating an implementation of a data read circuit according to another embodiment of the present invention. As illustrated in FIG. 14, the data read circuit 3100 may be disposed to correspond to each of a plurality of bit lines included in the nonvolatile memory device.
The data read circuit 3100 is a variety of circuits for reading data of the memory cell 3110. For example, the data read circuit 3100 selects a precharge circuit 3130 and a bit line connected to the bit line to precharge the bit line to a predetermined level. A bit line selection circuit 3120, a clamping circuit 3140 for clamping the bit line, and a current source 3150 for providing a current to the bit line. 14 shows an example in which the memory cell 3110 is an MRAM cell including an MTJ.
In addition, the data read circuit 3100 may include a first sense amplifier circuit 3160 that performs a sensing / amplification operation due to an integration operation using a plurality of reference voltages according to an embodiment of the present invention. The second sense amplifier circuit 3170 may perform a sensing / amplification operation. In addition, in order to selectively include each of the first and second sense amplifier circuits 3160 and 3170 in the data read circuit 3100, the data read circuit 3100 may perform a first response in response to the first control signal Ctrl_11. The first control circuit 3171 for controlling the selection of the sense amplifier circuit 3160 and the second control circuit for controlling the selection of the second sense amplifier 3170 in response to the second control signal Ctrl_12. 3171 may be further provided.
The first and second control circuits 3141 may be implemented as MOS transistors that receive the first and second control signals Ctrl_11 and Ctrl_12 through gate electrodes, respectively. In addition, the first and second electrodes of the first control circuit 3151 are connected to an input terminal (eg, a first input terminal receiving a data voltage VSA) and an output terminal of the first sense amplifier circuit 3160, respectively. In addition, the first and second electrodes of the second control circuit 3171 may be connected to an input terminal (eg, a first input terminal receiving the output VOUT1 of the first control circuit) and an output terminal of the second sense amplifier circuit 3170, respectively. Connected. The first sense amplifier circuit 3160 receives the first and second reference voltages VREFH and VREFL through the second and third input terminals, respectively. As described above, the first and second reference voltages VREFH and VREFL may be DC voltages generated in the nonvolatile memory device using voltages from outside or DC voltages provided directly from the outside. Alternatively, the first and second reference voltages VREFH and VREFL may be voltages developed by a reference cell that stores information corresponding to logic high or logic low.
Meanwhile, the second sense amplifier circuit 3170 receives the reference voltage VREF through the second input terminal. The reference voltage VREF may be a DC voltage generated in the nonvolatile memory device or directly provided from the outside. In addition, the reference voltage VREF may have a level corresponding to an intermediate value between the first and second reference voltages VREFH and VREFL.
According to the embodiment illustrated in FIG. 14, in addition to the second sense amplifier circuit 3170 in which the data read circuit 3100 performs an amplification operation using a single reference voltage VREF, the dual reference voltages VREFH and VREFL are used. An integrated circuit based first sense amplifier circuit 3160 is further provided. In the test mode of the nonvolatile memory device, the first and second control signals Ctrl_11 and Ctrl_12 may be provided to the first and second sense amplifier circuits 3160 and 3170, respectively. Accordingly, the first and second sense amplifiers may be provided. Characteristics of the output waveforms using the circuits 3160 and 3170 may be determined. When the second sense amplifier circuit 3170 is selected, the data voltage VSA through the bit line is provided to the first input terminal of the second sense amplifier circuit 3170 via the first control circuit 3151. The second sense amplifier circuit 3170 compares the level of the data voltage VSA and the reference voltage VREF and outputs an amplified signal VOUT2 corresponding to the result.
On the other hand, when the first sense amplifier circuit 3160 is selected, the data voltage VSA is provided to the first input terminal of the first sense amplifier circuit 3160, and as described in the above-described embodiment, the data voltage ( An integration operation is performed according to the level difference between VSA) and the first and second reference voltages VREFH and VREFL, and a differential output signal is generated according to the integration result. Thereafter, as the differential output signal is sensed / amplified at a predetermined time point, the amplified signal VOUT1 is output from the first sense amplifier circuit 3160. The output terminal of the first sense amplifier circuit 3160 may be electrically connected to the output terminal of the second sense amplifier circuit 3170 via the second control circuit 3171.
In the test mode, the waveform of the data signal may be analyzed using the amplified signals VOUT1 and VOUT2 output from the first and second sense amplifier circuits 3160 and 3170. With reference to the analysis result, one of the first and second sense amplifier circuits 3160 and 3170 may be set to be used in the normal operation of the nonvolatile memory device. For example, when it takes a long time for the amplified signal VOUT1 from the second sense amplifier circuit 3170 to be developed at the full digital level, the first sense amplifier circuit 3160 may be turned off during normal operation of the nonvolatile memory device. Enabled. The nonvolatile memory device may include a mode register set (not shown) for setting an operation mode, and the first and second control circuits 3171 and 3171 may be configured to be initially driven by the nonvolatile memory device. It can be controlled by the MRS code.
15 is a block diagram illustrating an implementation of a data read circuit according to another embodiment of the present invention. For convenience of description, only the sense amplifier circuit is shown among the components included in the above-described data read circuit.
In FIG. 15, a data read circuit 4100 for reading data of a unit cell storing two or more bits of data is shown. For example, the nonvolatile memory device may store two bits of data per memory cell (or unit cell). A multi-level cell may be used to implement a unit cell that stores one 2-bit data, or two single-level cells may store two bits of data. One unit cell may be implemented.
When two bits of data are stored in a unit cell, the data voltage VSA transmitted through the bit line connected to the unit cell has any one of four level states. In addition, a plurality of reference voltages are used to read data stored in a unit cell, and for example, four reference voltages VREFH, VREFL, VREFHM, and VREFLM are used. The reference voltages VREFH, VREFL, VREFHM, and VREFLM may be generated from reference cells storing each of four data states similarly to the above-described embodiments. Alternatively, the reference voltages VREFH, VREFL, VREFHM, and VREFLM may be DC voltages generated in the nonvolatile memory device using a voltage from an external source or directly provided from the external source.
The data read circuit 4100 may include a first sense amplifier circuit 4110 and a second sense amplifier circuit 4120 corresponding to one bit line. Each of the first and second sense amplifier circuits 4110 receives a data voltage VSA and at least two reference voltages. For example, when two bits of data are stored in a unit cell, four reference voltages are generated, and the first sense amplifier circuit 4110 receives the first and fourth reference voltages VREFH and VREFL, and the second reference voltage. The sense amplifier circuit 4120 may receive the second and third reference voltages VREFHM and VREFLM.
Each of the first and second sense amplifier circuits 4110 differentially amplifies the input voltages and performs a sensing / amplifying operation on the differential output signal as described in the above embodiments. The first sense amplifier circuit 4110 generates a differential output signal by integrating a level difference between the data voltage VSA and the first and fourth reference voltages VREFH and VREFL, and generates the differential output signal at a predetermined time point. Sensing / amplifying at generates the amplified differential output signals (VOUT1, VOUT1b). Similarly, the second sense amplifier circuit 4120 generates a differential output signal by integrating the level difference between the data voltage VSA and the second and third reference voltages VREFHM and VREFLM. The amplified differential output signals VOUT2 and VOUT2b are generated by sensing / amplifying the output signal at a predetermined point in time. The data read circuit 4100 may further include a decoding circuit 4130 for receiving amplified differential output signals VOUT1, VOUT1b, VOUT2, and VOUT2b.
The decoding circuit 4130 decodes the amplified differential output signals VOUT1, VOUT1b, VOUT2, and VOUT2b to generate a data signal Data. The level of the data voltage VSA has a different value depending on the data stored in the unit cell, and the amplified differential output signals VOUT1, VOUT1b, VOUT2, VOUT2b) also has different levels. The decoding circuit 4130 analyzes the levels of the amplified differential output signals VOUT1, VOUT1b, VOUT2, and VOUT2b to generate a 2-bit data signal Data.
In FIG. 15, an embodiment for reading two bits of data per unit cell and an embodiment in which two sense amplifier circuits 4110 and 4120 are disposed in correspondence to one unit cell are illustrated, but the present invention is limited thereto. There is no need. As an example, three or more sense amplifier circuits may be disposed in correspondence to one unit cell in order to improve the accuracy of the decoding operation. In this case, by properly combining the four reference voltages VREFH, VREFL, VREFHM, and VREFLM, each of the sense amplifier circuits may provide different dual reference voltages. For example, in addition to the sense amplifier circuit illustrated in FIG. 15, an additional sense amplifier circuit (for example, two sense amplifier circuits) may be further disposed, and one sense amplifier circuit may include first and third reference voltages. The data read circuit may be implemented in a form of providing (VREFH and VREFLM) and providing second and fourth reference voltages VREFHM and VREFL as another sense amplifier circuit.
In addition, more than three bits of data may be stored per unit cell, in which case a greater number of reference voltages may be generated from the reference cells or from the reference voltage generator.
16 and 17 are block diagrams illustrating an example of a layout of a nonvolatile memory device according to an embodiment of the present invention. FIG. 16 illustrates an example in which sense amplifier circuit blocks are separately arranged for each cell array, and FIG. 17 illustrates an example in which a plurality of cell arrays share a sense amplifier circuit block.
As illustrated in FIG. 16, the nonvolatile memory device 5000 may include a cell array 5100 including a plurality of memory cells 5110, a row decoder 5200 for selecting a word line of the cell array 5100, It may include a column selection area 5300 for selecting a bit line of the cell array 5100. The column select region 5300 may include a sense amplifier circuit block of a data read circuit according to an exemplary embodiment of the present invention, and the column select region 5300 may respond to a column select signal from a column decoder (not shown). To control the connection between the bit line and the sense amplifier circuit 5310.
The cell array 5100 may include a plurality of reference cells for generating the reference voltages VREFH and VREFL. For example, the cell array 5100 may include a first reference cell 5121 and a first reference cell for generating the first reference voltage VREFH. It may include a second reference cell (5122) for generating a second reference voltage (VREFL). A plurality of memory cells 5110 and first and second reference cells 5121 and 5122 may be connected to one word line, and data voltages from the plurality of memory cells 5110 may be sensed through respective bit lines. It is provided to one input terminal of the amplifier circuit 5310.
The voltage developed on the bit lines connected to the first and second reference cells 5121 and 5122 is provided to the column selection region 5300 as the first and second reference voltages VREFH and VREFL. A plurality of sense amplifier circuits 5310 may be disposed in the column selection region 5300, and the first and second reference voltages VREFH and VREFL may be commonly provided to the plurality of sense amplifier circuits 5310. . That is, the first and second reference voltages VREFH and VREFL generated from the first and second reference cells 5121 and 5122 are provided to the sense amplifier circuit 5310 locally, and the sense amplifier circuit 5310 is provided. The read data generated from) is transferred to an input / output circuit (not shown) through a global line (not shown).
FIG. 17 is a diagram illustrating an implementation having a layout different from that of the nonvolatile memory device of FIG. 16. As shown in FIG. 17, the nonvolatile memory device 6000 includes a plurality of memory cells 6110. The cell array 6100, a row decoder 6200 for selecting a word line of the cell array 6100, and a column selection region 6300 for selecting a bit line of the cell array 6100 may be included. In addition, the cell array 6100 may include a first reference cell 6121 for generating a first reference voltage VREFH and a second reference cell 6222 for generating a second reference voltage VREFL. .
In addition, the nonvolatile memory device 6000 further includes a column decoder region 6400 for decoding a column address to generate a column selection signal. The column decoder region 6400 may be disposed at one side in correspondence with the plurality of cell arrays 6100, and the column selection signal from the column decoder region 6400 is globally transmitted to be common to at least two cell arrays 6100. Can be provided. In addition, a plurality of sense amplifier circuits 6410 may be disposed in the column decoder region 6400.
In the column select region 6300, a local transfer line LIO for locally delivering the first and second reference voltages VREFH may be disposed, and the first and second reference cells 6121 and 6122 may be disposed. The first and second reference voltages VREFH and VREFL are provided to the column decoder region 6400 through the local transfer line LIO and the global transfer line GIO. The first and second reference voltages VREFH and VREFL transferred through the global transmission line GIO may be commonly provided to the plurality of sense amplifier circuits 6410.
According to the structure of the nonvolatile memory device 6400 illustrated in FIG. 17, since the sense amplifier circuit 6410 has a structure shared by the plurality of cell arrays 6100, an area occupied by the sense amplifier circuit 6410 may be reduced. Can be. On the other hand, since the data voltages and the reference voltages before being developed to the full digital level are transmitted through the global line, there is a possibility of occurrence of a variation in the voltage level according to the resistance component of the global line. These data read circuits have the capability of reducing the influence of the deviation, thereby improving the reliability of the read data.
18 is a circuit diagram illustrating an example of a data read circuit of a nonvolatile memory device according to another exemplary embodiment of the present invention. 18 shows an embodiment in which a memory different from the MRAM described in the above embodiment is applied.
As shown in FIG. 18, the data read circuit 7100 includes various circuits for reading data stored in the memory cell 7110, and as an example, a data voltage VSA and at least two reference voltages VREFH and VREFL. ) And a sense amplifier circuit 7120 for sensing and amplifying. In addition, the data read circuit 7100 may include a precharge circuit 7130 for precharging the bit line to a predetermined level, a bit line selection circuit 7140 for selecting the bit line, and a clamping circuit for clamping the bit line ( 7150 and a current source 7160 for providing a current to the bit line.
The memory cell 7110 may include a resistive memory such as a PRAM cell or an RRAM cell as a nonvolatile memory cell. As shown in FIG. 18, the PRAM cell and the RRAM cell may be configured or modeled as one diode and one resistive element connected in series. Data is stored according to the variable resistance characteristic of the resistive element, one node of the resistive element is connected to the bit line, and one node (eg, the cathode electrode) of the diode is connected to the word line WL. Although not shown in FIG. 18, when the nonvolatile memory cell is implemented with FRAM, the resistive element among the components illustrated in the drawing may be replaced with a ferroelectric capacitor using a ferroelectric thin film.
As in the above-described embodiment, the reference voltages VREFH and VREFL may be generated from a reference cell (not shown) having the same structure as that of the memory cell 7110. As an example, by performing a write operation on the reference cell once, the resistive elements of some reference cells have a high resistance, and the resistive elements of some of the reference cells have a low resistance. Have it. Subsequently, during the data read operation, the reference cell is selected to develop the voltage of the bit line connected to the reference cell to one of the reference voltages VREFH and VREFL. The sense amplifier circuit 7120 receives the data voltage VSA and the reference voltages VREFH and VREFL, performs an integration operation according to a voltage level difference, and generates a differential output signal, and the differential output signal at a predetermined time point. The output signal VOUT is amplified by sensing / amplifying.
19 is a block diagram illustrating an application example of an electronic system having a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 19, an electronic system 8100 includes an input device 8110, an output device 8120, a memory device 8140, and a processor device 8130. The memory device 8140 may be a concept including a cell array including a nonvolatile memory cell and a peripheral circuit for an operation such as read / write, or a concept including a nonvolatile memory device and a memory controller in terms of a system. Can be. As an example, assuming that the memory device 8140 includes a memory controller and a nonvolatile memory device, the memory 8141 of FIG. 19 may be applied to the nonvolatile memory device according to the embodiment of the present invention. The processor device 8130 is connected to the input device 8110, the output device 8120, and the memory device 8140 through a corresponding interface to control the overall operation.
20 is a block diagram showing an application example of a single chip microcomputer having a nonvolatile memory device of the present invention. Referring to FIG. 20, a microcomputer in the form of a circuit module includes a central processing unit 8290, a memory used as a work area of the CPU 8290, and the like. RAM 8280, bus controller 8270, oscillator 8220, frequency divider 8230, nonvolatile memory 8240, power supply circuit 8250, input / output port 8260 and timer counter Other peripheral circuits 8210 including a timer counter and the like.
The CPU 8290 includes a command control part (not shown) and an execution part (not shown), and decodes a fetched command through the command control part and executes it according to the decoding result. Processing is performed through the unit. The nonvolatile memory 8230 stores various types of data in addition to storing data of an operation program or the CPU 8290. The power supply circuit 8250 generates a voltage necessary for a read / write operation of the nonvolatile memory 8240, and the like. The frequency divider 8230 divides the source frequency provided from the oscillator 8220 into a plurality of frequencies to provide reference clock signals and other internal clock sugnals.
The internal bus includes an address bus, a data bus, and a control bus. The bus controller 8270 controls bus access in response to an access request from the CPU 8290. When a microcomputer is mounted in the system, the CPU 8290 controls the read / write operation for the nonvolatile memory 8230. In the test or manufacturing stage of the device, as an external recording device, read / write operations to the nonvolatile memory 8230 can be directly controlled via the input / output port 8260.
At least one of the nonvolatile memory 8230 and the RAM 8280 may be a nonvolatile memory device according to an embodiment of the present invention. That is, in addition to the nonvolatile memory device of the present invention for storing a large amount of data, the nonvolatile memory device of the present invention may be applied in place of the RAM 8280 that requires fast read / write time.
21 is a block diagram illustrating an example of a computer system equipped with a nonvolatile memory device according to the present invention.
Referring to FIG. 21, a nonvolatile memory device 8310 of the present invention may be mounted in a computer system such as a mobile device or a desktop computer. The computer system 8300 may include a nonvolatile memory system 8310, a modem 8320, a central processing unit 8330, a RAM 8340, and a user interface 8350 that are electrically connected to a system bus. The nonvolatile memory system 8310 may include a memory controller 8312 and a nonvolatile memory device 8311. For example, FIG. 21 illustrates a case where MRAM is applied as the nonvolatile memory device 8311.
The nonvolatile memory system 8310 stores data processed by the central processing unit 8330 or data input from the outside. The nonvolatile memory system 8310 may include a flash memory or a nonvolatile memory such as MRAM, PRAM, RRAM, and FRAM. In addition, at least one of the nonvolatile memory system 8310 and the RAM 8340 may be a nonvolatile memory device according to an embodiment of the present invention. That is, the nonvolatile memory device according to the embodiment of the present invention may be applied to a memory for storing a large amount of data required for the computer system 8300 or a memory for storing data requiring fast access such as system data. . Although not shown in FIG. 21, the information processing system 8300 may further include an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-explanatory to those who have learned.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (29)

  1. A cell array comprising nonvolatile memory cells;
    A bit line connected to the nonvolatile memory cell to transfer a data voltage; And
    Receives the data voltage through a first input unit, receives at least two reference voltages through a second input unit, and generates read data by differentially amplifying input signals provided to the first and second input units during a data read operation. A nonvolatile memory device having a sense amplifier circuit.
  2. The method of claim 1,
    The first input unit includes first and second input terminals for receiving the data voltage, respectively,
    The second input unit includes a third input terminal for receiving a first reference voltage and a fourth input terminal for receiving a second reference voltage.
  3. The method of claim 2, wherein the sense amplifier circuit,
    The nonvolatile memory device generating the read data by differentially amplifying any one of the first and second reference voltages with the data voltage.
  4. The method of claim 1, wherein the sense amplifier circuit,
    A first sense amplifier configured to differentially amplify input signals provided to the first and second input units to generate a differential output signal; And
    And a second sense amplifier configured to sense and amplify the differential output signal to generate the read data.
  5. The method of claim 4, wherein the first sense amplifier,
    And an integrating circuit for integrating a voltage level difference between input signals provided to the first and second input units.
  6. The method of claim 4, wherein the second sense amplifier,
    And a latch type sense amplifier configured to receive the differential output signal through the differential output terminal of the first sense amplifier and output the amplified signal through the differential output terminal.
  7. The method of claim 1,
    The cell array stores a first state of data in a first state and is connected to the second input through a first line, and the second state of cell stores a data in a second state and is connected to the second input through a second line. Further comprising a second reference cell,
    And supplying voltages from the first and second reference cells to the second input unit as first and second reference voltages, respectively.
  8. The method of claim 1,
    And a reference voltage generator configured to generate first and second reference voltages using a power supply voltage.
    The reference voltage generator is configured to provide the first and second reference voltages to the second input unit.
  9. The method of claim 1,
    The nonvolatile memory cell is any one of magnetic random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PRAM), and ferroelectric random access memory (FRAM).
  10. A first input unit for receiving a data voltage from a nonvolatile memory cell and a second input unit for receiving first and second reference voltages, and differentially amplifying input signals provided to the first and second input units A first sense amplifier generating a signal; And
    And a second sense amplifier configured to sense and amplify the differential output signal to generate an amplified signal.
  11. The method of claim 10,
    And a delay unit configured to control the enabling of the second sense amplifier to control the sensing timing of the second sense amplifier.
  12. The method of claim 11, wherein the delay unit,
    And a precharge control signal for precharging the differential output terminal of the first sense amplifier, and providing the second sense amplifier a signal obtained by delaying the precharge control signal.
  13. The method of claim 10,
    The first input portion includes first and second MOS transistors stacked in series, the second input portion includes third and fourth MOS transistors stacked in series,
    The data voltage is provided to a gate electrode of each of the first and second MOS transistors,
    And the first and second reference voltages are provided to gate electrodes of the third and fourth MOS transistors, respectively.
  14. The method of claim 10, wherein the first sense amplifier,
    A first capacitor connected to the first input through a first differential output terminal; And
    And a second capacitor coupled to the second input through a second differential output.
  15. 15. The method of claim 14,
    And a differential output signal obtained by differentially amplifying the reference voltage of the first and second reference voltages and the data voltage is stored in the first and second capacitors.
  16. The method of claim 10, wherein the second sense amplifier,
    And a latch type sense amplifier configured to receive the differential output signal through the differential output terminal of the first sense amplifier and output the amplified signal through the differential output terminal.
  17. The method of claim 10,
    A third sense amplifier configured to receive the data voltage and a third reference voltage and sense and amplify the data voltage using the third reference voltage;
    A first control circuit for controlling selection of the first and second sense amplifiers in response to a first control signal; And
    And a second control circuit for controlling the selection of the third sense amplifier in response to a second control signal.
  18. A cell array including a plurality of memory cells and first and second reference cells respectively storing data of the first and second states;
    A first bit line connected to each of the plurality of memory cells;
    Second and third bit lines connected to the first and second reference cells, respectively; And
    A plurality of sense amplifier circuits disposed corresponding to the plurality of memory cells, each sense amplifier circuit receiving a data voltage through the first bit line and receiving first and second data through the second and third bit lines. And a sense amplifier circuit block configured to receive a second reference voltage and sense and amplify the data voltage using the first and second reference voltages.
  19. 19. The method of claim 18,
    The data of the first state is data of logic high, and the data of the second state is data of logic low.
  20. 19. The method of claim 18, wherein each of the sense amplifier circuits,
    Receives the data voltage through a first input unit, receives the first and second reference voltages through a second input unit, and differentially amplifies input signals provided to the first and second input units to generate a differential output signal. A first sense amplifier; And
    And a second sense amplifier configured to sense and amplify the differential output signal to generate an amplified signal.
  21. 21. The method of claim 20,
    The first sense amplifier may include an integration circuit configured to generate a differential output signal by integrating at least one of the first and second reference voltages with a voltage level difference between the data signal,
    And the second sense amplifier comprises an amplifier circuit for sensing and amplifying the differential output signal.
  22. 21. The method of claim 20,
    The first input unit includes a plurality of first MOS transistors that receive the data voltage in common and are connected in series, and the second input unit receives a plurality of second MOSs that receive the first and second reference voltages in series. A transistor,
    The first sense amplifier,
    A first capacitor connected to one electrode of the first input unit and storing a voltage of a first differential output terminal;
    A second capacitor connected to one electrode of the second input unit and storing a voltage of a second differential output terminal; And
    And a precharge unit for precharging the first and second differential output terminals in response to a first control signal.
  23. The method of claim 22, wherein the second sense amplifier,
    A latch circuit receiving the differential output signal through the first and second differential output stages, sensing and amplifying the differential output signal, and outputting the differential output signal through the differential output stage; And
    And a bias unit configured to activate sensing and amplifying operations of the latch circuit in response to a second control signal.
  24. The method of claim 23, wherein the sense amplifier circuit,
    And a delay unit configured to receive and delay the first control signal and to provide the delayed first control signal as the second control signal to the second sense amplifier.
  25. 19. The method of claim 18,
    And non-volatile data of the first and second states are periodically rewritten to the first and second reference cells, respectively.
  26. Precharging the differential output stage of the first sense amplifier;
    Providing a data voltage, a first and a second reference voltage to the first sense amplifier;
    Generating a differential output signal by performing a differential amplification operation using the data voltage and the first and second reference voltages;
    Enabling the second sense amplifier after a predetermined delay time; And
    And sensing and amplifying the differential output signal in the second sense amplifier to generate read data.
  27. The method of claim 26,
    And the first and second reference voltages are generated from first and second reference cells that store data in first and second states, respectively.
  28. 27. The method of claim 26, wherein generating the differential output signal comprises:
    Integrating a level difference between at least one of the first and second reference voltages and the data voltage.
  29. The method of claim 26,
    And the second sense amplifier is enabled after the predetermined delay time after precharging the differential output terminal of the first sense amplifier.
KR1020110085146A 2011-08-25 2011-08-25 Data read circuit, nonvolatile memory device having the same and method for reading data of nonvolatile memory device KR20130022540A (en)

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KR1020110085146A KR20130022540A (en) 2011-08-25 2011-08-25 Data read circuit, nonvolatile memory device having the same and method for reading data of nonvolatile memory device
US13/562,871 US9042152B2 (en) 2011-08-25 2012-07-31 Data read circuit, a non-volatile memory device having the same, and a method of reading data from the non-volatile memory device
DE102012107639A DE102012107639A1 (en) 2011-08-25 2012-08-21 Method for reading data from e.g. phase change RAM, involves scanning voltage level difference between data voltage and reference voltages to produce differential output signals, and amplifying output signals to produce read data
TW101130500A TWI579842B (en) 2011-08-25 2012-08-22 Non-volatile memory device,method of reading data from non-volatile memory device and spin torque transfer magnetic random access memory device
JP2012185018A JP2013045498A (en) 2011-08-25 2012-08-24 Nonvolatile memory device, data reading method thereof and sttmram device
CN2012103092222A CN102956268A (en) 2011-08-25 2012-08-27 Data reading circuit, non-volatile memory device and data reading method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3427264A4 (en) * 2016-03-11 2019-10-30 Micron Technology, INC. Memory cell sensing with storage component isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3427264A4 (en) * 2016-03-11 2019-10-30 Micron Technology, INC. Memory cell sensing with storage component isolation

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