經滴部中央標準局員工消費合作社印製 A7 * B7__ 五、發明説明（，） 發明昔齧 本發明有關一種非揮發性半導體記億體裝置，尤其是 有關一種在一記憶體晶胞中包括一鐵電電容器的鐵電記 億體裝置。 第1A圖為一鐵電電容器的符號，而第1B圖則顯示節點 電荷與作用在其上之電壓之間的關僳。 請參考第1B_,熟習本技術者應熟知對於使用鐵電材 料作為電介質材料的電容器，將電壓作用在電容器的兩 節點之間時，將産生磁滯特戡，且由於電壓之故，將累 積電荷。 當鐵電電容器的兩節點之間的電壓為0 [伏特]時，可累 積電MQ的鐵電電容器存在兩種狀態，例如"S1”及"S2’’e 結果，甚至沒有供電時，鐵電電容器可儲存資料之二位 元型式。由於鐵電電容器的此特性，所以可利用作非揮 發性記億體裝置的記億體元件。而且，依據作用在鐵電 電容器兩端的電壓而改變鐵電電容器的極化狀態，因此 儲存在鐵電電容器的電荷改變。如果對在"S1"極化狀態 的鐵電電容器作用以適當的負電壓，電容器狀態隨箸第 1B圖的箭頭方向改變，因此極化狀態也隨箸改變。隨後 ，如果在電容器兩端之間的電壓為” 0”伏特時，則其狀 態成為”S2”狀態。當電壓作用在電容器兩端時，由偵測 所産生之電荷量之變化程度，謓取儲存在鐵電電容器中 的資料。 第2圖示當-VI電壓施加在鐵電電容器之兩端及當+ vi 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） I^-------C3-衣------訂 踩 (諳先閱讀背面之注意事項再填寫本頁) _ A7 ' B7 五、發明説明（> ), 電壓施加在鐵電電容器兩端時，電荷量狀態的變換，其 中鐵電電容器之"S1"的狀態定義為資料"1"，且鐵電電 容器之"S2”狀態定義為資料"0"。首先，吾人假設-VI電 壓施加在鐵電電容器兩端。當鐵電電容器的初始狀態為 "S1"時，其狀態改變為"S3"狀態，而電荷量改變為AQ1 。同時，在鐵電電容器之初始狀態為” S2"的例子中，其 狀態改變為” S4"狀態，而電荷量改變為AQ0。此電椅量 的改變為含位元線的電荷耦合，其等於記億體晶胞陣列 的位元線電容器〇而且，位元線電位的變動使得感測放 大器動作，因此由少量電荷産生的小信號被放大而作為 資料輸出。 經满部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 第3圖顯示傳統上使用鐵電電容器之鐵電記億髏裝置的 電路圖，其包含一 _測放大器SA, —鐵電記億體裝置Ml, 琴考電壓産生器R1及一預充電電路P1。感測放大器SA感 測且放大位元線B L及反相位元線B L B之間的檝小電位差。 記億體晶胞Ml包括多個單元記億體晶胞，各晶胞包括一 切換電晶體及一鐵電電容器，且用於儲存資料。參考電 壓産生器R1産生用於感測及放大所需的參考電壓。預充 電電路P1預充電位元線BL及反相位元線BLB至一接地準 位。在記億體晶胞Μ 1的切換電晶體中，其源極耦合位元 線，且其閘極耦合一字元線。鐵電電容器的一端耦合切 換電晶體的汲極，而另一端耦合一板線CP,以驅動鐵電 電容器。因此該預充電電路Ρ1與位元線BL及反相位元線 BLB之間形成串聯耦合，且包含兩NMOSi電晶體，此電晶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A 7 B7 五、發明説明（4 ) 體的閘極上施加入一位元線預充電信號BLP,且其共源 搔網合接地端。 (請先閱讀背面之注意事項再填寫本頁) 請參考第3圖，下文將詳細説明傳統鐵電記億體裝置 的操作。 最重要的是在備用狀態時，施加一高準位的位元線預 充電信號BLP,使得預充電位元線BL及反相位元線BLB預 充電至接地準位。其次，當讀取儲存在晶胞中的資料時 ，施加一低準位的θ位元線預充電信號BLP，使得位元線BL 及反相位元線BL漂移。隨後，施加高準位字元線信號WLO 及高準位板線CP。此時，鐵電電容器的狀態成為第2圖之 "S 3 "狀態，且△ Q 1或A Q 2的電荷量釋入位元線B L ,以導 致位元線電壓的改變。此位元線電壓改變被感測出來， 由此感測放大器SA放大。當參考字元線信號RMLO及參考 板RCP為高準位時，從參考電壓産生器R1産生感測放大 器SA的參考電壓。 經漓部中央標準局員工消費合作社印製. 第4圖為使用一鐵電電容器之另一傳統鐵電記億體裝 置的電路圖，該鐵電電容器包括一感測放大器SA, —記 億體晶胞Ml, —參考電壓産生器R1及一預充電電路P1。 感測放大器S1感測且放大位元線BL及反相位元線BLB之 間徹小的電壓差。記億體晶胞Ml包括多傾單元記億體晶 胞，各高胞包括一切換電晶體及鐵電電容器，且儲存一 資料。參考電壓産生器R1産生一用於感測及放大的參考 電壓。預充電電路P1預充電位元線BL及反相位元線BLB 至接地準位〇感測放大器SA,記億體晶胞Ml及參考電壓 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（4 ) 産生器R1的結構與第3圖所示者相同。 預充電電路P1串聯耦合於位元線BL及反相位元線BLB 之間，且包含一低準位預充電單元BLOCKO及一高準位預 充電單元BL0CK1。低準位預充電單元BLOCKO包括兩NMOS 電晶體，對各電晶髏的閘極供應一位元線低預充電信號 BLP,而高準位預充電單元BL0CK1包括兩PMOS電晶體，. 對各電晶髅的閘極供應一位元線高預充電信號BHP。此 時，兩個NMOS的共源極耦合接地準位，且兩PMOS電晶體 的共源極镄合電源電壓準位。 在備用狀態時，將位元線低預充電信號BLP的"高準位 "及位元線高預充電信號Β Η P的高準位供應對應的低準位 預充電單元BLOCKO及高準位預充電單元BL0CK1,使得將 位元線BL及反相位元線BLB預充電至接地準位。其次， 對於晶胞中儲存資料的讀取，將位元線低預充電信號BLP 的"低準位"及位元線高預充電信號Β Η P的"低準位"供應 對應的低準位預充電單元BLOCKO及高準位預充電單元 BL0CK1,使得位元線BL及反相位元線BLB預充電至電源 電準位^在預充電後，位元線高預充電信號BHP為高 準位，使得位元線B L及反相位元線B L B呈漂浮狀態。其 次，字元線信號WL0成為"高準位、此時，鐵電電容器 CS的狀態成為第2圖之"S4”狀態，而電赭量Δβΐ或AQ2 導入位元線BL中，因此使得位元線電壓改變。由感測放 大器S Α感測且放大此位元線電壓的改變。 在上述的預充電電路中，存在一問題，JP當位元線及 -6 - I J-------Q"裝-- (請先閲讀背面之注意事項再填离本頁)Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Div. A7 * B7__ 5. Description of the Invention (,) The present invention relates to a non-volatile semiconductor memory device, especially to a memory cell including a Ferroelectric capacitors for ferroelectric capacitors. Figure 1A shows the symbol of a ferroelectric capacitor, and Figure 1B shows the relationship between the node charge and the voltage acting on it. Please refer to Section 1B_. Those skilled in the art should be familiar with capacitors using ferroelectric materials as dielectric materials. When a voltage is applied between two nodes of the capacitor, hysteresis will be generated, and due to the voltage, the charge will be accumulated. . When the voltage between the two nodes of the ferroelectric capacitor is 0 [volts], there are two states of the ferroelectric capacitor that can accumulate electricity, such as " S1 "and " S2''e. As a result, even when there is no power supply, Ferroelectric capacitors can store two-bit types of data. Due to the characteristics of ferroelectric capacitors, they can be used as non-volatile memory devices for billion-meter devices. Moreover, the voltage can be changed according to the voltage across the ferroelectric capacitor. The polarization state of a ferroelectric capacitor changes the charge stored in the ferroelectric capacitor. If an appropriate negative voltage is applied to a ferroelectric capacitor in the "S1" polarization state, the capacitor state changes with the direction of the arrow in Figure 1B. Therefore, the polarization state also changes with 。. Then, if the voltage between the two ends of the capacitor is "0" volts, its state becomes the "S2" state. When a voltage is applied across the capacitor, it is detected by The degree of change in the amount of charge generated takes the data stored in the ferroelectric capacitor. Figure 2 shows when the -VI voltage is applied across the ferroelectric capacitor and when + vi National Standard (CNS) A4 Specification (210X297 mm) I ^ ------- C3-Cloths ---- (Please read the precautions on the back before filling this page) _ A7 'B7 V. Description of the invention (>), the change of the charge state when a voltage is applied across the ferroelectric capacitor, the "S1" state of the ferroelectric capacitor is defined as the data "1", and the "ferroelectric capacitor" "S2" status is defined as data " 0 ". First, we assume that -VI voltage is applied across the ferroelectric capacitor. When the initial state of the ferroelectric capacitor is " S1 ", its state changes to " S3 " and the amount of charge changes to AQ1. Meanwhile, in the example where the initial state of the ferroelectric capacitor is "S2", its state is changed to "S4" state, and the amount of charge is changed to AQ0. This change in the amount of electric chair is a charge coupling with a bit line, which is equal to the bit line capacitor of the billion-unit cell array. Moreover, the change in the bit line potential causes the sense amplifier to operate, so a small signal generated by a small amount of charge It is enlarged and output as data. Printed by the Consumer Standards Cooperative of the Central Bureau of Standards (please read the precautions on the back before filling out this page) Figure 3 shows the circuit diagram of the traditional ferroelectric recording device using ferroelectric capacitors. SA, the ferroelectric memory device M1, the piano test voltage generator R1 and a pre-charging circuit P1. The sense amplifier SA senses and amplifies a small potential difference between the bit line B L and the out-of-phase element line B L B. The billion cell unit M1 includes a plurality of unit cells, each of which includes a switching transistor and a ferroelectric capacitor, and is used to store data. The reference voltage generator R1 generates a reference voltage required for sensing and amplification. The pre-charging circuit P1 pre-charges the bit line BL and the anti-phase element line BLB to a ground level. In the switching transistor of the billion-cell unit M1, its source is coupled to a bit line, and its gate is coupled to a word line. One end of the ferroelectric capacitor is coupled to the drain of the switching transistor, and the other end is coupled to a plate line CP to drive the ferroelectric capacitor. Therefore, the pre-charging circuit P1 forms a series coupling with the bit line BL and the anti-phase element line BLB, and contains two NMOSi transistors. The paper size of this transistor is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). ) A 7 B7 V. Description of the Invention (4) A one-bit wire precharge signal BLP is applied to the gate of the body, and its common source is connected to the ground terminal. (Please read the precautions on the back before filling this page) Please refer to Figure 3, the operation of the traditional ferroelectric memory device will be explained in detail below. The most important thing is that in the standby state, a high-level bit line precharge signal BLP is applied, so that the precharge bit line BL and the inverse phase line BLB are precharged to the ground level. Secondly, when reading the data stored in the unit cell, a low-level θ bit line precharge signal BLP is applied, so that the bit line BL and the anti-phase bit line BL drift. Subsequently, the high-level word line signal WLO and the high-level plate line CP are applied. At this time, the state of the ferroelectric capacitor becomes the "S 3" state of Fig. 2 and the amount of charge of Δ Q 1 or A Q 2 is released into the bit line B L to cause a change in the bit line voltage. This bit line voltage change is sensed, thereby being amplified by the sense amplifier SA. When the reference word line signal RMLO and the reference plate RCP are at a high level, the reference voltage of the sense amplifier SA is generated from the reference voltage generator R1. Printed by the Consumers' Cooperative of the Central Bureau of Standards. Figure 4 is a circuit diagram of another traditional ferroelectric memory device using a ferroelectric capacitor. The ferroelectric capacitor includes a sense amplifier, Cell M1, a reference voltage generator R1 and a precharge circuit P1. The sense amplifier S1 senses and amplifies a completely small voltage difference between the bit line BL and the inverse phase line BLB. The billion-unit cell M1 includes a multi-tilt unit, and each unit cell includes a switching transistor and a ferroelectric capacitor, and stores data. The reference voltage generator R1 generates a reference voltage for sensing and amplification. Pre-charging circuit P1 pre-charging bit line BL and anti-phase element line BLB to the ground level. Sense amplifier SA, remembering the unit cell Ml and reference voltage. This paper size applies Chinese National Standard (CNS) A4 specification (210X297). (Mm) A7 B7 printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (4) The structure of the generator R1 is the same as that shown in Figure 3. The precharge circuit P1 is coupled in series between the bit line BL and the anti-phase element line BLB, and includes a low level precharge unit BLOCKO and a high level precharge unit BL0CK1. The low-level pre-charging unit BLOCKO includes two NMOS transistors, and a one-bit low-pre-charging signal BLP is supplied to the gate of each transistor. The high-level pre-charging unit BL0CK1 includes two PMOS transistors. Jinglu's gate supplies a one-bit line high precharge signal BHP. At this time, the common source of the two NMOS is coupled to the ground level, and the common source of the two PMOS transistors is combined with the power supply voltage level. In the standby state, the high level of the bit line low precharge signal BLP and the high level of the bit line high precharge signal B Η P are supplied to the corresponding low level precharge unit BLOCKO and Micro Motion The bit pre-charging unit BL0CK1 pre-charges the bit line BL and the anti-phase element line BLB to the ground level. Secondly, for reading the data stored in the cell, the "low level" of the bit line low precharge signal BLP and the "low level" of the bit line high precharge signal B Η P are supplied correspondingly. The low-level pre-charging unit BLOCKO and the high-level pre-charging unit BL0CK1 make the bit line BL and the anti-phase element line BLB pre-charge to the power level. After the pre-charging, the bit line high pre-charge signal BHP It is a high level, so that the bit line BL and the anti-phase element line BLB are in a floating state. Secondly, the word line signal WL0 becomes "high level". At this time, the state of the ferroelectric capacitor CS becomes "S4" state shown in FIG. The bit line voltage is changed. The change in the bit line voltage is sensed and amplified by the sense amplifier SA. In the above precharge circuit, there is a problem. JP is the bit line and -6-I J --- ---- Q " equipment-(Please read the notes on the back before filling out this page)
、tT 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（r ) 反相位元線預充電至接地準位或電源電壓準位時，導入 接地準位的位元線電位需放大至電源電壓準位或者是導 入電源電壓準位的位元線電位須放大至接地準位，此將 導致更多的功率耗損。另外，當放大時，在位元線及反 相位元線之間産生的電壓差減少，像因戚獼放大器之電 晶體的閘極電容器網合之故，此會導致放大程度減少的 問題。 發明抹 本發明僳提出以克服上述問題，本發明的目的在於提 供一種鐵電記億體裝置，其中當對位元線上産生的小信 號放大時，此鐵電記億體裝置可減少一感测放大器的電 流耗損，而且也可以經由感潮放大器的閘極電容，而減 少耦合效應，因此改進了放大能力。 為了逹成上述目的，本發明提供一種鐵電記億髅裝置 ，此鐵電記億僵裝置包括用於感測且放大一位元線及一 反相位元線之間之準位差的感測放大器；多傾記憶體晶 胞，各晶胞包括至少一切換電晶髏及至少一鐵電電容器 ;及一參考電壓産生裝置，用於産生威測及放大時所使 用的參考電壓；一 1/2電源電壓産生裝置，用於接收一 電源電壓，且然後産生一 1/2電源霄壓；一預充電電路， 用於預充電位元線及反相位元線至從該1/2電源電壓産 生單元所産生的1/2電源電壓，以回應一位元線控制信 號。 忒夕簡塱銳Bfl (祷先閱讀背面之注意事項再填寫本貢) •本紙乐尺度速用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印繁 A7 B7 五、發明説明U ) 為了使讀者更進一步了解本發明，本發明可參閲下文 中的說明，並請參考附圖，其中： 第1A圖表示鐵電電容器的符號，且第1B圖說明鐵電 電容器之節點A與B之間的關像； 第2圖示鐵電電容器之磁滯效應； 第3圖為傳統使用鐵電電容器之鐵電記億體裝置的電 路圖； 第4圖為使用一鐵電電容器之另一鐵電記億體裝置之 電路圖； 第5琴為根據本發明之一實施例，使用一鐵電電容器 之鐵電記憶體裝置的電路圖； 第6 _為根據本發明之一實施例之時序画，用於説明 根據本發明之一實施例之鐵電記億體裝置的讀取操作； 第7A画顯示包含一電晶體及一電容器的單元記憶體晶 胞； 第7B圖為一模型圖，用於說明從第7A圖之單元記億體 晶胞之儲存節點向基體流動的漏電流； 第8A圖為根據本發明之另一實施例的鐵電記億體裝置 之電路圖，其可防止儲存節點的電位減少； 第8 B圖為根據本發明之g —實施例之第8A圔中之鐵電 記億體裝置中信號的時序圖； 第9圖為本發明另一實施例之鐵電記億體裝置的電路 圖，其可防止儲存節點之電位的減少；以及 第10圖為本發明另一實施例之電路圖，其使用一鐵電 一 8 - 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ：297公釐） —--------C3"裝------訂-----·-線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（？） 電容器。 链明夕註钿說明 此將於下文中説明本發明，閲讀時並請參考附圖。 第5圖為本發明實施例之鐵電記億體裝置的電路圖， 該裝置使用鐵電電容器且包含一感測放大器S A，一記億 體晶胞Ml, —板驅動器F1, —參考電壓産生器R1及一預 充電電路P U感測放大器S AiS測旦放大位元線B L及反相 位元線B I, B之間微小的電壓差，記億體晶胞Μ 1包含多個 簞元記億體晶胞，各單元包含一切換電晶體及一鐵電電 容器，其儲存一資料。該板驅動器F1驅動板線PL而參考 電壓産生器R1産生用於感測及放大的參考電壓。預充電 電_路Ρ1預充電位元飨BL及凌相位元線BLB至1/2電源電壓 準位，以回應位元線預充電信號B LP。 預充電電路Ρ1耦合於位元線BL及反相位元線BLB之間 ，且包括兩値NMOS電晶體，對各電晶體的閘極位元線施 加預充電信號BLP,且共同源極耦合1/2電源電壓準位。 第6圖之信號圖用於説明本發明實施例中第5圖鐵電 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 第 明 說 文 下 圓 6 第 考 參 請 ο 作 操 取 讓 的 置 C 裝作 體操 憶.的 記·圖 „ 及 位BL 準線 高元 1 位 電 充 BL預 號又 信此 ft f 充通 預導 線N2 元及 位N1 , 體 中晶 態電 狀0S 用NM 備兩 在得 使 為 成 維後 也料 壓資 1 JJ 驾 UU. 的取 P1讀 線環 板循 0 一 位前 準在 壓果 電如 源 0 電位 2 / 準1 0 元源 78 位2m 的1/ 相在 反持 電 之 點 節 N S 的 中 環 循 在 現 在 且 作 動 應 回 線 元 字 I 如 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經满部中央標準局員工消費合作社印繁 A7 B7五、發明説明（^ ) 位為1/2電源電壓準位，則因為鐵電電容器兩端的電壓 差為Η Ο V ",所以鐵電電容器C 1的狀態為第2圖之"S 1 "狀 態或"S 2 "狀態。 為了將晶胞中儲存的資料讀至晶Η外銷，施加列位址 信號且然後由列解碼器解碼以選擇字元線。此時，為了 偵測儲存在晶胞中的電荷量，在選擇字元線之前，位元 線BL及反向位元線BLB應在漂浮狀態，而仍維持在1/2電 源電壓。為了執行此操作，位元線預充電信號B L Ρ應為 低準位。經由位元線預充電信號B L Ρ的低準位，電晶體Ν 1 及Ν 2關斷，使得位元線B L及反向位元線B L Β為漂浮狀態。 然後，選擇至外部作用的列位址之對應字元線，且字元 線的電壓增至3/2電源電壓準位。如果選擇字元線，記 億體晶胞中的切換電晶體導通。而且，如果驅動板線PL 的話，則儲存的晶胞中的電荷量將移轉到位元線中。 為了讀取儲存在鐵電電容器C1中儲存之資訊，應選擇 字元線WLO。另外，為了讀取儲存在鐵電電容器C2中的資 訊，應選擇字元線1。如果選擇字元線WLO,則切換電 晶體S T 1導通，而如果選擇字元線W L 1 ,則切換電晶體S T 2 導通。當增強字元線，則由板驅動器F1同時驅動板線PL 至3 / 2電源電壓準位，使得在選擇的晶胞電容器及位元 線電容之間達到電綺耦合，因此導致位元線電位改變。 此時，由上述方法驅動參考電壓産生單元R1，因此産生 一參考電壓。如果基於位址選擇字元線WLO，則選擇參 考電騰産生單元R 1的參考字元線兄》11〇,使得可由感測放 -1 0 - (讀先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五 經濟部中央標準局員工消費合作社印製 、發明説明（夕 大器S1執行感測及放大，該感測放大器耦合位元線^及 反向的位元線BLB。在反向位元線BLB上由參考電壓産生 單元R1鹿生的參考電壓為位元線準位之間的中間準位， 該位元線位準僳當從鐵電記億體裝置中讀取對應的資料 ” 1 "及” 0 "時，在對應的位元線上産生的準位。另外，在 位元線電壓産生後，驅動板線PL使得在位元線BL及反向位元線 B L B之間耦合感测放大器，以放大發展之電检間的差值， 以辨識如一二進位資料，且因此送至輸出節點。 同時，第7 A圖顯示一單元記億體晶胞，此單元記億體 晶胞包括一切換電晶體ST1及一鐵電電容器C1,其中多 脑單元記億體晶胞架構出第5圓的記億體晶胞Η 1。 在備用狀態期間，當板線PL維持在1/2電源電壓位 準時，電容器C1的相對節點SN應為1/2電源電壓準位， 以使得鐵電電容器C 1可停留在第2圖的"S 1 Η或"S 2 "狀態 。在完成讀取後，位元線預充電信號BLP的電位成為高 ’準位，使得位元線BL及反相位元線BLB的電位為1/2電源 電壓位準。如果隨後字元線不動作，則甚至在字元線不 動作後，SN節點仍維持在1/2電源電壓準位。但是，如 第7Β圖中的例子，有一漏電流從SN節點流向基體，使得 SN節點的電位逐漸^少，且鐵電電容器C1無法維持在備 用狀態的狀態"S 1 "或狀態"S 2 ”，而是在狀態，，S 3 "。 為了防止漏電流，可如第8A圖架構本發明的輸出緩衝 鞀，其更進一步包含用於接收控制信號的解碼器D1，以 接收控制信號REF，且解碼位址，因此可在預定的間隔 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —；---；-----〇 裝— (請先閲讀背面之注意事項再填寫本頁) 、-'° 經濟部中央標準局員工消費合作社印聚 A7 B7 五、發明説明（、。） 中插入字元線。 第8A圖為本發明實施例之鐵電記憶體裝置的電路圖， 其可防止儲存節點中電位減少，第8B圖表示第8 A圖中鐵 電記億體裝置的信號圖。 如第8B画所示，在備用狀態中，在預定的間隔中動作 控制信號R E F，以依序導通晶胞的字元線，使得S N節點 的電位可由預充電至1/2電源電壓準位的位元線持績維 持如1 / 2電源電壓準位中。 第9圔為本發明另一實施例的鐵電記億體裝置，其可 防ihSN節點的漏電流。此鐵電記億體裝置更包含一 NMOS 電晶體N 1，此電晶體耦合於S N節點及1 / 2電源電壓之間， 且接收流過其閘極的控制信號S N D。其中，在備用狀態 中，控制信號S H D成為"高準位”以預充電S N節點至1 / 2， 且當開始讀取操作時，成為"低準位"，由於可防止漏電 流而使得在備用狀態的電位減少。 第1〇_為本發明另一實施例之鐵電記億體裝置的電路 圖，其使用一鐵電電容器。此鐵電記億體裝置更包含一 第一方塊10及一第二方塊2D。第一方塊10將從參考電壓 産生單元R1中産生的參考電壓視需要向位元線BL或反相 位元線B L B傳送，且第二方塊2 0接收感測放大器S 1的輪 出，然後傳送予輸出節點。在第一方塊10中，從參考電 壓産生單元R1産生的參考電壓視需要依據第一控制倍號 RV0及第二控制信號RV2向位元線BL及反相位元線BLB傳 送。如果儲存在鐵電電容器C1中的資訊需要讀取時，控 -1 2 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297公釐） —.---^----0种衣------1T------J (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（11 ) 制信號R V 0為”高準位"，因此將參考電壓向反相位元線 BLB傳送。另外，如果儲存在鐵電電容器C2中的資訊謓 取時，控制信號R V 1為”高準位"，因此將參考電壓向位 元線BL傳送。 如上所述，本發明的效應為可由將位元線預充電至使 用鐵電電容器之半導體記億體裝置之1/2電源電壓準位 而減少感測放大器的電源耗損，且可改進_測放大器的 放大能力。 另外，可由防止在備用狀態中SN節點的漏電流，對於 儲存在鐵電電容器中的資料，可以更穩定的方式讀取。 上文已説明本發明之較佳實施例，熟習本技術者可對 上述實施例進行多種不同的更換，修飾。因此，上述的 説明並不用於限制本發明，本發明傺由下文的申請專利 範圍所界定。 ---. II (請先閲讀背面之注意事項再填寫本頁) 、-° 經漓部中央標率局負工消費合作社印製 -13- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標率局貝工消費合作社印繁 A7 B7五、發明説明（p ) 參考符號說明 BL.....位元線 B L B ....反相位元線 C 1，C 2 ·.…鐵電電容器 D 1.....字元線解碼器 F1.....板驅動器 Ml.....記憶體晶胞 P 1.....預充電電路 R1.....參考電壓産生器 SA.....感測放大器 I -.-------Q衣 I - (請先閱讀背面之注意事項再填寫本頁), TT This paper size applies to Chinese National Standards (CNS) A4 specifications (2 丨 0 X 297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (r) Reverse phase element wires are precharged to When the ground level or the power supply voltage level, the potential of the bit line introduced into the ground level needs to be amplified to the power supply voltage level or the potential of the bit line introduced to the power supply voltage level must be amplified to the ground level, which will cause more Power consumption. In addition, when amplifying, the voltage difference generated between the bit line and the inverse phase line is reduced, such as the gate capacitor network of the transistor of the chi-amp amplifier is connected, which will cause the problem of reducing the degree of amplification. The present invention is proposed to overcome the above problems. The object of the present invention is to provide a ferroelectric memory device, wherein when the small signal generated on the bit line is amplified, the ferroelectric memory device can reduce a sensing The current consumption of the amplifier can also be reduced through the gate capacitance of the tide amplifier, thereby reducing the coupling effect, thereby improving the amplification capability. In order to achieve the above-mentioned object, the present invention provides a ferroelectric recording device, the ferroelectric recording device includes a sensor for sensing and amplifying the level difference between a bit line and an out-of-phase line. Measuring amplifier; multi-tilt memory unit cells, each unit cell including at least one switching transistor and at least one ferroelectric capacitor; and a reference voltage generating device for generating a reference voltage used for power measurement and amplification; 1 / 2 power supply voltage generating device for receiving a power supply voltage and then generating a 1/2 power supply voltage; a pre-charging circuit for pre-charging bit lines and anti-phase element lines from the 1/2 power supply The 1/2 power supply voltage generated by the voltage generating unit is in response to a bit line control signal.忒 Xi Jian Jian Rui Bfl (please read the notes on the back before filling in this tribute) • The paper scale is quickly used Chinese National Standards (CNS) A4 specifications (210X297 mm) Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economy Yinfan A7 B7 5. Description of the invention U) In order for the reader to further understand the present invention, the present invention may refer to the following description and refer to the accompanying drawings, wherein: FIG. 1A shows the symbol of the ferroelectric capacitor, and FIG. 1B illustrates the ferroelectric capacitor Image between nodes A and B; Figure 2 shows the hysteresis effect of a ferroelectric capacitor; Figure 3 is a circuit diagram of a traditional ferroelectric memory device using a ferroelectric capacitor; Figure 4 is a ferroelectric capacitor Another circuit diagram of another ferroelectric memory device; The fifth piano is a circuit diagram of a ferroelectric memory device using a ferroelectric capacitor according to an embodiment of the present invention; and the sixth is a circuit diagram according to an embodiment of the present invention. Timing picture for explaining the reading operation of a ferroelectric memory device according to an embodiment of the present invention; FIG. 7A shows a unit memory cell including a transistor and a capacitor; FIG. 7B is a model It is used to explain the leakage current flowing from the storage node of the unit memory cell of FIG. 7A to the substrate; FIG. 8A is a circuit diagram of the ferroelectric memory device according to another embodiment of the present invention, which can prevent The potential of the storage node is reduced; FIG. 8B is a timing diagram of signals in the ferroelectric memory device according to g of the present invention—the 8A of the embodiment; FIG. 9 is a ferroelectric device according to another embodiment of the present invention The circuit diagram of the billion-body device, which can prevent the reduction of the potential of the storage node; and Fig. 10 is a circuit diagram of another embodiment of the present invention, which uses a ferroelectric 8-This paper size applies to Chinese National Standard (CNS) A4 Specifications (21〇 ×: 297 mm) —-------- C3 " installation ------ order ----- · -line (please read the precautions on the back before filling this page) A7 B7 5. Description of the invention (?) Capacitor.明明 夕 Note Description This invention will be described below, please refer to the drawings when reading. FIG. 5 is a circuit diagram of a ferroelectric memory device according to an embodiment of the present invention. The device uses a ferroelectric capacitor and includes a sense amplifier SA, a billion body cell M1, —board driver F1, —reference voltage generator. R1 and a pre-charging circuit PU sense amplifier S AiS measure the small voltage difference between the amplified bit line BL and the anti-phase element lines BI, B. It is recorded that the unit cell M 1 contains multiple units. The unit cell includes a switching transistor and a ferroelectric capacitor, which stores data. The board driver F1 drives the board line PL and the reference voltage generator R1 generates a reference voltage for sensing and amplification. The pre-charging circuit P1 precharges the bit 飨 BL and the phase element line BLB to 1/2 the power supply voltage level in response to the bit line precharge signal B LP. The precharge circuit P1 is coupled between the bit line BL and the anti-phase element line BLB, and includes two NMOS transistors. A precharge signal BLP is applied to the gate bit line of each transistor, and a common source coupling 1 / 2 supply voltage level. The signal diagram in Fig. 6 is used to explain the ferroelectricity in Fig. 5 in the embodiment of the present invention (please read the precautions on the back before filling this page). Printed by the Central Standards Bureau of the Ministry of Economic Affairs. For the test, please make a note of C and pretend to be a gymnastic memory. Notes and diagrams, and the BL level, the high level, the 1-digit electric charger, the BL number, and the ft f, the pre-wire N2, and the bit N1, The crystalline state of the body in the body is 0S. NM is used to prepare two. It is also expected to cost 1 JJ after driving UU. Take P1 to read the wire ring plate and follow it. Quasi 10 Yuan source 78 digits 2m 1 / phase at the point of anti-holding point NS in the central loop is now and should be returned to the line meta character I as 9 This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 mm ) A7 B7 printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the People ’s Republic of China. 5. The description of the invention (^) is 1/2 the power supply voltage level, because the voltage difference across the ferroelectric capacitor is Η Ο V " The state of capacitor C 1 is the " S 1 " state or " S 2 " State. In order to read the data stored in the cell to the crystal pin for export, a column address signal is applied and then decoded by the column decoder to select the word line. At this time, in order to detect the charge stored in the cell Before the word line is selected, the bit line BL and the inverted bit line BLB should be in a floating state and still maintained at 1/2 the power supply voltage. In order to perform this operation, the bit line precharge signal BL P should be Low level. Via the low level of the bit line precharge signal BL P, the transistors N 1 and N 2 are turned off, so that the bit line BL and the inverted bit line BL Β are in a floating state. Then, select to the outside The corresponding word line of the active column address, and the voltage of the word line is increased to the 3/2 power supply voltage level. If the word line is selected, the switching transistor in the billion cell is turned on. Moreover, if the driver board With the line PL, the amount of charge stored in the unit cell is transferred to the bit line. In order to read the information stored in the ferroelectric capacitor C1, the word line WLO should be selected. In addition, in order to read the information stored in the iron For the information in capacitor C2, select word line 1. If you select word Line WLO, the switching transistor ST 1 is turned on, and if the word line WL 1 is selected, the switching transistor ST 2 is turned on. When the word line is enhanced, the board driver F1 simultaneously drives the board line PL to 3/2 power supply voltage The level leads to an electrical coupling between the selected cell capacitor and the bit line capacitance, thus causing the potential of the bit line to change. At this time, the reference voltage generating unit R1 is driven by the above method, so a reference voltage is generated. If the word line WLO is selected based on the address, the reference word line brother "11" of the reference electric generation unit R 1 is selected, so that the sensor can be placed -1 0-(Read the precautions on the back before filling this page ) This paper size applies to Chinese National Standard (CNS) A4 specifications (210X297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed and invented (Xidaqi S1 performs sensing and amplification, the sensing amplifier is coupled The bit line ^ and the inverted bit line BLB. The reference voltage generated by the reference voltage generating unit R1 on the inverted bit line BLB is the intermediate level between the bit line levels. When reading the corresponding data "1" and "0" from the ferroelectric memory device, the level generated on the corresponding bit line. In addition, after the bit line voltage is generated, the board is driven. The line PL enables a sense amplifier to be coupled between the bit line BL and the inverse bit line BLB to amplify the difference between the developed electrical detections to identify data such as binary data, and therefore send it to the output node. At the same time, Figure 7A shows a unit of billions of cells. This unit The billion body cell includes a switching transistor ST1 and a ferroelectric capacitor C1, in which the multi-brain unit records the billion body cell to form the fifth round of the billion body cell Η 1. During the standby state, when the board line PL is maintained At the 1/2 power supply voltage level, the relative node SN of the capacitor C1 should be at the 1/2 power supply voltage level, so that the ferroelectric capacitor C 1 can stay at "S 1" or "S 2" in FIG. 2 Status. After the reading is completed, the potential of the bit line precharge signal BLP becomes the high level, so that the potentials of the bit line BL and the anti-phase element line BLB are 1/2 the power supply voltage level. The element line does not operate, and even after the character line does not operate, the SN node remains at the 1/2 power supply voltage level. However, as in the example in Figure 7B, a leakage current flows from the SN node to the base, making the SN node The potential of the capacitor is gradually reduced, and the ferroelectric capacitor C1 cannot maintain the state "S 1" or "S 2" in the standby state. Instead, it is in the state "S 3". In order to prevent leakage current, such as FIG. 8A illustrates an output buffer frame according to the present invention, which further includes a signal for receiving a control signal. The decoder D1 receives the control signal REF and decodes the address, so the paper size can be applied to the Chinese National Standard (CNS) A4 specification (210X297 mm) at predetermined intervals —; ---; ----- 〇 Equipment-(Please read the precautions on the back before filling this page),-'° Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Insert the character line in the description of the invention (,.) Figure 8A is for this The circuit diagram of the ferroelectric memory device according to the embodiment of the invention can prevent the potential in the storage node from decreasing. FIG. 8B shows the signal diagram of the ferroelectric memory device in FIG. 8A. As shown in FIG. 8B, in the standby state, the control signal REF is actuated at predetermined intervals to sequentially turn on the word lines of the cell, so that the potential of the SN node can be precharged to a level of 1/2 the power supply voltage. The bit line performance is maintained at the 1/2 power supply level. The ninth aspect is a ferroelectric memory device according to another embodiment of the present invention, which can prevent the leakage current of the ihSN node. The ferroelectric memory device further includes an NMOS transistor N 1, which is coupled between the S N node and the 1/2 power supply voltage, and receives a control signal S N D flowing through its gate. Among them, in the standby state, the control signal SHD becomes " high level " to precharge the SN node to 1/2, and becomes " low level " when the read operation is started, because it can prevent leakage current and The potential in the standby state is reduced. # 10_ is a circuit diagram of a ferroelectric memory device according to another embodiment of the present invention, which uses a ferroelectric capacitor. The ferroelectric memory device includes a first block 10 And a second block 2D. The first block 10 transmits the reference voltage generated from the reference voltage generating unit R1 to the bit line BL or the inverse phase line BLB as needed, and the second block 20 receives the sense amplifier S 1 is rotated out, and then transmitted to the output node. In the first block 10, the reference voltage generated from the reference voltage generating unit R1 is applied to the bit line BL and the reverse direction according to the first control multiple RV0 and the second control signal RV2 as needed. Phase element line BLB transmission. If the information stored in the ferroelectric capacitor C1 needs to be read, control -1 2-This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) —.--- ^ ---- 0 kinds of clothing ------ 1T ------ J (Please read first Note again fill the back of the page) A7 B7 V. description of the invention (11) is manufactured by the signal R V 0 '", the high level reference voltage thus transferred to the inverted bit line BLB. In addition, if the information stored in the ferroelectric capacitor C2 is retrieved, the control signal RV 1 is "high level", so the reference voltage is transmitted to the bit line BL. As described above, the effect of the present invention is that the The bit line is pre-charged to 1/2 the power supply voltage level of the semiconductor memory device using a ferroelectric capacitor to reduce the power consumption of the sense amplifier and improve the amplifier's amplification capability. In addition, it can be prevented from being in a standby state The leakage current of the middle SN node can read the data stored in the ferroelectric capacitor in a more stable manner. The preferred embodiment of the present invention has been described above. Those skilled in the art can perform a variety of different implementations on the above embodiment. Replace, modify. Therefore, the above description is not intended to limit the present invention. The present invention is defined by the scope of patent applications below. ---. II (Please read the precautions on the back before filling this page),-° Printed by the Labor Standards Cooperative of the Central Standards Bureau of the Ministry of Liability -13- This paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm). Yinfan A7 B7 V. Description of the invention (p) Reference symbol description BL ..... Bit line BLB .... Inverse phase element line C 1, C 2 · ... Ferroelectric capacitor D 1 .... .Word line decoder F1 ..... board driver Ml ..... memory cell P 1 ..... pre-charge circuit R1 ..... reference voltage generator SA ..... Sense Amplifier I -.------- Q Clothing I-(Please read the precautions on the back before filling this page)
、1T -14- 本紙張尺度適用中國國家標牟（CNS ) Α4規格（210Χ 297公釐）、 1T -14- This paper size applies to China National Standards (CNS) A4 specifications (210 × 297 mm)