594733 A7 B7_ 五、發明說明（/ ) 本發明傺關於具有位元線、字元線及陽極線之積體記 憶體及對應此記億體之操作方法。 由 H. Fujisawa等所著，發表於 IEEE Journal of Solid-State circuits， Vol.32， Νο·5， May 1997，第 655頁中 之文章"The Charge-Share Modified (CSM) Precharge-Level Architecture for High-Speed and Low-Power Ferroelectric Memory’’描述了 FeARM 或 FRA M型之鐵電記 億體。這些記億體以類似於DRAM之方式建構，但是其記 億體單元具有含有鐵電介電之儲存電容器。億體單元排 列在字元線及位元線之交叉點上。儲存電容器之一電極 偽連接於固定陽極板電位。固定之陽極板電位偽在FR AM 之兩個供應電位中間。相較於FR AM ,其中陽極電位並不 是常數，而是脈衝化（即所諝，"脈衝化陽極概念〃） ，恆定陽極電位之觀念，如參考文獻所述，通常被稱 為〃 V D D / 2概念〃。. 已知FR AM之1個電晶體/ 1値電容器記億體單元藉由 儲存電容器之鐵電介電之對應之不同極化而儲存不同邏 輯狀態。假使，選擇電晶體傺在開啓狀態，在儲存電容 器之電極偽在相同的電位上，即電壓Q傺跨橫在儲存電 容器之上，則極化並不受影響，因此記億體單元之儲存 邏輯狀態亦不受影響。例如，為了能自複數個記億體單 元選擇一記億體單元，該複數個記億體單元像連接到相 同字元線，其記億體單元僳接受讀取接達，上述文章給 予除了選擇字元線外之所有字元線如何預充電至恆定陽 極電位之描述。假使未選擇之字元線偽經由記憶體單元 - 3 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ——V-------丨_-裝—— (請先閱讀背面之注意事項再填寫本頁) · 經濟部智慧財產局員工消費合作社印製 ^4733 A7 ----B7 五、發明說明（> ) 之選擇電晶體連接到儲存電容器之電極，則在儲存電容 器中之電極具有陽極電位，且儲存內容並不受影響。然 而，選擇位元線，係帶到與陽極電位偏離之電位，結果 連接到該位元線之記憶體單元之儲存電容器之橫跨電壓 下降。結果造成該儲存電容器及所選擇之位元線之間之 電荷平衡，藉由此事，所選擇位元線之電位係根據儲存 電容器之極化狀態而有不同之影響。感測放大器放大以 此讀取之邏輯資訊。 然而，在寫入連達至所描述之記憶體中，那些不被接 達之記憶體單元之位元線係維持在陽極電位。在另一方 面，所選擇位元線之電位，其記憶體單元係被寫入，係 由感測放大器帶到對應之寫入電位，該寫入電位與陽極 電位不同。所選擇之位元線係放電至接地，例如，寫入 邏輯〇，而對寫入邏輯1係帶到正供應電位之値。 在特定的應用中，例如在測試模式中，需要寫入相同 的資訊至大量的記憶體單元。一簡單的記憶體測試可提 供，例如，一邏輯1寫入至所有的記憶體單元，且於後 再讀出。 爲了在上述文章所描述之記憶體上實施一測試，需要 連續寫入至所有的記憶體單元，因爲衹有一個字元線及 一個位元線，以至於一個在交叉點上之記憶體單元可以 同時被選取。 本發明係根據下列目的：明確化一積體記憶體，其中 相同之邏輯資訊以一簡單方式同時寫入至複數個記憶體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --ill· — — — ^ «—— — — — —— I , 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 594733 A7 B7 五、發明說明（令） 單元。 本發明之達成係藉由根據申請專利範圍第1項之積體 記憶體，及根據申請專利範圍第8項之積體記憶體之操 作方法。依附之申請專利範圍係關於有利的設計及本發 明之發展。 根據本發明之積體記憶體具有一第一操作模式及一第 二操作模式，在第一操作模式中’陽極線具有一恆定陽 極電位，而位元線亦具有陽極電位，但前提是沒有接達 至記憶體單元中之任一個，若是寫入接達至記憶體單元 中之一個，連接到該記憶體單元之字元線具有第一電 位，以寫入第一邏輯狀態，該第一電位較陽極電位爲小， 及一第二電位以寫入第二邏輯狀態，該第二電位較陽極 電位大，因此，在第二操作模式中，位元線具有陽極電 位，而在寫入接達時，至少有一陽極線具有特定之電位， 其與陽極電位不同。 因此，雖然根據本發明之記憶體具有第一操作模式， 如已知之FRAM及上述之H. Fujisawa所寫之文章，換言 之，寫入接達至記億體單元，係藉由位元線之電位改變 而達成，在第二操作模式中，資訊寫入並不是藉由改變 位元線之電位，而是藉由改變陽極線之電位來達成，這 意味著在第一操作模式中，根據本發明之記憶體之作業 如同傳統之記憶體，其係根據VDD/2槪念來操作，然而 在第二操作模式中，欲被寫入之儲存電容器之電極係連 接到陽極線，不再連接到恆定陽極電位，而是連接到偏 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公董） ----丨丨！ ！ ^裝！ ρί 丨訂·---I-- (請先閱讀背面之注音？事項再填寫本頁) 594733 經濟部智慧財產局員/工消費合作社印製 A7 B7 五、發明說明（a ) 移之特定電位，在第一操作模式中，橫跨用來寫入新邏 輯資訊項目至記憶體單元之儲存電容器之電壓係由各個 位元線之電位改變來產生，而陽極線之電位則保持恆 定；在另一方面，在第二操作模式中，橫跨·儲存電容器 所需之寫入電壓係由保持位元線之電位恆定，及藉由對 應陽極線之電位改變至偏離恆定陽極電位之値來產生。 根據本發明之記憶體具有下列好處，即允許以一簡單 方式使相同資訊同時寫入複數個記憶體單元。這是對所 有記憶體單元同時達成，其相關之陽極線具有偏離陽極 電位之特定電位。在極端的情況下，記憶體之所有陽極 線可以同時設定特定電位，而使得相同的邏輯資訊被同 時寫入至所有記憶體單元。 可以使陽極線成爲連續性之單元陽極之一部份，因此 形成一連續性區域。對此單元陽極之電位之改變使得儲 存電容器之所有陽極線及連接其上之電極同時帶到改變 之電位。 根據發展，特定電位係第一或第二電位，位元線在第 一操作模式之寫入接達時係設定成此特定電位。假使特 定電位等於第一電位時，第二邏輯狀態係在第二操作模 式中之寫入接達狀況下寫入至對應之記憶體單元。假使 特定電位等於第二電位，第一邏輯狀態係寫入至對應之 記憶體單元。 根據另一發展，特定電位係在陽極電位及第一或第二 電位之間。結果第一及/或第二邏輯狀態並未以滿位準 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---Γ----- I · I ---：---- 訂·！ II ---- (請先閱讀背面之注意事項再填寫本頁) 594733 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（r ) 寫入至對應之記憶體單元’而是以衰減之位準°以此方 式，能有利地模擬記憶體單元之老化，結果儲存在記憶 體單元之信號係相似地被衰減。藉由邏輯狀態之老化模 擬，（邏輯狀態並未以滿信號位準寫入）有利地使一連續 測試所需之時間縮短。這是由於〃衰減〃位元已經被寫 入記憶體單元，其〃衰減〃位元，（在傳續記憶體內’寫 入係以滿信號位準來作用）。衹在爲了漏電流之長時間後 才可獲得。 根據一發展，積體記憶體具有一終端區域’用於自記 憶體外饋入特定電位。這具有特定電位之値可以依需要 而被選擇且可在記憶體作業期間被改變之益處。 根據本發明之一發展，記億體具有字元線驅動器’其 連接字元線解碼器之輸出至字元線之一，以及一電壓產 生器，用於在第一操作模式中產生對於字元線驅動器之 第一供應電壓。再者，記憶體具有終端區域，用於在第 二操作模式中對字元線驅動器饋入第二供應電壓。這具 有下列益處：即第二供應電壓可以依需要被選擇且與第 一供應電壓無關。 根據本發明之操作方法之一實施例提供較第一供應電 壓小之第二供應電壓。這減少了在第二操作模式中之記 憶體之電能耗費，這是與下列情形比較，其中字元線驅 動器係亦在第二操作模式中被供應以較高之第一供應電 壓。除了藉由一接觸區而饋入之方法，第二供應電壓亦 可在積體記憶體中產生。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----1------11 —^—--訂--------1 (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 594733 A7 B7_ 五、發明說明（^ ) 根據操作方法之發展，第二供應電壓係被選擇使得當 一字元線被相關之字元線驅動器啓動時，字元線之電位 較陽極電位加記憶體單元之選擇電晶體之臨界電壓高， 但較第一供應電壓低。在第一操作模式中，當兩個邏輯 狀態之一被寫入，選擇電晶體必須自一位元線傳送一電 位至對應之儲存電容器，其係較陽極電位高（這是邏輯1 被寫入時之一般狀況）。因此，爲了啓動選擇電晶體，字 元線必須被帶到一電位，其係較位元線之最高電位加上 選擇電晶體之臨界電壓還高。第一供應電壓必須被選擇 使之與第一操作模式一般高。因爲在第二操作模式中， 位元線之電位係恆定並且等於陽極電位，假使至少等於 陽極電位加上選擇電晶體之臨界電壓之電位經過字元線 而存在於相關選擇電晶體時，則位元線電位被傳送到儲 存電容器之對應電極而無任何損失。 根據操作方法之另一實施例，第二供應電壓係被選 擇，使得當一字元線被相關之字元線驅動器啓動時，字 元線之電位係低於或等於陽極電位加上記憶體單元之選 擇電晶體之臨界電壓。結果是，在第二操作模式中，在 開啓狀態之選擇電晶體並不傳送至對應儲存電容器滿陽 極電位，其乃是位元線所在之電位，但是傳送一較低之 電位。以此方式達到的是··在第二操作模式中，資料並 不是以滿信號位準而是以一 〃衰減〃之.信號位準寫入記 憶體單元。 根據積體記憶體之一發展，在第一操作模式中，在寫 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------I I —Aw · I---r I I I I I I I I--- (請先閱讀背面之注咅？事項再填寫本頁) 594733 A7 B7 五、發明說明（ 同之 被達 線接 元入 字寫 一 在 之， 中中 列式 陣模 元作 單操 一二 在第 有在 抵 ， ，面 中方 件一 事另 之 〇 逹動 接啓 入時 C憶 動記 啓的 時有 同所 被對 線， 元中 字式 一 模 過作 超操 之二 列第 陣在 元： 單是 個的 一 到 每達 ，式 中方 件此 事以 連 像 元 單 體 億 記 的 有 所 而 5 ο 達一 接之 入線 寫元 之字 時之 同動 成啓 達時 元同 單，到 體接 明 說0 簡 式 圖 細之 詳線 更元 而字 例之 施動 實啓 性時 表同 代到 之接 繪連 描條 所元 中單 式中 圖其 用 ， 利文 傺下 ffu ΛΖ 發逑 本描 地 積 之 明 發 本 據 根第 示示 顯顯 圖圖 1X οώ 第第 例 施 實 之 體 億 元 單 體 億 記 體之 體 億 記 之 圖 33 驅 之 體 億 記 之 圖 1Χ 第 動 0 8 於 用 路 電 一 示 顯·， 31線 第元 字 及 以 圖 細 詳 之 器 碼 解 線 元 字 之 圖 3 第 示 顯 圔 4 第 明 說0 詳 之 明 發 詳 之 體 億 記 體 積 之 型 Μ Α R F 之 明 發 本 據 昆 示 顯 圖 1X 第 單 體 億i 己 L A.1I0P 中線 其極 ，陽 列及 塞 k 陣 L 元 單 體 億 記K 有B.L 具線 體元 億位\ 記在。 此列上 」kl— r5. O ® 點 料傺叉 資Me交 細元之 線 元 字 (請先閱讀背面之注意事項再填寫本頁) 裝 -I ϋ ϋ 一：OJa ϋ ϋ ϋ «1 I ϋ ·, 經濟部智慧財產局員工消費合作社印製 晶 第電 擇器 之 之 C Μ 元 單 體 億 記 之 圖 1Χ 第 示 顯 圖 其 ο C 器 容1, 電PL 存一 儲之 之線 電極 介陽 電到 鐵接 有連 含傺 及極 Τ電 體 另 而 經 選容則 一 電極 有存電 具儲一 隱 晶 電 擇 選第 由 進 更 圖 接 連BL 徑線 路元 制位 控示 可顯 之步 之 線 元 位 到 體 晶 電 道 通 I η 由 經 像 *連 體 S 器 器生 大産 放壓 測電 _到 一 接 到連 ?- 接 線 元 位 出 411 之 電電 道極 通陽 Ρ'-定 由恆 經生 像産 L 其 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 594733 A7 B7 _ 五、發明說明（彳） 位VPL。η-通道電晶體N及p-通道電晶體P (每一個皆 指派到相同之位元線BLi )之每一個係連接到行選擇線 CSLi。 陽極線PLi係在單元陣列之邊緣互相連接。他們係經 由P-通道型之第一電晶體而連接到電壓產生器1輸出。 第一電晶體τ 1係在閘極連接到測試信號TEST。陽極線 PLi係經由η-通道型之第二電晶體額外地連接到一接觸 區域。第二電晶體Τ2之閘極亦連接到測試信號TEST。 測試信號決定記憶體之操作模式。假使測試信號具有一 低位準（0V)，則記憶體係在一正常操作模式，而假使測 試信號具有一高位準（3 · 1 V)，則記憶體係在測試操作模 式。 在第1圖中顯示之記憶體衹有一連續之記憶體單元陣 列及感測放大器SA。除此之外，衹有兩條字元線WLk 及四個位元線及對應陽極線PLi被顯示。實際上，記憶 體通常有複數個單元陣列及大量之位元線及字元線，以 及相關之感測放大器。 再者，在FRAM中，差動感測放大器S A通常被使用 對於差動感測放大器，在讀取接達時’除了信號經過各 個被選擇之位元線而饋入，還有一參考信號亦經由一相 關之互補位元線被饋入。然而在第1圖中並未顯示互補 之位元線對，而衹有顯示單一位元線B L i，以便簡化描述。 在正常操作模式中，第1圖之記憶體具有下列操作方 法：藉由對應之位址，字元線WLk之一及行線C S L i之 -1 〇 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------l· I I I ^ 1111111 (請先閱讀背面之注音？事項再填寫本頁) 594733 A7 B7_ 五、發明說明（、。） 在寫入接達期間，感測放大器S A産生一電位Ο V，其傜 經由所選擇位元線BLO及記億體單元MC之選擇電晶體T 存在於儲存電容器C之一電極上。因為極線PLO仍具有 陽極電位1 . 2 5 V，而電壓-1 . 2 5 V傜存在於並橫跨儲存電容 器C上，其造成與寫入邏輯” 1 ”相反之儲存電容器C之鐵 電介電之極化。 位於位元線BLO及剩餘之字元線WLfc之交叉點之記億 體單元MC之儲存狀態不受影響，這是因為其上之選擇電 晶體T被關閉。此外，位在字元線WLO及剩餘之位元線 B L i之交叉點之記億體單元並不受影響，這是因為後者偽 藉由他們的P-通道電晶體P而維持在陽極電位1 . 25V，且 不論這些記億體單元M C之被開啓之選擇電晶體T，電壓 〇 V傺橫跨於其上之儲存電容器。結果是該電容器之儲存 狀態或極化狀態並不受影響。 假使顯示於第1圖之記億體偽藉由測試信號T E S Τ之高 位準到V，在測試操作模式中執行，第一電晶體Τ 1被關 閉，結果，陽極線PLi與産生陽極電位VPL之電壓産生 器1之輸出隔離。此外，第二電晶體T 2被開啓，結果陽 極線P L i傺連接到接觸區域A。結果可以由與陽極電位 VPL不同之所要之電位VF經由接觸區域A饋入陽極線 P L i。此外，在測試操作模式中，所有行選擇線C S L i像 在欲被實施之寫入接達期間為一低位準，使得位元線B L i 皆具有陽極電位。假使至少一字元線W L k被啓動則連 接到該字元線之記億體單元MC之選擇電晶體T被開 一 1 2 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ——,--------_-裝--- (請先閱讀背面之注意事項再填寫本頁) - 經濟部智慧財產局員工消費合作社印製 )94733 五 經濟部智慧財產局員工消費合作社印製 A7 __B7 、發明說明（I，） 啓。之後，1 .25V之陽極電位VPL係經由選擇電晶體T 存在於所選擇之記憶體單元MC之儲存電容器C之一電 極。假使，接著選擇了電位VF= 0，1 .25V之正電壓則橫 跨於對應之儲存電容器C。結果，邏輯” 1”被同時寫入至 具有高字元線WLk位準之所有記憶體單元MC。假使， 例如，電位VF具有一高位準2.5¥，而負電壓-1.25¥係 橫跨所選記憶體單元M C之對應儲存電容器，則邏輯"0 ” 被寫入這些記憶體單元MC之內。在上述之兩種情況中， 新邏輯狀態係同時寫入至複數個記憶體單元MC。 在第1圖顯示之記憶體之情況中，衹有一條字元線WLk 在正常操作模式中被啓動。另一方面，在測試操作模式 中，所有字元線WLk被同時啓動，使得記憶體單元MC 之所有選擇電晶體同時被開啓。以此方式，同時寫入接 達至所有記憶體單元M C。這將在以下參考第4圖更詳盡 地討論。 爲了在測試操作模式中，饋入〃衰減〃位元至記憶體 單元MC，即位元未被以滿信號位準1 .25 V寫入至記憶體 單元，在寫入邏輯”0”期間，特定電位VF之値係被選擇 在陽極電位VDD 1 .25V及正供應電位2.5V之間，例如 2V。爲了寫入衰減邏輯” 1 ”，特定電位VF被選擇在0V及 1 .25V之間，例如0.5V。記憶體單元MC之老化係以此方 式模擬，該老化通常發生在較長的時間內，並造成儲存 於內之信號之衰減。 在本發明之其他實施例中，可以使陽極線P L i在操作 -1 3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I--------丨裝-----^----訂--------- (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 594733 A7 B7__ 1、發明說明（P) 模式中，不連接到接觸區域，與第丨圖之記憶體情況相 反’但是連接到產生電位VF之記憶體之內部電壓產生 器。 在本發明之一實施例中，可以衹使一些陽極線在測試 操作模式中具有電位VF而偏離恆定陽極電位VPL。在此 情況下，寫入接達係衹有同時接達至與這些陽極線連 接之記憶體單元MC。在此情況下，陽極線當然不能互相 電氣連接。 第3圖顯不一電路配置，用於驅動第1圖之兩條字元 線WLk。字元位址RADR可被饋入之字元線解碼器RDEC 被顯示。在正常操作模式中，字元線解碼器依據字元位 址RADR啓動其一輸出B、C。字元線解碼器RDEC之輸 出B、C經由字元線驅動器D而連接至字元線WLk之一。 字元線驅動器D經由p-通道型之第三電晶體T3使其供應 電壓終端連接至第二電壓產生器2之輸出，而第二電壓 產生器2係用來產生第一供應電壓V P P。此外，字元線 驅動器D之供應終端係經由η-通道型之第四電晶體T4 連接至第二接觸區域Ε，經由第二接觸區域，可饋入第二 供應電壓Vext。第三電晶體Τ3及第四電晶體之閘極係連 接到測試信號。在正常操作模式中（Test = 0V)，由第二電 壓產生器2所產生之第一供應電壓VPP，係經由第三電 晶體饋入至字元線驅動器D。在測試操作模式中（測試= 3 . 1 V )，第二供應電壓Vext係經由第四電晶體饋入字元線 驅動器D。第一供應電壓V P P具有3 . 1 V之値。假使字元 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----1---：----^裝----K----訂--------- (請先閱讀背面之注意事項再填寫本頁> 594733 經濟部智慧財產局員工消費合作社印製 A7 ------B7__ 五、發明說明（〇 ) 線WLk之一係由字元線解碼器啓動，則在正常操作模式 中，字元線具有第一供應電壓VPP之値，即3 . 1 V。記憶 體單元MC之各個選擇電晶體T係由3 . 1 V驅動，使得藉 由該電晶體，電位2 _ 5 V可以在寫入邏輯” 1 ”期間自感測放 大器SA傳送至儲存電容器。記憶體單元之選擇電晶體τ 之臨界電壓爲0.6V。 在測試操作模式中，字元線驅動器RDEC同時啓動所 有的字元線WLk，而不論在該字元線驅動器之字元位址 RADR爲何。假使字元線驅動器D亦由在測試操作模式 中之第二電壓產生器2所供應，則該第二電壓產生器之 大小必須夠大，才能同時驅動多個字元線驅動器D。因 此，在測試操作模式中，字元線驅動器並不經由第二電 壓產生器2來供應，而是經由自積體記憶體外之第二接 觸區域E來供應。 在此實施例中，在測試操作模式中經由第二接觸區域E 饋入之第二供應電壓Vext係大於第一供應電壓VPP。其 値爲2V，因此大於陽極電位（1 .25V)及記憶體單元MC之 選擇電晶體T之臨界電壓（0.6 V)之和。在測試操作模式 中，已啓動之字元線WLk係被帶到第二供應電壓Vext二 2V，使得對應選擇電晶體T之閘極爲2V。這個閘極電壓 能夠經由陽極電位VPL，即在測試操作模式中之所有位 元線BLi上存在之1.25V，切換至儲存電容器C之對應電 極。 在本發明之其他實施例中，能夠選擇第二供應電壓 -1 5 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝-----：----訂--------- (請先閱讀背面之注音？事項再填寫本頁) 594733 經濟部智慧財產局員工消費合作社印製 A7 B7 1、發明說明（α)594733 A7 B7_ V. Description of the invention (/) The present invention is about a memory with a bit line, a character line, and an anode line, and an operation method corresponding to this memory. Article by H. Fujisawa et al., Published in IEEE Journal of Solid-State circuits, Vol. 32, No. 5, May 1997, page 655 " The Charge-Share Modified (CSM) Precharge-Level Architecture for `` High-Speed and Low-Power Ferroelectric Memory '' describes the ferroelectric memory of FeARM or FRA M type. These memory cells are constructed in a manner similar to DRAM, but their memory cells have a storage capacitor containing a ferroelectric dielectric. The billion body units are arranged at the intersections of word lines and bit lines. One of the electrodes of the storage capacitor is pseudo-connected to a fixed anode plate potential. The fixed anode plate potential is pseudo intermediate between the two supply potentials of the FR AM. In contrast to FR AM, where the anode potential is not constant, but pulsed (ie, the "pulsed anode concept"), the concept of constant anode potential, as described in the reference, is often referred to as 〃 VDD / 2 concepts 〃. It is known that a transistor of a FR AM / 1 値 capacitor memory cell uses different polarizations of the ferroelectric dielectric of the storage capacitor to store different logic states. If the transistor 选择 is selected in the on state, the electrodes of the storage capacitor will be at the same potential, that is, the voltage Q 傺 will be across the storage capacitor, and the polarization will not be affected. The status is also unaffected. For example, in order to be able to select one hundred million body units from a plurality of hundred million body units, the plurality of hundred million body units are connected to the same word line, and the hundred million body units 僳 accept read access. The above article gives except selection Description of how all the word lines outside the word line are precharged to a constant anode potential. If the unselected zigzag line passes through the memory unit-3-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ——V ------- 丨 _-install—— (Please read the precautions on the back before filling out this page) · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 4733 A7 ---- B7 V. Description of the Invention (>) Selection transistor is connected to the electrode of the storage capacitor , The electrode in the storage capacitor has an anode potential, and the storage content is not affected. However, the bit line is selected to be brought to a potential deviating from the anode potential, and as a result, the crossover voltage of the storage capacitor of the memory cell connected to the bit line is decreased. As a result, the charge balance between the storage capacitor and the selected bit line is caused. As a result, the potential of the selected bit line has different effects depending on the polarization state of the storage capacitor. The sense amplifier amplifies the logic information thus read. However, in the write-connected memory described, the bit lines of those unreachable memory cells are maintained at the anode potential. On the other hand, the potential of the selected bit line is written into the memory cell, which is brought to the corresponding write potential by the sense amplifier, which is different from the anode potential. The selected bit line is discharged to ground, for example, write logic 0, and write logic 1 is tied to the positive supply potential. In certain applications, such as in test mode, the same information needs to be written to a large number of memory cells. A simple memory test can be provided, for example, a logic 1 is written to all memory cells and read out later. In order to perform a test on the memory described in the above article, it is necessary to continuously write to all memory cells, because there is only one word line and one bit line, so that one memory cell at the intersection can be simultaneously Was selected. The present invention is based on the following objectives: to clarify a cumulative memory, in which the same logical information is simultaneously written to a plurality of memories in a simple manner. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) (Please read the notes on the back before filling out this page) --ill · — — — ^ «—— — — — — I, Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives Printing 594733 A7 B7 V. Description of Invention (Order) Unit. The invention is achieved by using the integrated memory according to item 1 of the scope of patent application and the operating method of the integrated memory according to item 8 of the scope of patent application. The scope of the attached patent application relates to advantageous designs and developments of the invention. The integrated memory according to the present invention has a first operation mode and a second operation mode. In the first operation mode, the 'anode line has a constant anode potential, and the bit line also has an anode potential, provided that it is not connected. If any one of the memory cells is reached, if it is a write access to one of the memory cells, the word line connected to the memory cell has a first potential to write a first logic state. The first potential The potential is smaller than the anode potential, and a second potential is written to the second logic state. The second potential is larger than the anode potential. Therefore, in the second operation mode, the bit line has the anode potential, and the write access At least one anode line has a specific potential, which is different from the anode potential. Therefore, although the memory according to the present invention has a first mode of operation, such as the known FRAM and the above-mentioned article written by H. Fujisawa, in other words, the write access to the memory cell is based on the potential of the bit line The change is achieved. In the second operation mode, the information writing is not achieved by changing the potential of the bit line, but by changing the potential of the anode line. This means that in the first operation mode, according to the present invention, The operation of the memory is like the traditional memory, which is operated according to the VDD / 2 concept. However, in the second operation mode, the electrode of the storage capacitor to be written is connected to the anode line and is no longer connected to the constant line. The anode potential is connected to a partial paper size that applies the Chinese National Standard (CNS) A4 specification (210 X 297 public directors) ---- 丨 丨! !! ^ Install! ρί 丨 · --I-- (Please read the note on the back? Matters before filling out this page) 594733 Printed by A7 B7, member of the Intellectual Property Bureau of the Ministry of Economic Affairs / Industrial and Consumer Cooperatives V. Description of the invention (a) Specific potential shifted, In the first mode of operation, the voltage across the storage capacitor used to write new logic information items to the memory cell is generated by the potential change of each bit line, while the potential of the anode line remains constant; in another On the other hand, in the second operation mode, the write voltage required across the storage capacitor is generated by keeping the potential of the bit line constant, and by changing the potential of the corresponding anode line to a value that deviates from the constant anode potential. The memory according to the present invention has the advantage of allowing the same information to be simultaneously written into a plurality of memory cells in a simple manner. This is achieved for all memory cells at the same time, and the associated anode line has a specific potential that deviates from the anode potential. In extreme cases, all anode lines of the memory can set a specific potential at the same time, so that the same logic information is written to all memory cells at the same time. The anode wire can be made a part of the unit anode of continuity, thus forming a continuity area. The change in the potential of the anode of this unit causes all anode wires of the storage capacitor and the electrodes connected to the storage capacitor to be brought to the changed potential at the same time. According to development, the specific potential is the first or second potential, and the bit line is set to this specific potential when the write access of the first operation mode is made. If the specific potential is equal to the first potential, the second logic state is written to the corresponding memory cell under the write access condition in the second operation mode. If the specific potential is equal to the second potential, the first logic state is written to the corresponding memory cell. According to another development, the specific potential is between the anode potential and the first or second potential. As a result, the first and / or second logical states did not apply to the full-scale standard. The Chinese paper standard (CNS) A4 (210 X 297 mm) was applied. --- Γ ----- I · I --- : ---- Ordered! II ---- (Please read the precautions on the back before filling out this page) 594733 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (r) is written to the corresponding memory unit. Attenuation level ° In this way, the aging of the memory unit can be favorably simulated, and as a result, the signals stored in the memory unit are similarly attenuated. By aging simulation of the logic state (the logic state is not written at the full signal level), the time required for a continuous test is advantageously shortened. This is because the "attenuation" bit has been written into the memory cell, and its "attenuation" bit (in the continuation memory's writing system acts at the full signal level). Only available after a long time for leakage current. According to a development, the integrated memory has a terminal region ' for feeding a specific potential from the memory. This has the benefit that specific potentials can be selected as needed and changed during memory operation. According to a development of the present invention, the memory device has a character line driver, which connects one of the character line decoder output to one of the character lines, and a voltage generator for generating characters for the character in the first operation mode. The first supply voltage of the line driver. Furthermore, the memory has a termination region for feeding a second supply voltage to the word line driver in the second operation mode. This has the advantage that the second supply voltage can be selected as needed and is independent of the first supply voltage. An embodiment of an operating method according to the present invention provides a second supply voltage that is lower than the first supply voltage. This reduces the electricity consumption cost of the memory in the second operation mode, which is compared with the case where the word line driver is also supplied with a higher first supply voltage in the second operation mode. In addition to feeding through a contact area, a second supply voltage can also be generated in the integrated memory. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------------ 11-^ ---- Order -------- 1 (Please read first Note on the back? Matters should be filled out on this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 594733 A7 B7_ V. Description of the Invention (^) According to the development of the operating method, the second supply voltage is selected so that it becomes a character line When activated by the related word line driver, the potential of the word line is higher than the threshold voltage of the anode potential plus the selection transistor of the memory cell, but lower than the first supply voltage. In the first operation mode, when one of the two logic states is written, the selection transistor must transmit a potential from a bit line to the corresponding storage capacitor, which is higher than the anode potential (this is the logic 1 is written General conditions). Therefore, in order to activate the selection transistor, the word line must be brought to a potential which is higher than the highest potential of the bit line plus the threshold voltage of the selection transistor. The first supply voltage must be selected to be as high as the first mode of operation. Because in the second mode of operation, the potential of the bit line is constant and equal to the anode potential. If the potential at least equal to the anode potential plus the critical voltage of the selection transistor passes through the word line and exists in the related selection transistor, then the bit The element line potential is transferred to the corresponding electrode of the storage capacitor without any loss. According to another embodiment of the operating method, the second supply voltage is selected so that when a word line is activated by the related word line driver, the potential of the word line is lower than or equal to the anode potential plus the memory cell. Select the threshold voltage of the transistor. As a result, in the second operation mode, the selection transistor in the on state is not transmitted to the corresponding anode of the storage capacitor, which is the potential at which the bit line is located, but transmits a lower potential. What is achieved in this way is that, in the second operating mode, the data is not written to the memory cell at a full signal level but at a decaying signal level. According to the development of one of the integrated memories, in the first operation mode, the Chinese paper standard (CNS) A4 (210 X 297 mm) is applied to the paper size of the manuscript. -------- II —Aw · I- --r IIIIIII I --- (Please read the note on the back? Matters before filling out this page) 594733 A7 B7 V. Description of the invention The model element is a single exercise. One or two are in the first place, and the other side is the same as the other one. When the call is received, C remembers the time when it is recorded and the same place is lined up. The second column is in Yuan: The single one arrives every time. In the formula, the matter is based on the number of billions of pixels. 5 ο The simultaneous action when the word of the yuan is reached when it reaches the line. When the time element is the same, the detailed line of the simplified diagram is more detailed and the actuality of the word example is more practical. It is the same as that of the single pattern in the successive strokes. His Majesty's ffu ΛZO οώ The first example of the actual implementation of the system of 100 million yuan, the system of the system, the system of the system, the system of the system, the system of the system, the system of the system, and the operation of the system. Figure 3 Detailed device code solution line metacharacter Figure 3 First display 4 First display 0 Detailed display 0 Detailed display 100 million volume type M Α RF The clear display of this document shows 1X The first 100 million i LL A.1I0P The center line has its poles, the Yang column and the plug k array L element single billion K K has BL wire body million million \ Record in this column "kl— r5. O ® point material fork MeMe cross-line characters (please read the notes on the back before filling out this page) Pack -I ϋ ϋ One: OJa ϋ ϋ ϋ «1 I ϋ ·, Printed by the Intellectual Property Bureau Employee Consumer Cooperatives Figure 1X of the CM unit of the electric selector. Figure 1X shows the ο C device capacity 1. The electric PL stores a stored wire electrode. The anode and the iron are connected to the iron and the electrode. In addition, after the selection, an electrode has a storage device to store a hidden crystal. The connection of the BL path line element position control shows the step of the line element to the body crystal channel I η from the warp image * conjoined S device device to produce large-scale discharge voltage measurement _ to a connection?-Wiring The electric circuit of Yuanwei 411 is Tongyang P'-determined by Hengjingshengxiang L. Its paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. # 594733 A7 B7 _ 5. Description of the invention (彳) Bit VPL. Each of the n-channel transistor N and the p-channel transistor P (each of which is assigned to the same bit line BLi) is connected to the row selection line CSLi. The anode lines PLi are connected to each other at the edges of the cell array. They are connected to the output of the voltage generator 1 via a P-channel type first transistor. The first transistor τ 1 is connected at the gate to the test signal TEST. The anode line PLi is additionally connected to a contact region via an n-channel type second transistor. The gate of the second transistor T2 is also connected to the test signal TEST. The test signal determines the operating mode of the memory. If the test signal has a low level (0V), the memory system is in a normal operation mode, and if the test signal has a high level (3 · 1 V), the memory system is in the test operation mode. The memory shown in Fig. 1 has only one continuous memory cell array and a sense amplifier SA. In addition, only two word lines WLk and four bit lines and corresponding anode lines PLi are displayed. In fact, a memory usually has a plurality of cell arrays, a large number of bit lines and word lines, and related sense amplifiers. Furthermore, in FRAM, the differential sense amplifier SA is usually used. For the differential sense amplifier, when reading and receiving, 'in addition to the signal being fed through each selected bit line, there is also a reference signal via a correlation The complementary bit lines are fed. However, the complementary bit line pairs are not shown in Fig. 1, but only a single bit line B L i is displayed in order to simplify the description. In the normal operation mode, the memory of Figure 1 has the following operation methods: by corresponding address, one of the character lines WLk and the line CSL i -1 〇-This paper size applies the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) -------------- l · III ^ 1111111 (Please read the note on the back? Matters before filling out this page) 594733 A7 B7_ V. Description of the invention ( During the writing access period, the sense amplifier SA generates a potential 0 V, which is present on one of the electrodes of the storage capacitor C via the selected bit line BLO and the selection transistor T of the memory cell MC. Because the polar line PLO still has an anode potential of 1.25 V, and a voltage of -1.25 V 傜 exists and crosses the storage capacitor C, it causes the ferroelectricity of the storage capacitor C, which is the opposite of the write logic "1" Dielectric polarization. The storage state of the memory cell MC located at the intersection of the bit line BLO and the remaining word line WLfc is not affected because the selection transistor T thereon is turned off. In addition, the billion-body unit at the intersection of the word line WLO and the remaining bit lines BL i is not affected, because the latter is maintained at the anode potential by their P-channel transistor P1 25V, irrespective of the selected transistor T of the memory cell MC being turned on, a voltage of 0V 傺 across the storage capacitors. As a result, the storage state or polarization state of the capacitor is not affected. Suppose that the digitizer shown in Fig. 1 is falsely tested by the high level of the test signal TES T to V. In the test operation mode, the first transistor T 1 is turned off. As a result, the anode line PLi and the anode potential VPL The output of the voltage generator 1 is isolated. In addition, the second transistor T 2 is turned on, and as a result, the anode line P L i 傺 is connected to the contact area A. As a result, a desired potential VF different from the anode potential VPL can be fed into the anode line P L i via the contact area A. In addition, in the test operation mode, all the row selection lines C S L i are at a low level during the write access to be implemented, so that the bit lines B L i have an anode potential. If at least one character line WL k is activated, the selection transistor T of the memory cell MC connected to the character line is turned on. 1-This paper size applies to China National Standard (CNS) A4 (210 X 297) (Mm) ——, --------_- install --- (Please read the notes on the back before filling out this page)-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 94533 A7 __B7 printed by the Property Cooperative Consumer Cooperative, Invention Description (I,) Kai. Thereafter, the anode potential VPL of 1.25 V is present at one of the electrodes of the storage capacitor C of the selected memory cell MC via the selection transistor T. If a potential VF = 0 is selected next, a positive voltage of 1.25V will traverse the corresponding storage capacitor C. As a result, the logic "1" is simultaneously written to all the memory cells MC having the high word line WLk level. If, for example, the potential VF has a high level of 2.5 ¥, and a negative voltage of −1.25 ¥ is across the corresponding storage capacitor of the selected memory cell MC, then logic “0” is written into these memory cells MC. In both cases, the new logic state is written to multiple memory cells MC at the same time. In the case of the memory shown in Figure 1, only one word line WLk is activated in the normal operating mode. On the one hand, in the test operation mode, all the word lines WLk are activated at the same time, so that all the selection transistors of the memory cell MC are turned on at the same time. In this way, all the memory cells MC are simultaneously accessed. This will It is discussed in more detail below with reference to Figure 4. In order to feed the "attenuation" bit to the memory cell MC in the test operation mode, that is, the bit is not written to the memory cell at the full signal level of 1.25 V During the writing of logic "0", the system of the specific potential VF is selected between the anode potential VDD 1.25V and the positive supply potential 2.5V, such as 2V. In order to write the attenuation logic "1", the specific potential VF is Select at 0V Between 1.25V, such as 0.5V. The aging of the memory cell MC is simulated in this way. The aging usually occurs over a long period of time and causes the attenuation of the signal stored therein. In other embodiments of the present invention Can make the anode line PL i in operation-1 3- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) I -------- 丨 Installation ----- ^ ---- Order --------- (Please read the phonetic on the back? Matters before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 594733 A7 B7__ 1. In the description of the invention (P) It is not connected to the contact area, which is the opposite to the situation of the memory in the figure. But it is connected to the internal voltage generator of the memory that generates the potential VF. In one embodiment of the present invention, only some anode lines can be tested. The mode has a potential VF and deviates from the constant anode potential VPL. In this case, the write access only has access to the memory cells MC connected to these anode lines at the same time. Of course, the anode lines cannot of course be electrically connected to each other. Figure 3 shows a circuit configuration for driving Figure 1. Two word lines WLk. The character line decoder RDEC where the character address RADR can be fed is displayed. In normal operation mode, the character line decoder activates one of its outputs B, C according to the character address RADR. Outputs B and C of the word line decoder RDEC are connected to one of the word lines WLk via a word line driver D. The word line driver D connects its supply voltage terminal via a third transistor T3 of the p-channel type. The output to the second voltage generator 2 is used to generate the first supply voltage VPP. In addition, the supply terminal of the word line driver D is connected via the fourth transistor T4 of the η-channel type To the second contact region E, a second supply voltage Vext can be fed through the second contact region E. The gates of the third transistor T3 and the fourth transistor are connected to the test signal. In the normal operation mode (Test = 0V), the first supply voltage VPP generated by the second voltage generator 2 is fed to the word line driver D via a third transistor. In the test operation mode (test = 3.1 V), the second supply voltage Vext is fed into the word line driver D via the fourth transistor. The first supply voltage V P P has a range of 3.1 V. If the paper size of the character is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) ---- 1 ---: ---- ^ ------------------------ ------ (Please read the notes on the back before filling out this page> 594733 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ------ B7__ 5. Description of the invention (〇) One of the line WLk It is activated by the word line decoder. In normal operation mode, the word line has one of the first supply voltage VPP, which is 3.1 V. Each selection transistor T of the memory cell MC is 3.1 V Driven so that with this transistor, a potential of 2 _ 5 V can be transferred from the sense amplifier SA to the storage capacitor during the writing logic “1”. The threshold voltage of the transistor τ of the memory cell is 0.6V. Under test In the operation mode, the word line driver RDEC starts all the word lines WLk at the same time, regardless of the word address RADR of the word line driver. If the word line driver D is also the second in the test operation mode, Supplied by the voltage generator 2, the size of the second voltage generator must be large enough to drive multiple word line drivers at the same time Therefore, in the test operation mode, the word line driver is not supplied through the second voltage generator 2, but is supplied through the second contact area E outside the self-integrated memory. In this embodiment, In the test operation mode, the second supply voltage Vext fed through the second contact area E is greater than the first supply voltage VPP. Its 値 is 2V, so it is greater than the anode potential (1.25V) and the selection transistor of the memory cell MC The sum of the threshold voltage (0.6 V) of T. In the test operation mode, the activated word line WLk is brought to the second supply voltage Vext 2V, so that the gate of the corresponding selection transistor T is 2V. This gate The voltage can be switched to the corresponding electrode of the storage capacitor C via the anode potential VPL, that is, 1.25V present on all bit lines BLi in the test operation mode. In other embodiments of the present invention, the second supply voltage can be selected − 1 5-This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ----------- installed -----: ---- order ----- ---- (Please read the phonetic on the back? Matters before filling out this page) 594733 Ministry of Economic Affairs Hui Property Office employees consumer cooperatives printed A7 B7 1, invention is described in (α)
Vext之値，使其小於或等於陽極電位及選擇電晶體之臨 界電壓之和。假使第二供應電壓被選擇爲1 .25 V， 因而等於陽極電位VPL，則後者之大小不再經由選擇電 晶體傳送到在測試操作模式中之儲存電容器。結果，〃 衰減〃位元係在此情況中寫入至記憶體單元MC，結果再 次模擬了記憶體單元MC之老化。 在本發明之其他實施例中，在測試操作模式中，字元 線驅動器D可以用來連接至積體記憶體之對應內部第二 供應電壓Vext，這意味著第二接觸區域E爲多餘的。在 此情況中，最好能使第二供應電壓Vext小於第一供應電 壓VPP，以便減少記憶體之能源消耗量。爲了產生第二 供應電壓Vext，記憶體內應具有對應之電壓產生器。 第4圖顯示第3圖之字元線解碼器RDEC之詳細圖。 這個字元線解碼器具有由第五個電晶體、第六個電晶 體、第七個電晶體及第八個電晶體形成之序列電路，在 高供應電位VDD及低供應電位接地之間。第五個電晶體 係P-通道型，而其餘三個電晶體則是η-通道型。在第五 Τ5及第六Τ6電晶體之間之電路節點係經由兩個背對背 之反相器之保持電壓Η及在下游之反相器I連接至字元 線解碼器RDEC之輸出。一在第七電晶體Τ7及第八電晶 體Τ8之間之電路節點係經由η-通道型之第九電晶體連接 至保持電路Η之輸入。第九電晶體T9之閘極係連接至測 試信號TEST。 第五及第八電晶體之閘極之閘極係連接至一區塊信號 -1 6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----— — — — — — -----r I I I -------- (請先閱讀背面之注音？事項再填寫本頁) 594733 A7 B7_ 五、發明說明（β ) (請先閱讀背面之注音？事項再填寫本頁) B S，第六電晶體之閘極係連接到第一位址信號A 1，第七 電晶體之閘極則連接到第二位址信號A 2。兩個位址信號 A 1、A 2及方塊信號B S傺形成字元位址R A D E。從第3圖之 字元線解碼器之每個輸出Β、C傺被指派第四圖之電路。 所有的這些電路分享相同的區塊信號BS。在另一方面， 他們的位址信號Al、Α2並不相同。區塊信號BS作為顯示 於第1圖中之單元陣列之選擇，而記億體之其他單元陣 列，未示於第1圖中，偽被指派有其他的區塊信號。單 元陣列之字元線WLk之一係由在正常操作模式中之位址 信號A 1及A 2所選擇。 經濟部智慧財產局員工消費合作社印製 在正常操作模式中（T e s t = Ο V)，第九電晶體被鼸閉， 使得第六及第七電晶體並不橋接。因此，當一字元位 址R ADR被施加時，紙有一字元線WLk被選取，這是因為 祗有字元線解碼器R D E C之輸出B、C中之一個被啓動。 在測試操作模式中（T e s t = 3 . 1 V )，第九電晶體T 9被開啓 ，橋接第六T 6及第七T 7電晶體，使得位址信號A 1、A 2 均無效，而字元線解碼器RD EC之所有輸出B、C傺藉由 區塊信號B S同時啓動，g卩是邏輯” 0 ’’。以此方式，在測 試操作模式中，在區塊信號B S為高位準時，單元陣列或 一區塊之所有字元線同時被啓動。 假使，在第1圖中之記億體中，需要相同的資訊被寫 入至正常操作模式中之所有記憶體單元M C，則必須依序 選取所有的字元線W L k及所有的位元線B L i。寫入紙能 依序地對所有記憶體單元M C有效，如同傳統的根據 VDD/2設計的FRAM操作。根據本發明之測試操作模式 能同時寫入相同的資料到複數値記億體單元M C ,而減少 _-17-_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 594733 A7 B7 五、發明説明（/t ) 寫入該資料所需的時間。 主要元件符號說明： ----i---r---------、訂-----Aw (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -18- MC 記 憶 體 IUZ. 單 元 T 電 晶 體 C 電 容 器 BLi 位 元 線 WLK 字 元 線 PLi 陽 極 線 VPL 陽 極 電 位 VF 特 定 電 位 RDEC 字 元 線 解 碼 器 RADR 字 元 線 位 址 VPP 第 一 供 應 電 壓 Vext 第 二 供 應 電 壓 D 字 元 線 驅 動 器 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）The value of Vext is less than or equal to the sum of the anode potential and the critical voltage of the selected transistor. If the second supply voltage is selected to be 1.25 V and thus equal to the anode potential VPL, then the magnitude of the latter is no longer transmitted to the storage capacitor in the test operation mode via the selection transistor. As a result, the "attenuation" bit is written to the memory cell MC in this case, and the result once again simulates the aging of the memory cell MC. In other embodiments of the present invention, in the test operation mode, the word line driver D may be used to connect to the corresponding internal second supply voltage Vext of the memory, which means that the second contact area E is redundant. In this case, it is preferable to make the second supply voltage Vext smaller than the first supply voltage VPP in order to reduce the energy consumption of the memory. In order to generate the second supply voltage Vext, a corresponding voltage generator should be provided in the memory. Fig. 4 shows a detailed diagram of the word line decoder RDEC of Fig. 3. This word line decoder has a sequence circuit formed by a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, between a high supply potential VDD and a low supply potential ground. The fifth transistor is of the P-channel type, while the remaining three transistors are of the η-channel type. The circuit node between the fifth T5 and the sixth T6 transistor is connected to the output of the word line decoder RDEC via the holding voltage of the two back-to-back inverters and the inverter I downstream. A circuit node between the seventh transistor T7 and the eighth transistor T8 is connected to the input of the holding circuit via a n-channel type ninth transistor. The gate of the ninth transistor T9 is connected to the test signal TEST. The gates of the gates of the fifth and eighth transistors are connected to a block signal-1 6- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ — — — ----- r III -------- (Please read the phonetic on the back? Matters before filling out this page) 594733 A7 B7_ 5. Description of the invention (β) (Please read the phonetic on the back? Please fill in this page again for matters) BS, the gate of the sixth transistor is connected to the first address signal A 1, and the gate of the seventh transistor is connected to the second address signal A 2. The two address signals A 1, A 2 and the block signal B S 傺 form a character address R A D E. Each output B, C 傺 of the word line decoder of Fig. 3 is assigned the circuit of Fig. 4. All these circuits share the same block signal BS. On the other hand, their address signals Al and A2 are not the same. The block signal BS is selected as the cell array shown in FIG. 1, and the other cell arrays of the memory cell are not shown in FIG. 1, and other block signals are pseudo-assigned. One of the word lines WLk of the cell array is selected by the address signals A 1 and A 2 in the normal operation mode. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In normal operation mode (T e s t = 0 V), the ninth transistor is closed, so that the sixth and seventh transistors are not bridged. Therefore, when a word address R ADR is applied, a word line WLk of the paper is selected because one of the outputs B, C of the word line decoder R D E C is activated. In the test operation mode (T est = 3.1 V), the ninth transistor T 9 is turned on, bridges the sixth T 6 and the seventh T 7 transistor, so that the address signals A 1 and A 2 are invalid, and All outputs B and C of the word line decoder RD EC are activated simultaneously by the block signal BS, and g 卩 is a logic "0". In this way, in the test operation mode, when the block signal BS is high on time All cell lines of a cell array or a block are activated at the same time. If, in the memory of Figure 1, the same information is required to be written to all the memory cells MC in the normal operation mode, it must be Select all the word lines WL k and all the bit lines BL i in order. The writing paper can be effective for all the memory cells MC in sequence, just like the traditional FRAM design based on VDD / 2. According to the invention, The test operation mode can simultaneously write the same data to the complex memory cell MC, and reduce _-17-_ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 594733 A7 B7 V. Description of the invention (/ t) The time required to write the information. No. Description: ---- i --- r --------- 、 Order ----- Aw (Please read the precautions on the back before filling out this page) Employees ’Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs Printed -18- MC memory IUZ. Cell T transistor C capacitor BLi bit line WLK word line PLi anode line VPL anode potential VF specific potential RDEC word line decoder RADR word line address VPP first supply voltage Vext second supply voltage D word line driver This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm)