JPH0729398A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify a fault reject by forcibly making a memory cell unstable. CONSTITUTION:A pair of transfer MOSFETA1 and A2 constituting an FF type memory cell are provided and a pair of word lines WLA and WLB divided and connected to the gates of the MOSFETS are provided. At the time of testing the memory cell, different potentials are given to the word lines WLA and WLB, the latching state of the FF is forcibly made unstable and thus, identification of a faulty memory cell is made easier. Individual powers VD1 and VD2 for giving desired potentials to the word lines WLA and WLB and a operation mode switching circuit 7 are provided and the potentials to be given to the word lines WLA and WLB are switched between the normal operation time and the testing time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a test circuit for detecting a defect in a marginal cell.

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram of a bit line load circuit of a conventional semiconductor memory device. In the figure, BL, / BL
Is a pair of bit lines, L1 and I2 are a pair of bit line load transistors, A1 and A2 are drive transistors which form memory cells, and I1 and I2 are transfer M which form memory cells.
The OS transistors R1 and R2 represent the load resistance of the memory cell.

When a memory cell is selected when the memory cell selection line WL is at "H" level, the flip-flop type memory cell of SRAM is composed of an inverter composed of L1, A1 and I1 and L2, A2 and I2. It consists of an inverter. At this time, R1 and R2 usually have large resistance values and can be ignored.

Consider an inverter composed of L1, A1 and I1. 0 ≦ Vin ≦ Vth (N channel M
At the threshold voltage of the OS transistor), I1 is in the off state, and a1 becomes Vdd-Vth through L1 and A1.
When Vth ≦ Vin ≦ Vdd, I1 has an ON resistance according to the value of Vin. L1 and A1 each have on-resistance,
The sum of the sum and the on-resistance of I1 provides a potential that is resistance-divided between Vdd and GND to a1. The graph of this characteristic is the solid line in FIG. L2, A2
The characteristics of the inverter based on I2 are similar, and since the input and output terminals are opposite, they can be overlapped as shown by the dotted line. The intersection of the solid line and the dotted line is a stable point, and the larger the shaded area, the more difficult the flip-flop is to invert.

However, for example, 1 Mbit SRA
If M, there are 1 million memory cells in the same chip. As described above, among a large number of memory cells, if they do not operate at all, they are defective by a simple function test, but there are also memory cells that normally operate and fail only in special cases.

For example, when the finished dimensions of the transistor A2 are varied and the on-resistance of the load is reduced, the characteristics of the memory cell are as shown in FIG. 13 (b), which makes it easier to invert as compared with a normal memory cell. a1 is "H", a2
Is "L" level, BL is "H" and / BL is "
Another memory cell at the L "level is read out, then this memory cell is read out, and then BL is again" L ", / BL
When the operation of reading another memory cell whose "H" is "H" is continuously performed in a short cycle, the memory cell is affected by the bit line level, the levels of a1 and a2 gradually change, and finally, There is a problem that it is reversed.

In order to detect such a marginal cell, a method disclosed in Japanese Patent Laid-Open No. 3-276500 has been proposed. This method adds a means for receiving a signal from the outside to enter the test mode and lowering the on-resistance of one of the pair of bit line loads only when the test mode is entered.

FIG. 12 is a diagram for explaining the above conventional example.

In this conventional example, when the test mode is entered, either the signal TEST3 or TEST4 is set to "".
H ”. For example, when TEST3 is“ H ”, BL load is L1 + M1 and / BL load is L2.
It will only be. Fig. 13 shows the characteristics when not in test mode.
A memory cell having unstable characteristics as shown in FIG.
When T3 is set to "H", the characteristic becomes as shown in FIG. 13B, and the latch is not applied.

The state of being latched while being unstable does not become defective unless special disturb that takes a long time is applied. However, by forcibly testing such a memory cell in an unstable state, Can be easily rejected as defective.

However, in general, the SRAM is set to have a large read bit line load capacity and a small write bit line load capacity in order to secure a high speed at the time of reading and a margin at the time of writing. Therefore, when it is desired to check a marginal memory cell for both reading and writing, it is necessary to set imbalances separately for reading and writing, which complicates size setting. There is also a problem that layout of the bit line load becomes difficult. In addition, in order to simplify the layout and size determination, if this conventional example is applied only to reading, it is impossible to equivalently check a failure mode peculiar to writing that loses the capability of the transfer MOS transistor. was there.

[0012]

A semiconductor memory that rejects memory cells (memory cells whose characteristics deviate from the distribution) that will not become defective unless a special disturb that takes a long time is applied in a latched state that is unstable. The purpose is to obtain the device.

Further, the circuit and layout are not complicated,
An object of the present invention is to obtain a semiconductor memory device capable of checking a marginal cell even in a write-specific mode.

[0014]

Means for Solving the Problem Means 1. Pair of transfer MO
In a semiconductor memory device including a flip-flop type memory cell in which word lines connected to respective gates of S transistors are separately arranged, a pair of word line potentials can take different values during a shipping test.

Means 2. The semiconductor memory device according to means 1 is characterized in that one word line potential is VDD potential and the other word line potential is boost VDD potential.

Means 3. The semiconductor memory device according to means 1 is characterized in that one word line potential is a VDD potential and the other word line potential is a step-down VDD potential.

Means 4. One of a pair of word line drive circuits, a flip-flop type memory cell in which word lines connected to respective gates of a pair of transfer MOS transistors are separately arranged, a pair of word line drive circuits for driving the pair of word lines A first word line driving power source supplied from the outside,
A second word line drive power supply externally supplied to the other,
It is characterized by comprising an operation mode switching circuit for switching between the word line driving power supply during normal operation and the word line driving power supply during test.

Means 5. One of a pair of word line drive circuits, a flip-flop type memory cell in which word lines connected to respective gates of a pair of transfer MOS transistors are separately arranged, a pair of word line drive circuits for driving the pair of word lines It is characterized by comprising a word line drive voltage generating circuit for generating a boosted voltage or a lowered voltage on the other side of VDD, and a timing generation circuit for generating a timing for generating the boosted voltage or the lowered voltage.

Means 6. The timing generating circuit according to means 5 is configured to generate a boosted voltage or a stepped-down voltage based on (at the time of testing) and (at the time of starting writing and starting chip select access or address access). .

[0020]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment relating to the means 1. In FIG. 1, BL and / BL are a pair of bit lines, L
1, 12 are a pair of bit line load transistors, A1, A
2, I1 and I2 are N-channel type MOS transistors forming a memory cell, R1 and R2 are load resistances of the memory cell, and WLA and WLB are transfer MOS transistors A1 and A.
A word line connected to each of the two gates, VDD indicates a power supply voltage, and GND indicates a ground potential. Further, the signal PCC is a signal for varying the bit line load capacity at the time of reading and writing, and is set to "H" at the time of reading to increase the load capacity,
At the time of writing, it is set to "L" to reduce the load capacity.

A memory cell in which WLA and WLB are separated is a 1991 IEDM technical digest.
Reported in P477-478, it is relatively easy to implement.

The feature of this embodiment is that the word line WLA and the word line WLB can have different potentials. As a result, the on-resistance of the one-side transfer MOS transistor is changed and the memory cell is unbalanced. It is possible to easily reject as a defect by forcibly testing the memory cell having the characteristics as shown in FIG. 13B when not in the test mode in an unstable state.

The means 2 is characterized in that the potential on one side of the word line is VDD and the potential on the other side is a boosted VDD potential higher than the VDD potential. By setting the boosted VDD potential, the capability of the transfer MOS transistor is increased. The memory cell having the characteristics as shown in FIG. 13B when not in the test mode is shown in FIG.
As in (c), the characteristics are not latched.

The means 3 is characterized in that the potential on one side of the word line is VDD and the potential on the other side is a step-down VDD potential lower than the VDD potential. By setting the step-down VDD potential, the on-resistance of the transfer MOS transistor becomes high and the write time (time constant) becomes long. For example, in the case of a memory cell in which the contact connecting the a1 side node of the transfer MOS transistor and the drain node of the drive MOS transistor has some problem and has a high resistance, and the write margin is lost, the word line potential is stepped down. By setting the potential to VDD, the capacity of the transfer MOS transistor is further reduced, resulting in writing failure. In this way, a marginal defect can be detected.

The means 4 is the first example of the configuration for actually realizing the means 1.

FIG. 3 shows a block diagram. A memory cell 1 having a pair of word lines separated from each other, a pair of word line driving circuits 2 for driving the pair of word lines, and power sources VD1 and VD of the pair of word line driving circuits provided from the outside during a test.
2 and an operation mode switching circuit 7 that switches to supply VD1 and VD2 as a power supply for a pair of word line drive circuits during testing and to supply VDD during normal operation.

The operation mode switching circuit 7 causes the TEST
When 1 signal is "H", the chip enters test mode and VD
1, VD2 are used as a power source for the word line drive circuit 2. When the TEST1 signal is "L", the chip is in a normal operation state, and VD1 and VD2 are not input, so that VDD is supplied as the power supply of the word line drive circuit. Since the operation mode switching circuit 7 is composed of P-channel MOS transistors, the external input signals VD1 and VD2
Is given as a voltage lower than (VDD + Vth of Pch).

The word line drive circuit 2 to which VD1 and VD2 are input receives the word line selection signal / WL and raises the word line. Therefore, the "H" potential of the word line is VD1,
The potential of VD2 is output.

By adopting this structure, VD1, V
It is possible to freely set D2 from the outside, and it is possible to perform tests in both step-up and step-down modes. That is,
It is possible to detect the marginal defect peculiar to writing which appears at the time of step-down as described in the embodiment of the means 3.

The means 5 is a second example of the configuration for actually realizing the means 1.

FIG. 4 shows a block diagram.

Address buffer circuit 5, address decode circuit 6, timing generation circuit 4, word line drive voltage generation circuit 3, pair of word line drive circuits 2, pair of transfer MOs.
A flip-flop type memory cell 1 in which word lines connected to the respective gates of the S transistors are separately arranged.

Next, a detailed description will be given with reference to circuit examples one by one.

The address buffer circuit is shown in FIG. The address buffer circuit 5 includes an address buffer circuit 51 that receives an external address signal and generates an internal address signal,
An address transition detection circuit 52 that detects a change in the address signal and generates an ATD signal.

The ATD signal is sent to the timing generation circuit 4. The timing generation circuit shown in FIG. 7 synthesizes the / CS signal falling detection circuit 41, the / WE signal falling detection circuit 42, the address transition detection signal, the / CS falling detection signal, and the / WE falling detection signal. Signal CL
It is composed of a synthesis circuit 43 for generating M and the like. This C
Timing is generated based on the LM signal, the TEST1 signal, and the TEST2 signal. That is, the timing is generated such that the word line is stepped up or stepped down within a certain period from the start of writing, the start of chip select access, and the start of address access. This timing corresponds to the means 6.

When TEST1 is "H", the chip is in the test mode and the word line potential control circuit is activated. T
The EST2 signal is used to switch between the one-node test mode and the other-node test mode of the memory cell. That is, either the SCON1 signal generation gate or the SCON2 signal generation gate is activated to determine which of the pair of word lines the boosted or stepped down VDD potential is applied to. Further, the timing of the step-up or step-down is formed inside the chip by taking the logic with the CLM signal. This simplifies testing by eliminating the need for complicated timing from the outside.

SCO generated by the timing generation circuit 4
The N1 and SCON2 signals are sent to the word line drive voltage generation circuit 3. 5 shows a booster circuit, and FIG. 6 shows an embodiment of a step-down circuit. For each of SCON1 and SCON2, the circuit of either FIG. 5 or FIG. 6 is provided in a pair depending on whether the voltage is stepped up or stepped down. Output signal VD is SCON1, SCON2
The signals are output as VD1 and VD2, respectively.

VD1 and VD2 output from the word line drive voltage generation circuit 3 are sent to the pair of word line drive circuits 2. FIG. 2 shows a pair of word line driving circuits (here, an inverter circuit is taken as an example), and VD1 and VD2 are connected to the power supply thereof. In addition, the pair of word lines is obtained from the output of the inverter drive circuit to which VD1 and VD2 are connected as a power source. That is, by stepping down or boosting the power supply of the word line drive circuit at the above timing, boosted voltage or stepped down voltage can be separately obtained from the pair of word lines at the same timing.

On the other hand, the word line selection signal / WL input to the word line drive circuit 2 is obtained as the output of the decode circuit 6. Although not specifically shown, the decode circuit 6 may be composed of a commonly used CMOS NOR gate or NAND gate.

Next, the timing of each part will be described based on the timing chart shown in FIG. This timing chart shows an example of chip select (/ CS) access in boost mode. The address is fixed and / WE is fixed at "H".

When the TEST1 signal is "L", the chip is in the normal operation mode, and the selection potential of the pair of word lines is VDD.
Has become.

When the TEST1 signal is "H", the chip is in the test mode.

In this state, when the falling / reading mode of / CS is entered, the timing generation circuit 4 detects and CL
A pulse is generated as the M signal. CLM signal and TEST
Since the logic of 1 and TEST2 signal is taken, CLM
When the TEST2 signal is "L" in response to the signal pulse, S
A pulse is generated from CON1, and the TEST2 signal is "H".
At that time, a pulse is generated from SCON2. At the same time,
SCON1, SCON with a margin in reading time
2 has a secured pulse width. That is, the pulse width setting circuit 41 in FIG. 7 enlarges the SCON1 and SCON2 pulse widths. At the time of testing, strobes are made during this period and data judgment is performed. Then SCON
1 and SCON2 signal are received, boosted voltages are generated from VD1 and VD2, respectively. Meanwhile, the row address ADX is decoded to generate the word line selection signal / WL. / WL
Since the power supplies VD1 and VD2 of the word line drive circuit for receiving the data are generated as described above, the result WLA, WLB is S
A boosted voltage is obtained based on the CON1 and SCON2 signals. The read mode has been described above as an example.
Is "L" and the writing is started at the falling edge of / CS.

The timing of each part will be described with reference to the timing chart shown in FIG. This timing chart is
An example of address access at the start of writing by the fall of the / WE signal is shown. Further, the boost mode is set as in FIG.

Similar to FIG. 9, when the TEST1 signal is "H", the chip enters the test mode. TE for simplicity
The ST2 signal is fixed at "H" and the WLB boosting mode is set.

First, in the write mode based on the falling edge of the / WE signal, the falling edge of / WE is detected and C
Pulsed as LM. CLM signal and TEST
Since the logic of 1 and TEST2 signal is taken, WLB
The SCON2 signal that determines the boosting timing is generated as a pulse. At this time, at the same time, the pulse width is secured with a margin in the writing time. TEST2 signal is "
Since it is H ”, no pulse is generated from the SCON1 signal. Next, the SCON2 signal is received and a boosted voltage is generated from VD2. VD1 remains at the VDD potential. Meanwhile, the row address ADX is decoded and the word line selection signal is generated. / W
L is generated. Since the power supplies VD1 and VD2 of the word line driving circuit receiving / WL are generated as described above, the result W
A boosted voltage is obtained from LB based on the SCON2 signal. WLA becomes VDD voltage.

Next, in the address access mode, a change in the address signal is detected and an ATD pulse is issued.
Upon receiving the ATD signal, the CLM signal is generated as a pulse. Since the logic of the CLM signal and the TEST1 and TEST2 signals are taken, SC which determines the WLB boosting timing
The ON2 signal is generated as a pulse. At this time, at the same time, a pulse width is secured with a margin in the reading time. Since the TEST2 signal is "H", no pulse is generated from the SCON1 signal. Next, upon receiving the SCON2 signal, a boosted voltage is generated from VD2. VD1 remains at the VDD potential. On the other hand, the row address ADX is decoded to generate the word line selection signal / WL. Since the power supplies VD1 and VD2 of the word line drive circuit receiving / WL are generated as described above, the boosted voltage is obtained from the result WLB based on the SCON2 signal. WLA becomes VDD voltage.

The case of boosting the word line has been described above, but the same applies to the case of reducing the voltage.

[0050]

As described above, according to the present invention,
By testing the memory cells which are unstable but latched and take a long time, which does not become defective unless special disturb is applied, in an unstable state,
The effect is that it can be easily rejected as a defect.
That is, the test time can be shortened.

As shown in the means 3, even if a writing peculiarity such that the write margin is lost due to the deterioration of the transfer MOS transistor capability, it can be easily rejected as a failure without taking a complicated circuit configuration and layout. There is an effect.

As indicated by the means 4, the step-up / step-down mode can be realized without increasing the number of circuits in the chip, and as described above, the failure peculiar to writing can be easily rejected as a failure. There is.

As indicated by means 5, the test can be simplified by generating the timing inside the chip without inputting a complicated power supply signal from the outside.

Furthermore, since marginal defects can be rejected by a simple test, there is an effect that a highly reliable semiconductor memory device can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of means 1, 2, and 3 of the present invention.

FIG. 2 is a diagram showing an embodiment relating to means 4 of the present invention.

FIG. 3 is a diagram showing an embodiment relating to means 5 and 6 of the present invention.

FIG. 4 is a diagram showing an embodiment of a word line driving circuit according to the present invention.

FIG. 5 is a diagram showing an embodiment of a booster circuit according to the present invention.

FIG. 6 is a diagram showing an embodiment of a step-down circuit according to the present invention.

FIG. 7 is a diagram showing an embodiment of a step-up or step-down timing generation circuit according to the present invention.

FIG. 8 is a diagram showing an embodiment of an address buffer circuit according to the present invention.

FIG. 9 is a diagram showing a first timing according to the means 6 of the present invention.

FIG. 10 is a diagram showing a second timing according to the means 6 of the present invention.

FIG. 11 is a diagram showing a first conventional example according to the present invention.

FIG. 12 is a diagram showing a second conventional example according to the present invention.

FIG. 13 is a diagram showing memory cell characteristics according to the present invention.

[Explanation of symbols]

1 ・ ・ Memory cell group 2 ・ ・ Word line drive circuit 3 ・ ・ Boosted voltage or step-down voltage generation circuit 4 ・ ・ Boosted voltage or step-down voltage generation timing circuit 5 ・ ・ Address buffer circuit 6 ・ ・ Row address decode circuit 7 ・・ Operation mode switching circuit 41 ・ ・ Chip selection signal falling detection circuit 42 ・ ・ Write enable signal falling detection circuit 43 ・ ・ Address transition signal, write enable falling detection signal, chip selection signal falling detection signal synthesis circuit 44 ・・ Pulse width setting circuit 51 ・ ・ Address buffer circuit 52 ・ ・ Address transition detection circuit VDD ・ ・ Power supply GND ・ ・ Ground potential BL, / BL ・ ・ A pair of bit lines / WL ・ ・ Word line selection signals WLA, WLB, WL ..Word line PCC E signals L1, L2, L3, L4, M1, M2 ·· bit line load transistors I1, I2 · · memory cell driving transistor A1, A2 · · memory cell transfer transistors R1, R2 · · memory cell high resistance load transistor a1. a2 ・ ・ Memory cell store node VD, VD1, VD2 ・ ・ Word line drive circuit power supply WLM ・ ・ Word line group DECM ・ ・ Row address decode signal group ADXMO ・ ・ Internal row address signal group ADXMI ・ ・ External supply address signal group SCON , SCON1, SCON2 ・ ・ Word line step-up or step-down timing signal ATD ・ ・ Address transition detection signal CLM ・ ・ Step-up or step-down timing reference signal / CS ・ Chip select signal / WE ・ ・ Wight enable signal TEST1 ..WLA, WLB step-up (step-down) switching signals TEST3, TEST4 ..... Bit line load switching signal during TEST

Claims (6)

[Claims] 1. In a semiconductor memory device comprising a flip-flop type memory cell in which word lines connected to respective gates of a pair of transfer MOS transistors are separately arranged, a pair of word line potentials can take different values during a test. A semiconductor memory device characterized by the above. 2. The semiconductor memory device according to claim 1, wherein one word line potential is VDD potential and the other word line potential is boost VDD potential. 3. The semiconductor memory device according to claim 1, wherein one word line potential is VDD potential and the other word line potential is stepped down VDD potential. 4. A flip-flop type memory cell in which word lines connected to respective gates of a pair of transfer MOS transistors are separately arranged, a pair of word line drive circuits for driving the pair of word lines, and a pair of word lines. A first word line drive power supply externally supplied to one of the drive circuits, a second word line drive power supply externally supplied to the other, a word line drive power supply during normal operation, and a word line drive during test A semiconductor memory device, comprising: an operation mode switching circuit for switching between a power source and a power source. 5. A flip-flop type memory cell in which word lines connected to respective gates of a pair of transfer MOS transistors are separately arranged, a pair of word line driving circuits for driving the pair of word lines, and a pair of word lines. V on one side of the drive circuit
A semiconductor memory device comprising: a word line drive voltage generation circuit for generating a boosted voltage or a stepped down voltage on the other side of DD; and a timing generation circuit for generating a timing for generating a boosted voltage or a stepped down voltage. 6. The timing generation circuit according to claim 5,
A semiconductor memory device configured to generate a step-up voltage or a step-down voltage based on (at the time of testing) and (at the start of writing, at the start of chip select access, and at the start of address access).