JPH07201199A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To detect the whole memories as a defect memory to a memory cell group with imperfect operation by controlling a dummy word line level decision circuit through first, second pads and making dummy word line drive potential be a prescribed value. CONSTITUTION:A semiconductor integrated circuit is formed by a memory cell array 10 and a dummy cell part 11. Dummy word line pair DWL, anti-DWL in the cell part 11 are driven by a dummy word line drive circuit 12 of DWL potential control circuit 17a, a dummy word line drive system decision circuit 13 and a dummy word line level decision circuit 15a, etc. Respective source voltages for regular level operation and screening test are supplied to the circuit 12 according to the potential impressed to the pad 161 connected to the circuit 15a, and an operation source voltage with an optional level is supplied to the circuit 12 according to the potential impressed to the pad 162 at a screening mode time. Thus, at the time of a test in a wafer state, the whole memory cells for a memory cell group of a read margin are detected as the defect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (I
C), particularly I having a memory cell array and a sense amplifier for sense-amplifying read information of the memory cell
It relates to a means for controlling the read margin of the cell in C.

[0002]

2. Description of the Related Art An IC (for example, a memory IC) having a memory cell array and a bit line sense amplifier for sense-amplifying read information of a memory cell is a non-defective product in a first inspection process (so-called die sort process) after the wafer process is completed. We carry out sorting inspection of defective products. In the die sort process, the probe card needle is applied to the chip pad formed on the wafer, and the power, address, input data, control signal, etc. necessary for chip operation are given, and the current flowing into each needle and the output data The quality is judged and the good product is judged by comparing it with the expected value.

The die sort process is divided into many items, but it is generally roughly divided into (1) current test and (2) operation test. The operation test is performed on a chip that has passed the current test, and its purpose is to inspect whether the write / read operation of the memory cell is correctly performed.

The operation test is divided into several items. Power supply voltage, voltage / timing of input data, voltage / timing of address, data pattern to be written in memory cell (“0”, “1” written in memory cell plane)
Combination) and the like are combined for writing and reading to test whether the written data pattern is correctly read.

Although the process of manufacturing a memory IC is strictly controlled, some variation is still unavoidable. A slight variation in each process is accumulated until all the wafer process steps are completed, and this accumulated variation appears as a characteristic variation of the memory cells included in the memory IC after the wafer process. The characteristic distribution of the memory cells is considered to be divided into three groups as shown in FIG.

In FIG. 9, the distribution (1) is a healthy memory cell group,
Distribution (2) is a group of completely defective cells that cannot be read or written at all, and distribution (3) is a group of memory cells that can be read or written but whose operation is incomplete.

By the way, in the conventional die sort process, the memory cells of the group (2) can be easily removed. On the other hand, in the memory cell of the group (3), since the amount of information at the time of reading (the potential difference of the bit line pair in the case of voltage reading, the current difference of the bit line pair in the case of current reading) is small, Removal is not easy.

In particular, a dynamic memory (DRAM)
In the case of a 3D structure such as a stack type cell or a trench type cell due to the increase in capacity, a sufficient cell capacity due to a defective contact of the storage node of the stacked type cell or a defect of the trench hole of the trench type cell. It becomes difficult to secure the above, and as described above, since there is a probability that there are cells that are likely to become defective, as described above (3)
The problem of not being able to remove all the memory cells of a group becomes even more important.

In order to solve the above-mentioned problems, the "semiconductor integrated circuit" of Japanese Patent Application No. 3-304335 filed by the applicant of the present application allows a memory which has an incomplete operation during a screening test in a wafer state. It becomes possible to detect all memory cells as defective for the cell group, and even if the memory cells are highly integrated and miniaturized, the imbalance of the read margin of "1" and "0" data can be eliminated. Techniques have been proposed that allow for easy correction.

The semiconductor integrated circuit according to this proposal is, for example, as shown in FIG. 10, a memory cell array 10, sense amplifiers SA1 to SAn for sense-amplifying the read information of the memory cells MC of this memory cell array, and the above memory cell array. Complementary bit line pairs (BL1, / BL
1) to (BLn, / BLn) respectively corresponding to the capacitance C
The dummy word line (DWL1, / DWL1) is connected via the dummy cell part 11 and the dummy word line when the selected word line of the word lines WL1 to WLn of the memory cell array is activated. And a dummy word line potential control circuit 17 capable of arbitrarily controlling the driving method.

The dummy word line potential control circuit 17 has
A dummy word line drive circuit 12 connected to the dummy word lines DWL and / DWL, a dummy word line drive system determination circuit 13 for determining a dummy word line drive system by the dummy word line drive circuit 12, and a chip external The first pad 1 which gives the dummy word line drive system control potential applied from
4, a dummy word line level determining circuit 15 added to drive the dummy word lines DWL and / DWL at an arbitrary level, and a potential for controlling the dummy word line level determining circuit 15 is applied. Second pad 1
6 and.

FIG. 11 shows an example of the dummy word line potential control circuit 17 in FIG.

In the dummy word line potential control circuit 17, reference numeral 701 denotes the second pad 16 and the power supply potential (VC
C) High resistance connected between the node and 71, the second is the second
A current mirror load type CMOS differential amplifier circuit in which one input node is connected to the pad 16 is a source / drain 72 connected between the VCC node and the other input node of the differential amplifier circuit 71. , A P channel M whose gate is connected to one output node of the differential amplifier circuit 71.
The OS transistor 73 is a resistor connected between the other input node of the differential amplifier circuit 71 and the ground potential (VSS) node. As a result, the other input node of the differential amplifier circuit 71 has a potential Vout obtained by reducing the power supply potential Vcc.
Will output.

702 is a high resistance connected between the first pad 14 and the VSS node, 74 is an inverter having an input node connected to the first pad 14, and 75 is an output of the inverter 74 and a word. A two-input AND gate to which the line drive timing signal φWL is input, 76 is a two-input NAND gate to which the output of the AND gate 75 and a row address signal A0R for selecting the bit lines BL1 to BLn are input, and 77 The output of the NAND gate 76 is input, and the step-down potential Vout is used as a high potential side power source.
Is a CMOS inverter whose output is supplied to the dummy word line DWL.

Reference numeral 78 is a two-input NAND gate to which the output of the AND gate 75 and the row address signal / A0R for selecting the bit lines / BL1 to / BLn are input, and 79 is the output of the NAND gate 78. , A CMOS to which the step-down potential Vout is applied as a high potential side power source and the output of which is supplied to the dummy word line / DWL
It is an inverter.

In the circuit of FIG. 11, the second pad 16
Is at Vcc, Vcc appears at the other input node of the differential amplifier circuit 71, and this Vcc appears at the CMOS inverter 77,
It is provided as an operating power supply for 79.

In this state, if the first pad 14 is at VSS, the output of the inverter 74 is at "H" level.
As a result, when the word line drive timing signal φWL is activated, the dummy word line DWL or / DWL is activated according to the address signal A0R or / A0R. As a result, for example, as in the operation waveform shown in FIG. 12, the operation by the dummy word line driving method similar to the conventional one can be obtained.

On the other hand, when Vcc is applied to the first pad 14 from the outside to set the output of the inverter 74 to the "L" level, a dummy word different from the dummy word line driving system shown in FIG. The operation by the line driving method can be obtained.

On the other hand, in the screening test in the wafer state, the power supply potential V is externally applied to the second pad 16.
When an arbitrary potential equal to or lower than cc is given, a step-down potential Vout corresponding to the given potential appears at the other input node of the differential amplifier circuit 71, and this step-down potential Vout is given as an operating power supply for the CMOS inverters 77 and 79. To be In this case, the step-down potential Vou is set by the dummy word line driving method according to the potential (VSS or Vcc) of the first pad 14.
t is applied to the dummy word line DWL or / DWL.

As described above, by supplying the arbitrary step-down potential Vout to the dummy word line DWL or / DWL, the read margin of the cell is made strict (when the data stored in the memory cell is read, the bit line pair is read). It becomes possible to make it difficult to read because the potential difference or the current difference appearing becomes small).

Therefore, according to the DRAM of FIG. 10 described above, it becomes possible to tighten the data read margin in the screening test of the DRAM which has completed the wafer process, and the memory cell having a small data read margin becomes defective. Can be determined.

However, in the dummy word line potential control circuit 17 of FIG. 11 as described above, the through current is constantly flowing through the differential amplifier circuit 71 and the PMOS transistor 72 and the resistor 73 connected thereto, and the DRAM is The larger the capacity is, the larger the driving capability is required, and thus the through current is increasing.

[0023]

As described above, the conventional DRAM is provided with the dummy word line potential control circuit using the differential amplifier circuit, and when the read margin of the memory cell is tightened in the screening test in the wafer state. The through current flows through the dummy word line potential control circuit, and there is a problem that the through current increases as the capacity of the DRAM increases.

The present invention has been made to solve the above-mentioned problems, and it is possible to detect all memory cells as defective with respect to a memory cell group which is incomplete in operation during a screening test in a wafer state. Therefore, it is an object of the present invention to provide a semiconductor integrated circuit having a dummy word line potential control circuit which prevents a through current.

[0025]

In a semiconductor integrated circuit according to the present invention, memory cells are arranged in rows and columns, word lines commonly connected to memory cells in the same row and bit lines connected to memory cells in the same column. A first dummy word line is connected to one bit line of a complementary bit line pair of the memory cell array via a first capacitor, and the other bit line of the bit line pair has a second dummy word line. A dummy cell portion to which a second dummy word line is connected via a second capacitor and a dummy word for driving the dummy word line by a predetermined driving method when a selected word line of the memory cell array is activated. A line potential control circuit is connected to a complementary bit line pair of the memory cell array, and a sense amplifier for sense-amplifying the information read from the selected memory cell to the bit line. The dummy word line potential control circuit sets the dummy word line drive potential to the normal operation mode or the screening test mode in accordance with a predetermined first potential applied to the first pad from the outside of the integrated circuit chip. The dummy word line drive potential is controlled to an arbitrary level in accordance with the second potential applied to the second pad from outside the integrated circuit chip.

[0026]

The dummy word line potential control circuit is connected to the first pad for controlling the mode of the dummy word line drive potential and the second pad for controlling the dummy word line drive potential to an arbitrary level. ing.

As a result, in the screening test of the DRAM after the wafer process, the dummy word line drive potential is controlled in the screening test mode by the potential of the first pad, and the desired potential is applied to the second pad. As a result, the data read margin can be set strictly, and it becomes possible to detect all the memory cells as defective in the memory cell group in which the operation is incomplete.

Further, in the dummy word line drive potential control operation as described above, a through current does not flow in the word line potential control circuit, and even when the DRAM has a larger capacity and the dummy word line drive capability is increased. It becomes possible to suppress an increase in through current.

[0029]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a DRA according to the first embodiment of the present invention.
A part of M is shown.

The DRAM shown in FIG. 1 is different from the DRAM of the conventional example described with reference to FIG. 10 in part of the dummy word line potential control circuit and the other parts are the same.
The same parts as those in FIG. 10 are designated by the same reference numerals.

That is, the memory cell array 10 includes DRAM cells MC arranged in a matrix and cells MC in the same row.
To the word lines WL1 to WLm commonly connected to each other, and the bit lines BL1 and / B commonly connected to the cells MC in the same column.
L1, ~ BLn, / BLn.

Coupling capacitance type dummy cell section 11
Are bit lines BL1 to BL1 of the memory cell array MCA.
Dummy word line DWL via capacitance C one by one in BLn
, And one dummy word line / DWL is connected to each of the bit lines / BL1 to / BLn via a capacitor C. As these capacitors C, MOS capacitors or interlayer capacitors between the plate polysilicon and the gate electrode material are used.

The sense amplifiers SA1 to SAn are complementary bit line pairs (BL1, / B) of the memory cell array 10.
L1) to (BLn, / BLn) are respectively connected to sense and amplify the information read to the bit line from the memory cell of the selected row. In some cases, one sense amplifier may be switched and connected to a plurality of bit line pairs.

The dummy word line potential control circuit (DWL potential control circuit) 17a in the present invention includes a dummy word line drive circuit 12 connected to the dummy word lines DWL and / DWL, and the dummy word line drive circuit. The dummy word line drive system determination circuit 13 for determining the dummy word line drive system by 12, the first pad 161 to which a predetermined first potential is applied from the outside of the integrated circuit chip, and an arbitrary second potential are The dummy word line drive potential is switched to the normal operation mode or the screening test mode in accordance with the applied second pad 162 and the predetermined first potential applied to the first pad 161, and the second pad is controlled. A dummy word for controlling the dummy word line drive potential to an arbitrary level according to an arbitrary second potential applied to 162. Comprising a line-level determining circuit 15a.

The dummy word line level determination circuit 15a
Various configurations are conceivable. As an example thereof, the dummy word line drive circuit 12 is supplied with a normal level operation power supply voltage or a screening test level according to the first potential applied to the first pad 161. The operating power supply voltage is controlled to be switched and supplied, and the operating power supply voltage of an arbitrary level is supplied to the dummy word line drive circuit 12 according to the second potential applied to the second pad 162 in the screening test mode. Control (i.e., the dummy word lines DWL and / W depending on the second potential).
The drive voltage of DWL is controlled to an arbitrary level).

The dummy word line drive system decision circuit 13 in FIG. 1 is connected to the third pad 14, and the third word
In accordance with the potential of the pad 14 of FIG.
In order to drive the dummy word line drive circuit 12 according to this method, one of a plurality of dummy word line drive methods (for example, shown in FIGS. 12 to 17) shown in No. 4335 is selected. It is configured, and its details will be described later.

FIG. 2 shows a specific example of the dummy word line level determination circuit 15a and the dummy word line drive circuit 12 shown in FIG.

In FIG. 2, the dummy word line level determination circuit 15a has a switch PMOS transistor 21 whose source is connected to the power supply potential Vcc node and whose gate is connected to the first pad 161, and whose drain is Vcc.
Connected between the first pad 161 and the ground potential node, and an NMOS transistor 22 having a gate connected to the second pad 162 and a source connected to the drain of the PMOS transistor 21. A high resistance element R1 and a high resistance element R2 connected between the second pad 162 and the VSS node.

The dummy word line drive circuit 12 is supplied with the drain potential of the PMOS transistor 21 as an operating power supply, and inverts the signal Sa supplied from the dummy word line drive system determination circuit 13 to invert the dummy word line. Inverter 23 for supplying DWL, and the PMOS
The drain potential of the transistor 21 is supplied as an operating power supply, and the signal Sb supplied from the dummy word line drive system determination circuit 13 is inverted to invert the dummy word line / DW.
And an inverter 24 which supplies L.

Next, the operation of the dummy word line level determination circuit 15a in FIG. 2 will be described.

During normal operation, no voltage is applied to the first pad 161 and the second pad 162 from the outside,
Each is pulled down to the VSS potential (“0” level). As a result, the PMOS transistor 21 is on and the NMOS transistor 22 is off.

Therefore, the inverter 23 of the dummy word line drive circuit 12 is supplied with the VCC potential as the operating power supply,
Input signal S from the dummy word line drive system determination circuit 13
The potential (VCC or VSS) with the level of a inverted is supplied to the dummy word line DWL. Similarly, the inverter 24 of the dummy word line drive circuit 12 is also supplied with the VCC potential as the operating power supply, and the potential (VCC or VSS) obtained by inverting the level of the input signal Sb from the dummy word line drive system determination circuit 13 is used as the dummy word. Supply to line / DWL.

During the screening test, the VCC potential is applied to the first pad 161 and the desired potential VG is applied to the second pad 162. As a result, the PMOS transistor 21 is turned off and the NMOS transistor 22 is turned off.
Is turned on.

Therefore, the inverter 23 of the dummy word line drive circuit 12 operates as VG-VTHN (VTHN
Is a gate threshold voltage of the NMOS transistor 22), and the dummy word line potential VDW is obtained by inverting the level of the input signal Sa from the dummy word line drive system determination circuit 13.
("H" level is VG-VTHN, "L" level is VSS)
Are supplied to the dummy word line DWL.

In this case, the potential of VG-VTHN is PM.
Since it is applied to the drain of the OS transistor 21 and the source of the PMOS transistor of the CMOS inverter 23, the potential of VG-VTHN becomes smaller than the back gate bias (VCC in this example) of these PMOS transistors, that is, VG- It is set so that V THN ≤V CC.

Similarly, the inverter 24 of the dummy word line drive circuit 12 is also supplied with VG-VTHN as an operating power supply, and the dummy word line potential VDW is obtained by inverting the level of the input signal Sb from the dummy word line drive system determination circuit 13.
("H" level is VG-VTHN, "L" level is VSS)
Are supplied to the dummy word line / DWL.

That is, according to the DRAM of the above-described embodiment, the dummy word line drive potential is controlled in the screening test mode by applying a predetermined potential to the first pad 161 in the screening test of the DRAM after the wafer process. By applying a desired potential VG to the second pad 162, for example, it becomes possible to strictly set the read margin of "0" data, and a memory cell having a small read margin of "0" data can be provided. It can be determined as defective. Contrary to the above,
By strictly setting the read margin of "1" data, it is possible to determine that a memory cell with a small read margin of "1" data is defective.

Therefore, it becomes possible to tighten the read margin of the memory cells and detect all the memory cells as defective for the memory cell group whose operation is incomplete.

In the dummy word line drive potential control operation as described above, a through current does not flow through the word line potential control circuit 17a, and the dummy word line drive capability is increased as the DRAM becomes larger in capacity. However, it becomes possible to suppress the increase of the through current.

3 to 5 show modified examples of the dummy word line level determination circuit 15a in FIG.

Dummy word line level determination circuit 1 in FIG.
5a, compared with the dummy word line level determination circuit 15a shown in FIG. 2, the NMOS transistor 22 is omitted, the second pad 162 is directly connected to the drain of the PMOS transistor 21, and the high resistance element R2. Is V
The difference is that it is connected between the CC node and the second pad 162, and the other parts are the same, so the same reference numerals as in FIG. 2 are given.

This dummy word line level determination circuit 15a
In the normal operation, no voltage is externally applied to the first pad 161 and the second pad 162.
Pad 161 is pulled down to VSS potential and PMOS
Transistor 21 is on and second pad 162 is pulled up to the Vcc potential. As a result, the inverters 23 and 24 operate as Vcc as the operating power source.
The dummy word line drive system determination circuit 13 is supplied with a potential.
Corresponding to the input signals Sa and Sb from the dummy word lines DWL and / DWL to the dummy word line potential VDW.
("H" level is Vcc, "L" level is VSS).

During the screening test, the Vcc potential is applied to the first pad 161, the PMOS transistor 21 is turned off, and the desired potential VD is applied to the second pad 162. As a result, the inverters 23 and 24 are supplied with VD as an operating power supply, and the input signal Sa from the dummy word line drive system determination circuit 13 is supplied.
And dummy word lines DWL and /
DWL is a dummy word line potential VDW ("H" level is VD
, "L" level supplies VSS).

Dummy word line level determination circuit 1 in FIG.
5a is different from the dummy word line level determination circuit 15a shown in FIG. 3 in that the PMOS transistor 4 is provided between the second pad 162 and the drain of the PMOS transistor 21.
1 is inserted and connected between the source and drain, and a potential obtained by inverting the potential of the first pad 161 by the inverter 42 is applied to the gate of the PMOS transistor 41, except that the other is the same. The same reference numerals as those in 3 are attached.

Dummy word line level determination circuit 1 in FIG.
In 5a, during normal operation, the PMOS transistor 41 is controlled to the off state by the potential obtained by inverting the pull-down potential VSS of the first pad 161 by the inverter 42. And during the screening test, the first
The potential Vcc applied to the pad 161 of the inverter 42
The PMOS transistor 41 is controlled to be turned on by the inverted potential, the desired potential VD is applied to the second pad 162, and the potential VD is supplied as the operating power supply for the inverters 23 and 24.

In FIGS. 3 and 4, the potential VD
Must be set smaller than the back gate bias of the PMOS transistor (VCC in this example).

Dummy word line level determination circuit 1 in FIG.
5a is different from the dummy word line level determination circuit 15a shown in FIG. 4 in that the NMOS transistor 5 is provided between the second pad 162 and the drain of the PMOS transistor 21.
1 is inserted and connected between the drain and source, and the potential of the first pad 161 is directly applied to the gate of the NMOS transistor 51. Others are the same, so the same symbols as in FIG. Is attached.

Dummy word line level determination circuit 1 in FIG.
In 5a, in normal operation, the pull-down potential VSS of the first pad 161 controls the NMOS transistor 51 to be in the off state. At the time of the screening test, VG (for example, VCC +
The gate threshold voltage of the NMOS transistor 51 is applied to VTHN and VTHN, and the NMOS transistor 51 is controlled to be in the ON state by this applied potential, and the second pad 16
A desired potential VD is applied to 2 and the potential VVG-VTHN (VCC in this example) is supplied as an operating power supply for the inverters 23 and 24. In this case, the dummy word line potential VDW
Does not exceed VG-VTHN.

Further, as the dummy word line drive circuit 12, as shown in FIGS. 2 to 5, a Vcc node and a Vss node are provided.
A PMOS transistor TP and an NMOS transistor TN connected in series with the node,
OS transistor TP and NMOS transistor TN
CMOS inverters 23, 24 for supplying a drive signal to the dummy word line from the serial connection node (output node) of
In the case where is used, the dummy word line level determination circuit 15a can be modified and implemented as shown in FIGS. 6 to 8, for example.

That is, the dummy word line level determination circuit 15a shown in FIGS. 6 to 8 outputs the word line selection signal to the dummy word line drive circuit according to the first potential applied to the first pad 161. The normal operation mode supplied to the gates of both the PMOS transistor TP and the NMOS transistor TN of the circuit 12 or the word line selection signal is supplied only to the gate of the NMOS transistor TN,
The gate of the PMOS transistor TP is controlled to be switched to the screening test mode in which it is set to the "H" level.

FIG. 6 shows the dummy word line level determination circuit 1
5a and a part of the dummy word line drive circuit 12 (CMO
The S inverter 23) is shown. In the dummy word line level determination circuit 15a, the potential of the first pad 161 is the first
Of the high resistance connected between the Vcc node and the first pad 161 and the AND circuit 61 which receives the input signal Sa from the dummy word line drive system decision circuit to the second input node. Element R1, Vcc node and CMO
An NMOS transistor 62 connected between the output node of the S inverter 23 and the gate thereof is connected to the second pad 162, and a high resistance element R2 connected between the second pad 162 and the VSS node. The output of the AND circuit 61 is supplied to the gate of the PMOS transistor TP of the CMOS inverter 23.

In the dummy word line level determination circuit 15a shown in FIG. 6, the first pad 16 is used during normal operation.
No voltage is applied to the first and second pads 162 from the outside, the first pad 161 is pulled up to the Vcc potential, and the second pad 162 is pulled down to the VSS potential. As a result, the AND circuit 61 changes the input signal Sa to C
The state of supplying to the gate of the PMOS transistor TP of the MOS inverter 23 and the state of the NMOS transistor 62 are off. Therefore, the CMOS inverter 23
Supplies the potential obtained by inverting the level of the input signal Sa to the dummy word line DWL.

During the screening test, the VSS potential is applied to the first pad 161 and the desired potential VG is applied to the second pad 162. As a result, the output signal of the AND circuit 61 is always at "L" level, and the input signal S
a is a PMOS transistor T of the CMOS inverter 23
The state is not supplied to the gate of P. Further, the NMOS transistor 62 is in the on state. Therefore, CM
The OS inverter 23 receives the input signal Sa from the NMOS
When the transistor TN is in the off state, the dummy word line potential VDW is VG-VTHN (VTHN is NM).
The gate threshold voltage of the OS transistor 62) is supplied, and when the NMOS transistor TN is turned on by the input signal Sa, VSS is supplied as the dummy word line potential VDW.

In this case, the potential of VG-VTHN is CM.
Since it is applied to the drain of the PMOS transistor TP and the drain of the NMOS transistor TN of the OS inverter 23, the potential of VG-VTHN is the back gate bias of the PMOS transistor TP (VCC in this example).
It is necessary to set so as to be smaller than the back gate bias of the NMOS transistor TN (Vss in this example).

Similarly to the above, the dummy word line drive circuit 1
The second inverter 24 also receives the dummy word line potential V by the input signal Sb and the dummy word line level determination circuit 15a.
DW is decided.

Compared to the dummy word line level determination circuit 15a shown in FIG. 6, the dummy word line level determination circuit 15a shown in FIG. 7 is provided between the second pad 162 and the drain of the NMOS transistor TN. The high resistance element R2 and the NMOS transistor 62 are inserted and connected in series, and a potential obtained by inverting the potential of the first pad 161 by the inverter 63 is applied to the gate of the NMOS transistor 62, but otherwise the same. Therefore, the same reference numerals as those in FIG. 6 are given.

Dummy word line level determination circuit 1 in FIG.
In 5a, during normal operation, the first pad 161 is pulled up to the Vcc potential, and the AND circuit 61 is in a state of supplying the input signal Sa to the gate of the PMOS transistor TP of the CMOS inverter 23. Further, the NMOS transistor 62 is controlled to the off state by the potential VSS obtained by inverting the pull-up potential VCC of the first pad 161 by the inverter 63. Then, during the screening test, the output signal of the AND circuit 61 is always at the “L” level due to the potential VSS applied to the first pad 161, and the input signal Sa is not supplied to the gate of the PMOS transistor TP of the CMOS inverter 23. It becomes a state. Also, the applied potential V of the first pad 161
NM by the potential Vcc which is the SS inverted by the inverter 42
Since the OS transistor 62 is controlled to be in the ON state and the desired potential VD is applied to the second pad 162, the dummy word line potential VDW is set to V according to the input signal Sa.
Become SS or VD.

Compared to the dummy word line level determining circuit 15a shown in FIG. 7, the dummy word line level determining circuit 15a shown in FIG. 8 uses a PMOS transistor 64 instead of the NMOS transistor 62, and corresponds to this. The inverter 63 is omitted, and the potential of the first pad 161 is applied to the gate of the PMOS transistor 64. The other parts are the same, and the same reference numerals as in FIG. 7 are given.

Dummy word line level determination circuit 1 in FIG.
Since the operation of 5a is almost the same as the operation of the dummy word line level determination circuit 15a in FIG. 7, its description is omitted.

12 to 17 show some different examples of the dummy word line drive system controlled by the DWL line drive system determination circuit 13 in FIG. However, here, for simplification of the drawing, only the normal operation in which the VCC potential is given from the dummy word line level determination circuit 15a as the operation power supply of the dummy word line drive circuit 12 is shown, but the screening test Sometimes the dummy word line drive potential is different.

12 to 17, Vcc is a power supply potential, Vcc / 2 is a bit line precharge potential, WL is a word line in a selected row, DWL is one dummy word line, and / DWL is another dummy. A word line, BL is one bit line connected to the cells of the selected row, / BL is the other bit line complementary to the bit line BL (the capacitance C selected by the dummy word line DWL is Connected bit line). vn is the word line W of the selected row
When the potential of L rises, the gate of the cell MC of the selected row
The potential due to the coupling noise generated in the one bit line BL through the drain capacitance, vd is the potential due to the coupling noise generated in the other bit line / BL by raising the potential of the dummy word line DWL, v1 Is the amount of change in the signal potential that appears when the "1" data of the selected cell MC is read to the bit line BL, and v0 is the "0" data of the selected cell MC that is read to the bit line BL. It is the amount of change in the signal potential that appears when

The drive system shown in FIG. 13 uses the selected word line W.
In this method, both dummy word lines DWL and / DWL are kept inactive when L is activated. That is, the bit line pair (B
After the precharge / equalized state of the potentials (L, / BL) is released, the word line WL of the selected row rises to the boosted potential. When the potential of the word line WL rises, a potential vn due to coupling noise is generated in one bit line BL through the gate-drain capacitance of the cell in the selected row. Then, data is read from the cell of the selected row to one bit line BL, and the bit line pair (BL, /
When a potential difference occurs in BL), the sense amplifier operates,
One potential of the bit line pair (BL, / BL) is pulled down and the other potential is pulled up.

In this driving method, the potential of one bit line BL is raised by the potential vn due to the coupling noise from the word line WL generated at the rise of the word line potential, but the other bit line / BL is dummy. Word line DWL
Since the potential vd due to the coupling noise from 1 does not appear, v1> v0.

Compared to the driving method shown in FIG. 13, the driving method shown in FIG. 14 maintains the potential of the dummy word line / DWL at the “H” level and activates the dummy word line DWL when the selected word line WL is activated. The difference is that the potential of is changed from "H" to "L", and the others are the same.

In this driving method, the potential of one bit line BL rises by the potential vn due to the coupling noise from the word line WL generated when the word line potential rises, and at the same time the potential of the dummy word line DWL falls. Since the potential of the other bit line / BL is lowered by the potential vd (= -vn) due to the coupling noise from the dummy word line DWL generated at the time, v1 >> v0.

Compared to the driving method shown in FIG. 13, the driving method shown in FIG. 15 keeps the potential of the dummy word line DWL at the “L” level when the selected word line WL is activated and keeps the dummy word line / DWL. The difference is that the potential of is changed from "L" to "H", and the other points are the same.

In this drive system, the potential of one bit line BL rises by the potential vn due to the coupling noise from the word line WL generated at the rise of the word line potential, and at the same time the potential of the dummy word line / DWL rises. Since the potential of one bit line BL is increased by the potential vd (= vn) due to the coupling noise from the dummy word line / DWL generated when the voltage rises, v1 >> v0.

Compared to the driving method shown in FIG. 13, the driving method shown in FIG. 16 maintains the potential of the dummy word line DWL at the “H” level and activates the dummy word line / DWL when the selected word line WL is activated. The difference is that the potential of is changed from "H" to "L", and the others are the same.

In this driving method, the potential vn due to the coupling noise from the word line WL generated at the rise of the word line potential is converted from the dummy word line / DWL generated when the potential of the dummy word line / DWL falls. Since this is canceled by the potential vd (= -vn) due to the coupling noise of, v1 = v0.

Compared to the driving method shown in FIG. 13, the driving method shown in FIG. 17 changes the potential of the dummy word line DWL from “H” to “L” and activates the dummy when the selected word line WL is activated. The other point is the same except that the potential of the word line / DWL is changed from "L" to "H".

In this driving method, the potential of one bit line BL is raised by the potential vn due to the coupling noise from the word line WL generated at the rise of the word line potential, and the potential of the dummy word line / DWL is raised. One bit line BL corresponding to the potential vd (= vn) due to the coupling noise from the dummy word line / DWL
At the same time that the potential of the other bit line / BL lowers by the potential vd (= -vn) due to the coupling noise from the dummy word line DWL generated when the potential of the dummy word line DWL falls. , V1 >> v
It becomes 0.

18 to 21 show the above-mentioned Japanese Patent Application No. 3-30.
12-17, as disclosed in US Pat.
Some different examples of the dummy word line drive system determination circuit 13 and the dummy word line drive circuit 12 controlled by the dummy word line drive system determination circuit 13 which can select any of the dummy word line drive systems shown in FIG.

In the DWL potential control circuit shown in FIG. 18, 30 is a high resistance connected between the third pad 14 and the ground potential node, 31 is an inverter whose input node is connected to the pad 14 and 32 is Two-input AND gates to which the output of the inverter 31 and the word line drive timing signal φWL are input, 33 are bit lines BL1 to BLn
A two-input NAND gate to which the row address signal A0R for selecting the system and the output of the AND gate 32 are input, 23 is an inverter that inverts the output of the NAND gate 33 and supplies the inverted data to the dummy word line DWL, and 35 is A two-input NAND gate to which the row address signal / A0R for selecting the bit lines / BL1 to / BLn and the output of the AND gate 32 are input, and 24 is the output of the NAND gate 35 to invert the dummy word line. / DW
It is an inverter that supplies L.

In this circuit, when the pad 14 is at the ground potential, the output of the inverter 31 is at "H" level, and the word line drive timing signal φWL is activated (in this example, it becomes "H" level). , The dummy word line DWL or / D depending on the address signal A0R or / A0R
Activate WL. This operation corresponds to the dummy word line driving method as shown in FIG.

On the other hand, if an “H” level signal is externally applied to the pad 14 to keep the output of the inverter 31 at the “L” level, even if the word line drive timing signal φWL is activated, the dummy signal is generated. Word line DWL, / DW
Since both L are kept in the inactive state (“L” level in this example), the operation by the dummy word line driving method as shown in FIG. 13 can be obtained.

In the DWL potential control circuit shown in FIG. 19, 30 is a high resistance connected between the third pad 14 and the ground potential node, 31 is an inverter whose input node is connected to the pad 14, and 36 is The output of the inverter 31 and the word line drive timing signal φWL and the row address signal A0R for selecting the bit lines BL1 to BLn are input, and the output thereof is the dummy word line D.
A 3-input NAND gate supplied to WL, 37 is an output of the inverter 31 and a word line drive timing signal φ
This is a three-input NAND gate to which a row-system address signal / A0R for selecting the WL and bit lines / BL1 to / BLn system is input and the output thereof is supplied to the dummy word line / DWL.

In this circuit, when the pad 14 is at the ground potential, the output of the inverter 31 is at "H" level, and when the word line drive timing signal φWL is activated,
Since the dummy word line DWL or / DWL is activated according to the address signal A0R or / A0R, the operation according to the dummy word line driving method as shown in FIG. 14 can be obtained.

On the other hand, if an "H" level signal is applied to the pad 14 from the outside to keep the output of the inverter 31 at the "L" level, even if the word line drive timing signal φWL is activated, the dummy Word line DWL, / DW
Since both L are kept inactive, the operation according to the dummy word line driving method as shown in FIG. 13 can be obtained.

In the DWL potential control circuit shown in FIG. 20, 40 is a high resistance connected between the third pad 14 and the ground potential node, 41a is an inverter whose input node is connected to the pad 14, and 41b is Inverter 4
1a output (control signal φA) is inverted to invert control signal φ
An inverter that generates B, and 42 are bit lines BL1 to BL
A two-input NAND gate to which the row address signal A0R and the word line drive timing signal φWL for selecting the n system is input, and the output of the NAND gate 42 is input to 43, which operates by the complementary control signals φB and φA. Is controlled by a clocked inverter, 44 is an inverter to which the output of the NAND gate 42 is input, 45 is an input to the output of the inverter 44, and the complementary control signal φA
Is a clocked inverter whose operation is controlled by φB and φB. The outputs of the clocked inverter 45 and the clocked inverter 43 are wired-OR connected and supplied to the dummy word line DWL. Four
Reference numeral 6 is a two-input NAND gate to which the row address signal / A0R for selecting the bit lines / BL1 to / BLn and the word line drive timing signal φWL are input, and 47 is the output of the NAND gate 46 and is complementary. A clocked inverter whose operation is controlled by the general control signals φB and φA, 48 is an inverter to which the output of the NAND gate 46 is input, 49 is an output from the inverter 48, and is supplied by the complementary control signals φA and φB. It is a clocked inverter whose operation is controlled. The outputs of the clocked inverter 49 and the clocked inverter 47 are wired-OR connected and supplied to the dummy word line / DWL.

In this circuit, when pad 14 is at the ground potential, control signals .phi.A and .phi.B correspond to "H".
/ It is at "L" level. As a result, when the word line drive timing signal φWL is activated, the address signal A
The dummy word line DWL or / DWL is activated according to 0R or / A0R. This operation corresponds to the dummy word line driving method as shown in FIG.

On the other hand, by applying an "H" level signal to the pad 14 from the outside, the control signals φA and φB are applied.
Corresponding to "L" / "H" level, when the word line drive timing signal φWL is activated, the operation by the dummy word line drive system as shown in FIG. 14 is obtained.

In the DWL potential control circuit shown in FIG. 21, 50 is a high resistance connected between the third pad 14 and the ground potential node, 51a is an inverter whose input node is connected to the pad 14, and 51b is Inverter 5
1a output (control signal φA) is inverted to invert control signal φ
An inverter that generates B, 52 is the bit lines BL1 to BL
A row-system address signal A0R for selecting the n-system is inputted to one end, and a CMOS transfer gate whose operation is controlled by the complementary control signals .phi.B and .phi.A, and 53 selects the bit line / BL1 to / BLn system. A row-system address signal / A0R for inputting to one end, and its operation is controlled by the complementary control signals φA and φB.
These are CMOS transfer gates, and the outputs of these CMOS transfer gates 52 and 53 are wired-OR connected. Reference numeral 54 is a two-input AND gate to which the wired OR output and the word line drive timing signal φWL are input and which supplies the output to the dummy word line DWL. 55 receives the address signal A0R at one end,
A CMOS transfer gate whose operation is controlled by the complementary control signals φA and φB, 56 receives the address signal / A0R at one end, and the complementary control signal φ
These are CMOS transfer gates whose operations are controlled by B and φA, and the outputs of these CMOS transfer gates 55 and 56 are connected by wired OR. Reference numeral 57 is a two-input AND gate to which the wired OR output and the word line drive timing signal φWL are input and which supplies the output to the dummy word line / DWL.

In this circuit, when pad 14 is at the ground potential, control signals .phi.A and .phi.B correspond to "H".
/ It is at "L" level. As a result, when the word line drive timing signal φWL is activated, the address signal A
The dummy word line DWL or / DWL is activated according to 0R or / A0R. This operation corresponds to the dummy word line driving method as shown in FIG.

On the other hand, by applying an "H" level signal to the pad 14 from the outside, the control signals φA and φB are applied.
Corresponding to "L" / "H" level, when the word line drive timing signal φWL is activated, the operation by the dummy word line drive system as shown in FIG. 15 is obtained.

The present invention is not limited to the above embodiment, but various modifications such as those disclosed in Japanese Patent Application No. 3-304335 are possible.

That is, by using a plurality of pads 14 for controlling the dummy word line drive system, the dummy word line drive system determination circuit 13 controls so that three or more types of dummy word line drive systems can be selected. It is possible.

The dummy word line is changed so that the capacitance of the dynamic memory cell and the transfer gate MOS transistor are connected in series to the bit line, and the dummy word line drive system is changed accordingly. Is possible.

[0099]

As described above, according to the IC of the present invention,
During the screening test in the wafer state, all the memory cells can be detected as defective with respect to the memory cell group having a small read margin (that is, incomplete operation). As a result, the efficiency of the test can be improved, the defect occurrence rate after packaging can be reduced, the package material and the inspection cost can be saved, and the reliability defect such as a defect at the user's hand can be reduced. Less worries about problems.

Further, since it is possible to prevent the through current from flowing in the dummy word line potential control circuit, it is possible to suppress the increase in the through current even when the dummy word line driving capability is increased as the DRAM becomes larger in capacity. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a DWL level determination circuit and a DWL drive circuit in FIG.

FIG. 3 is a circuit diagram showing another example of the DWL level determination circuit in FIG.

FIG. 4 is a circuit diagram showing still another example of the DWL level determination circuit in FIG.

5 is a circuit diagram showing still another example of the DWL level determination circuit in FIG.

6 is a circuit diagram showing still another example of the DWL level determination circuit in FIG.

FIG. 7 is a circuit diagram showing still another example of the DWL level determination circuit in FIG.

FIG. 8 is a circuit diagram showing still another example of the DWL level determination circuit in FIG.

FIG. 9 is a diagram showing a distribution state of characteristic variations of memory cells included in a DRAM after a wafer process.

FIG. 10 is a circuit diagram showing a part of a conventional DRAM.

11 is a circuit diagram showing an example of a DWL potential control circuit in FIG.

12 is a voltage waveform diagram showing an example of a read operation of the DRAM of FIG.

13 is a voltage waveform diagram showing another example of the read operation of the DRAM of FIG.

14 is a voltage waveform diagram showing still another example of the read operation of the DRAM of FIG.

15 is a voltage waveform chart showing still another example of the read operation of the DRAM of FIG.

16 is a voltage waveform chart showing still another example of the read operation of the DRAM of FIG.

17 is a voltage waveform chart showing still another example of the read operation of the DRAM of FIG.

FIG. 18 is a DWL drive system determination circuit and DW in FIG.
FIG. 6 is a circuit diagram showing an example of an L drive circuit.

FIG. 19 is a DWL drive system determination circuit and DW in FIG.
The circuit diagram which shows the other example of the L drive circuit.

FIG. 20 is a DWL drive system determination circuit and DW in FIG.
The circuit diagram which shows the further another example of the L drive circuit.

FIG. 21 is a DWL drive system determination circuit and DW in FIG.
The circuit diagram which shows the further another example of the L drive circuit.

[Explanation of symbols]

10 ... Memory cell array, 11 ... Dummy cell section, 12 ...
DWL drive circuit, 13 ... DWL drive system determination circuit, 14
... third pad, 15a ... DWL level determination circuit, 16
1 ... 1st pad, 162 ... 2nd pad, 17a ... D
WL potential control circuit, 23, 24 ... CMOS inverter,
MC ... Memory cell, WL, WL1 to WLm ... Word line,
(BL, / BL), (BL1, / BL1) to (BLn,
/ BLn) ... Bit line pair, C, C0, C1 ... Dummy cell capacitance, DWL, / DWL ... Dummy word line, SA1 to S
An ... Bit line sense amplifier.

Claims (3)

[Claims] 1. A memory cell array in which memory cells are arranged in rows and columns and has word lines commonly connected to memory cells in the same row and bit lines connected to memory cells in the same column, and a memory cell array complementary to the memory cell array. A first dummy word line is connected to one bit line of the bit line pair via a first capacitance, and the other dummy bit line is connected to the other bit line of the bit line pair via a second capacitance. A dummy cell part connected to the memory cell array, a dummy word line potential control circuit for driving the dummy word line by a predetermined driving method when a selected word line of the memory cell array is activated, and a complementary cell array of the memory cell array. A bit line pair, and a sense amplifier for sense-amplifying the information read from the selected memory cell to the bit line, the dummy word line potential Control circuit comprises a dummy word line drive circuit for driving the dummy word line, the integrated circuit the second to the first pad and the optional second potential the first potential from the outside of the chip of the predetermined is applied is applied
And a predetermined first potential applied to the first pad, the dummy word line drive potential is controlled to be switched to the normal operation mode or the screening test mode and applied to the second pad. And a dummy word line level determination circuit for controlling the dummy word line drive potential to an arbitrary level according to the second potential of the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the dummy word line level determination circuit sets a normal level to the dummy word line drive circuit according to a first potential applied to the first pad. Control is performed so as to switch and supply the operating power supply voltage or the operating power supply voltage at the screening test level, and the dummy word line drive circuit is arbitrarily supplied according to the second potential applied to the second pad in the screening test mode. A semiconductor integrated circuit characterized by being controlled so as to supply a level operation power supply voltage. 3. The semiconductor integrated circuit according to claim 1, wherein the dummy word line drive circuit has a PMOS transistor and an NMOS transistor connected in series between a power supply voltage node and a ground potential node, and the PMOS is provided.
A drive signal is supplied to the dummy word line from a serial connection node of a transistor and an NMOS transistor, and the dummy word line level determination circuit is responsive to a first potential applied to the first pad to select a word line selection signal. To the gates of both the PMOS transistor and the NMOS transistor of the dummy word line drive circuit, or to supply the word line selection signal only to the gate of the NMOS transistor of the dummy word line drive circuit, A semiconductor integrated circuit characterized by switching control to a screening test mode in which a gate of a PMOS transistor of a drive circuit is set to an "H" level.