JPH09162365A - Dynamic random access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make effective screening of a device which is for actualizing potential defects in an insulating film, etc., of a memory capacitor. SOLUTION: At a normal operating mode, only one of pairs of bit lines BL0-BL3, BL0-BL3 is connected to data lines DL, DL by decoded address signals Y0-Y3. At a stress application mode, when a stress application signal BTM becomes '1', all the bit lines BL0-BL3, BL0-BL3 are connected to the data line DL or DL and some of them are selected by word lines WL0-WL3 and then bit data is written for applying stress to four memory cells MC at the same time. By this method, the bit data for applying stress can be written efficiently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell using memory capacitors arranged in a matrix, which stores bit data by accumulated charges, selected by a word line driven by a row decoder and a column selector. The present invention relates to a dynamic random access memory which is selected by a bit line, and which performs write access and read access through the bit line. Particularly, it relates to an insulating film forming a memory capacitor and a gate oxide film of an access transistor. In order to make a physical defect manifest, stress is applied by actually applying a voltage to these insulating film and oxide film, etc. When screening a device, by efficiently applying the voltage, the initial defect Dynamic random access system that enables efficient screening. It related to Li.

[0002]

2. Description of the Related Art Conventionally used RAM (random
access memory is a dynamic random access memory (DRA).
Called M). In this DRAM, the charge accumulated in the memory capacitor of each memory cell causes
Store bit data. In a DRAM, bit data is stored depending on the presence / absence of charge accumulated in a memory capacitor and the amount of charge. In a DRAM, such memory cells arranged in a matrix are selected by a word line driven by a row decoder and a bit line selected by a column selector, and write access and read are performed via the bit line. Access and further refresh operations are performed.

In the DRAM, the accumulated charge corresponding to the bit data to be stored is a MOS (metal oxide semiconductor).
) It decreases over time due to transistor leakage current and recombination on the semiconductor substrate surface. For this reason, D
The RAM is characterized in that the refresh operation is performed on each memory cell at a constant cycle.

FIG. 1 is a block diagram showing a structure of a general DRAM which has been conventionally used.

In FIG. 1, memory cells MC are arranged in a matrix to form a memory matrix. For such a memory matrix, word lines WL0 to WL3 driven by row decoders, not shown in FIG. 1, and bit lines BL0 to BL3 selected by the column selector 12 (BL0 bar). ~ (BL
3 bar), a desired memory cell is selected, and write access and read access are performed through the bit lines BL0 to BL3 and (BL0 bar) to (BL3 bar).
Alternatively, the refresh operation is accessed.

At the time of write access, the input data DI is the input buffer 22 and the data line DL,
The pair of bit lines BL0 to BL0 which are input to the column selector 12 via (DL bar) and are selected by the column selector 12.
It is transmitted to BL3, (BL0 bar) to (BL3 bar).

On the other hand, in the read access, the bit data stored in the desired memory cell MC to be read is the bit line BL selected by the column selector 12.
0 to BL3, (BL0 bar) to (BL3 bar), the data is input to the column selector 12, the data line DL, (DL bar) and the read circuit 24 to the outside of the DRAM, and the bit is output data DO. The data is read. In such a read access, the bit line BL
0 to BL3, (BL0 bar) to (BL3 bar),
The bit data stored in the selected memory cell MC is amplified by the sense amplifier SA controlled by the sense signal SE output from the sense amplifier timing circuit 14.

Here, the memory cell MC shown in FIG.
Is the access transistor TG, as shown in FIG.
And a memory capacitor CM.
The cross section of such a memory cell MC on the integrated circuit is as shown in FIG. 5, for example. Here, Vp is a plate potential, for example, the plate voltage supply circuit 1 of FIG.
Powered by 6A.

Here, in FIG. 5, reference numerals 32, 34,
The access transistor TG shown in FIG. 2 is formed on the semiconductor substrate 1 by 36 and 42. Reference numerals 32 and 34 are a source region or a drain region.
Reference numeral 36 is a gate. Reference numeral 42 is an insulating film, which is a gate oxide film. Further, in FIG. 5, reference numeral 34,
The memory capacitor CM of FIG. 2 is formed on the semiconductor substrate 1 by 44 and 38. Here, reference numerals 34 and 3
Reference numeral 8 serves as an electrode of the memory capacitor CM. Also, reference numeral 4
Reference numeral 4 is an insulating film.

Here, if there is any defect in the insulating films 42 and 44, various obstacles will occur in the operation of the DRAM. For example, if there is a defect in the insulating film of reference numeral 44 and the electrodes of reference numerals 34 and 38 are electrically connected, it becomes impossible to store the accumulated charges for storing bit data.

The defects of such a DRAM include a manifested defect which has already caused some kind of failure and a potential defect which causes some kind of failure in the future although no actual failure has occurred yet. is there. This potential defect is, for example, deterioration of the insulating film of reference numeral 44 in FIG. 5, and the deterioration is promoted when it is used for a long time, and finally the electrodes of reference numerals 34 and 38 are electrically connected. There is something that causes an actual obstacle.

Generally, in order to ensure the reliability of the semiconductor device, it is necessary to screen the semiconductor device having such a potential defect. The screening is to expose a latent defect as an actual defect and expose the latent defect to remove a semiconductor device having the latent defect.

Further, as such screening,
There are an electric field acceleration method and a temperature acceleration method. Further, burn-in, which realizes these electric field acceleration method and temperature acceleration method at the same time, is often used.

In the electric field acceleration method, screening is performed while increasing the voltage applied to the memory capacitor of the memory cell as compared with that during normal operation. In the DRAM, during normal operation, a potential (Vcc / 2) that is half the power supply voltage Vcc is applied to the plate forming the capacity of the memory capacitor of the memory cell, that is, the electrode indicated by reference numeral 38 in FIG. Is common. In such a DRAM, in the stress application mode for screening by the electric field acceleration method, the potential applied to such a plate of the memory capacitor of the memory capacitor is higher than that of the potential applied to (Vcc / 2) during normal operation. A potential that causes a large potential difference between the electrodes is applied, for example, the potential of the voltage Vcc or the ground Vss is applied to the plate. Further, in such an electric field acceleration method, for example, while a large potential difference is generated between the electrodes of the memory capacitor, all the memory cells are sequentially scanned and accessed in the address order, so that the word lines are sequentially driven.

Now, consider the above-mentioned normal operation mode. In the normal operation mode, the plate potential is set to (V
cc / 2). Then, when writing "1" bit data to the memory cell, the charge storage node 34 in FIG. 5 becomes Vcc, so that the voltage (potential difference) applied across the insulating film of the memory capacitor is (Vcc / 2). On the other hand, when "0" bit data is written, the charge storage node becomes Vss (0V), so the voltage applied across the insulating film of the memory capacitor is (-(V
cc / 2)). Therefore, the stress applied to the insulating film of the memory capacitor in the normal operation mode is (Vc
c / 2).

On the other hand, consider the above-mentioned stress application mode in which the plate voltage Vp is Vcc as shown in FIG. 3, for example. In this case, it is as follows. That is,
When bit data of "1" is written in the memory cell, the charge storage node becomes Vcc, so the voltage applied across the insulating film of the memory capacitor becomes 0V. On the other hand, when "0" bit data is written, the charge storage node becomes Vss (0V), so the voltage applied across the insulating film of the memory capacitor becomes Vcc. Therefore, when the plate voltage Vp is set to Vcc in this way, the stress applied to the insulating film of the memory capacitor is Vcc.

Next, consider the above-mentioned stress application mode in which the plate potential is Vss. In this case, it is as follows. That is, when "1" bit data is written in the memory cell, the charge storage node becomes Vcc, so the voltage applied across the insulating film of the memory capacitor becomes Vcc. On the other hand, when "0" bit data is written, the charge storage node becomes 0V, so the voltage applied across the insulating film of the memory capacitor becomes 0V. Therefore, when the plate potential Vp is Vss as described above, the stress of the insulating film of the memory capacitor is Vcc.
Becomes

As described above, when the plate potential of Vcc or Vss is applied in the stress application mode as shown in FIGS. 3 and 4, the stress twice as much as that in the normal operation shown in FIG. 2 is applied to the memory capacitor. It can be applied to the insulating film. Therefore, even when a potential defect exists in the insulating film, the stress can be exposed more efficiently by the stress stronger than that in the normal operation in the stress application mode, and the screening efficiency can be improved. You can

[0019]

Here, in the memory capacitor of the memory cell as shown in FIGS. 2 to 5, latent defects start to become apparent and the insulating film of the memory capacitor begins to break down, Consider a case where a minute leak current starts to flow in the insulating film.

In the electric field acceleration method such as DRAM burn-in, the memory cells are sequentially accessed in the order of addresses to sequentially write bit data of "1" or "0". Therefore, during the writing of bit data in each memory cell, that is, between the writing and the next writing, the charge storage node of the memory capacitor is in a floating state, and the voltage applied to the insulating film of the memory capacitor is It depends only on the stored charge of the memory capacitor.

Here, when the latent defect of the insulating film begins to become apparent and a minute leak current flows in the insulating film, the stored charge of such a memory capacitor is lost, and thus the insulation of the memory capacitor is lost. The voltage applied to the membrane is relieved and the stress is relieved. Therefore, with such a minute leak current, the manifestation of latent defects is alleviated, and the insulating film that has begun to break down cannot be completely broken down, or the insulating film is completely broken down. It takes a very long time to get destroyed.

In this electric field acceleration method,
While repeatedly writing the bit data sequentially to all the memory cells, the refresh operation is performed on the memory cells belonging to the word line in the same row as the cells to be accessed. However, if a small leak current flows in the insulating film of the memory capacitor and the bit data to be stored is lost or is about to be lost, the stored charge will not be supplemented again in the memory capacitor even by the refresh operation, and The voltage applied to the insulating film of the capacitor is not maintained and stress is no longer maintained. Until the bit data in the address order is actually written to the memory cell again, the memory cell remains in a stress-free state.

The present invention has been made to solve the above-mentioned problems of the prior art, and is intended to make latent defects relating to an insulating film forming a memory capacitor, a gate oxide film of an access transistor, and the like visible. Provided is a DRAM capable of efficiently screening an initial failure by efficiently applying a voltage when screening a device that is actually stressed by applying a voltage to an insulating film or an oxide film. The purpose is to do.

[0024]

SUMMARY OF THE INVENTION According to the present invention, a memory cell using memory capacitors arranged in a matrix for storing bit data by accumulated charges is formed by a word line driven by a row decoder and a column selector. In a dynamic random access memory which is selected by a selected bit line and is accessed for writing and reading through the bit line, a normal operation mode or a stress application mode for screening a potential defect is selected. A mode selection circuit that makes either setting, and a normal plate potential is applied in the normal operation mode, while a screening in which a larger potential difference occurs in the memory capacitor in the stress application mode than when the normal plate potential is applied Plate for applying plate potential Position a supply circuit, larger than the number of bits to be selected during a write access of the normal operation mode,
The above problem is solved by providing a screening write circuit that simultaneously writes bit data with accumulated charges to the memory capacitor.

Further, in the DRAM, the screening write circuit uses all bit lines provided in the dynamic random access memory at least at the same time for use in write access, so that more memory capacitors can be used. At the same time, a more specific configuration of the screening write circuit, which can solve the above problems by writing bit data with accumulated charges, has been found.

The operation of the present invention will be briefly described below with reference to the drawings.

FIG. 6 is a block diagram showing the basic structure of the invention application portion of the DRAM of the present invention.

In FIG. 6, the memory cell matrix section 3 stores bit data by accumulated charges.
Memory cells using memory capacitors are arranged in a matrix. Such a memory cell is selected and accessed by a word line and a bit line provided in the memory cell matrix section 3. Specifically, a desired memory cell is selected by a word line driven by a row decoder (not shown) and a bit line selected by a column selector in the input / output circuit 18, and the selected memory cell is passed through the bit line. Write access and read access are performed.

The mode selection circuit 15, the plate voltage supply circuit 16 and the screening write circuit 17 shown in FIG. 6 provided for such a memory cell matrix section 3 are characteristic of the present invention.

First, the mode selection circuit 15 is in either a normal operation mode for performing a normal write access or a read access, or a stress application mode for screening a potential defect such as the electric field acceleration method described above. Set the mode. This setting is the DRA
You may perform according to the input from the outside of M. The setting result is output to the plate voltage supply circuit 16 and the screening writing circuit 17.

Next, the plate voltage supply circuit 16 supplies two types of plate potentials as described above. Specifically, the plate voltage supply circuit 16 supplies a plate potential of (Vcc / 2) as shown in FIG. 2 described above, for example, as the normal plate potential in the normal operation mode. On the other hand, in the stress application mode, the plate voltage supply circuit 16 uses, for example, Vc of FIG. 3 described above as a screening plate potential applied with a larger potential difference to the insulating film of the memory capacitor than when supplying the normal plate potential.
c or the plate potential of Vss in FIG. 4 described above is supplied.

The screening write circuit 17 simultaneously writes bit data with accumulated charges to the memory capacitors of a plurality of memory cells, the number of which is larger than the number of bits selected during write access in the normal operation mode. By thus writing the bit data with accumulated charges, a voltage is applied to the insulating film of the memory capacitor of the memory cell, and stress is applied.

Here, in the present invention, the writing of the bit data having the accumulated charge is the writing of the bit data of "0" if there is a plate potential as shown in FIG. 3, for example. Alternatively, for example, if the plate potential is as shown in FIG. 4, the bit data of "1" is written.

Here, for example, the conventional DRA shown in FIG. 1 is used.
In M, only one of the plurality of bit lines BL0 to BL3 and (BL0 bar) to (BL3 bar) is connected to one pair of the data lines DL and (DL bar).
Only the bit memory cells are accessed. Therefore, in such a conventional DRAM, in the screening of the electric field accelerating method, the writing of bit data for applying stress is also performed bit by bit.

On the other hand, in the present invention, the screening write circuit 17 can simultaneously write bit data for applying stress to the memory capacitors of a plurality of memory cells. Therefore, according to the present invention, since it is possible to apply stress to the insulating film of the memory capacitor for a plurality of memory cells at the same time, it is possible to sequentially write such bit data to all memory cells in an address order. When performing, the writing frequency can be increased.

Therefore, according to the present invention, it is possible to effectively screen a DRAM having a latent defect and improve the reliability of the DRAM. or,
Shortening the work time in such screening,
It is possible to reduce costs.

Further, as described above, even when a latent defect in the insulating film of the memory capacitor begins to become apparent and a minute leak current begins to flow in the insulating film, bit data for applying stress more frequently. Since the writing can be performed, stress can be effectively applied to the insulating film that is beginning to break down, and this latent defect can be revealed more quickly.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 7 is a block diagram showing the structure of a DRAM to which the present invention is applied.

In this embodiment, the present invention is applied to the above-mentioned conventional DRAM shown in FIG.

The illustrated stress application signal BTM is not shown in FIG. 7, but the mode selection circuit 1 shown in FIG.
Is generated by a circuit corresponding to 5. In the conventional DRAM of FIG. 1, the stress application signal BTM is input only to the plate voltage supply circuit 16A. On the other hand, in the present embodiment of FIG. 7, the column selector 12A also has
This stress application signal BTM is input. The present embodiment is also characterized in that the column selector 12A and the plate voltage supply circuit 16B shown in FIG. 7 are different from the column selector 12 or the plate voltage supply circuit 16A of the conventional example shown in FIG.

First, FIGS. 8 and 9 are circuit diagrams of the plate voltage supply circuit 16B used in this embodiment. In this embodiment, one of the plate voltage supply circuits 16B shown in FIGS. 8 and 9 is used.

In the plate voltage supply circuit 16B shown in FIGS. 8 and 9, first, in the normal operation mode in which the stress application signal BTM is "0", the plate potential Vp is (Vcc / 2) for both plate voltage supply circuits 16B. ).

On the other hand, the stress application mode in which the stress application signal BTM is "1" is as follows.
That is, in the stress application mode, the plate voltage supply circuit 16B of FIG. 8 supplies the plate potential of Vss. On the other hand, similarly, in the stress application mode in which the stress application signal BTM is "1", the plate voltage supply circuit 16B shown in FIG. 9 supplies the plate potential Vp of Vcc.

In FIG. 8, when the stress application signal BTM is "0" in the normal operation mode, the N-channel MOS transistor TN1 is turned off and the P-channel MOS transistor is turned off.
Both the transistor TP1 and the N-channel MOS transistor TN2 are turned on. Therefore, in this normal operation mode, (V
A plate potential Vp of cc / 2), that is, a normal plate potential is supplied.

On the other hand, in FIG. 8, when the stress application signal BTM of "1" is inputted in the stress application mode,
The N-channel MOS transistor TN1 is turned on, and both the P-channel MOS transistor TP1 and the N-channel MOS transistor TN2 are turned off. Therefore, the plate Vp becomes Vss, which is the screening plate potential.

In FIG. 9, first, when the stress application signal BTM becomes "0" in the normal operation mode, the P channel M
The OS transistor TP2 is turned off, and the P-channel MOS transistor TP3 and the N-channel MOS transistor TN1 are both turned on. Therefore, the plate potential Vp of (Vcc / 2) divided by the two resistors R1 is supplied, and the normal plate potential is supplied.

On the other hand, in FIG. 9, when the stress application signal BTM becomes "1" in the stress application mode, the P-channel MOS transistor TP2 is turned on and P
Channel MOS transistor TP3 and N-channel MO
Both the S transistors TN1 are turned off. Therefore,
In this stress application mode, the plate potential Vcc of Vcc
p is supplied and the screening plate potential is supplied.

FIG. 10 is a circuit diagram centering on the column selector 12A used in this embodiment.

The circuit of the column selector 12A of FIG. 7 is shown in the alternate long and short dash line of FIG. That is, the column selector 12A has N-channel MOS transistors T0A to T3.
A, T0B to T3B, and OR logic gates G0 to G3. The column selector 12A is shown in FIG.
0 has a built-in address decoder, and the column address CA input from the outside as shown in FIG. 7 is decoded by the address decoder to generate an address signal Y.
0 to Y3 are internally generated.

In FIG. 10, when the stress application signal BTM is "0" in the normal operation mode, the OR logic gate G is generated according to the decoded address signals Y0 to Y3.
Any one of 0 to G3 outputs "1", one of the N-channel MOS transistors T0A to T3A is turned on, and any one of the bit lines BL0 to BL3 is connected to the data line DL. . At the same time, in accordance with any one of the OR logic gates G0 to G3 which outputs "1",
Any one of the N-channel MOS transistors T0B to T3B is turned on, and the bit lines (BL0 bar) to (BL
Any one of 3 bars) is connected to the data line (DL bar).

On the other hand, when the stress application signal BTM becomes "1" in the stress application mode, the OR logic gates G0 to G are generated regardless of the decoded address signals Y0 to Y3.
3 becomes "1", all N-channel MOS transistors T0A to T3A and T0B to T3B are turned on, and all bit lines BL0 to BL3 are data lines D.
All of the bit lines (B0L bar) to (BL3 bar) are connected to the data line (DL bar). Therefore, in the stress application mode, all the memory cells MC connected to any one of the word lines WL0 to WL3 driven by the row decoder, that is, the four memory cells MC are
At the same time, write access is possible on the data lines DL, (DL bar).

Here, in this embodiment, as described above, the N-channel MOS transistors T0A to T3A and T0B to T are centered around the OR logic gates G0 to G3.
Together with 3B, the one corresponding to the screening write circuit 17 of FIG. 6 is configured.

As described above, in the present embodiment, in the normal operation mode, the word lines WL0 to WL3 and the bit lines BL0 to BL3, (BL0 bar) to (BL3 bar) are selected, and the data is selected according to the selection. Line DL,
Only one memory cell MC connected to (DL bar) is accessed. On the other hand, in the stress application mode, the four memory cells selected by the word lines WL0 to WL3 are supplied while supplying the plate potential Vp to which a higher voltage is applied to the insulating film of the memory capacitor of the memory cell MC. Write access to the MC is possible at the same time. In this way, since the same bit data can be written in the four memory cells MC at the same time,
In this embodiment, each memory cell M is, for example, four times more frequently than the conventional DRAM shown in FIG. 1 within the same time.
Bit data can be written to C by applying a voltage to the insulating film of the memory capacitor to apply stress.

Therefore, according to the present embodiment, the insulating film and the oxide film for forming the memory capacitor, the gate oxide film of the access transistor, and the like are exposed in order to reveal potential defects. When a device is screened by applying a voltage and applying stress, the voltage is efficiently applied, so that it is possible to obtain an excellent effect that an initial defect can be efficiently screened.

[0056]

As described above, according to the present invention, these insulating films and oxide films for exposing potential defects relating to the insulating film forming the memory capacitor, the gate oxide film of the access transistor, and the like. DR that can efficiently perform initial defect screening by efficiently applying the voltage when screening a device that is actually stressed by applying a voltage to a device such as DR
An excellent effect that AM can be provided can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional DRAM.

FIG. 2 is a circuit diagram showing an operation when a plate potential of (Vcc / 2) is applied in a normal operation mode in a DRAM memory cell.

FIG. 3 is a circuit diagram showing an operation when a plate potential of Vcc is applied in a stress application mode in a memory cell of DRAM.

FIG. 4 is a circuit diagram showing an operation when a plate potential of Vss is applied in a stress application mode in a DRAM memory cell.

FIG. 5 is a sectional view of an integrated circuit of a memory cell used in a DRAM.

FIG. 6 is a block diagram showing a basic configuration of a main part of a DRAM of the present invention.

FIG. 7 is a block diagram showing a configuration of an embodiment of a DRAM to which the present invention is applied.

FIG. 8 is a circuit diagram of a first example of a plate voltage supply circuit used in the embodiment.

FIG. 9 is a circuit diagram of a second example of the plate voltage supply circuit used in the embodiment.

FIG. 10 is a circuit diagram centering on a row selector used in the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 3 ... Memory cell matrix part 12, 12A ... Column selector 14 ... Sense amplifier timing circuit 15 ... Mode selection circuit 16, 16A, 16B ... Plate voltage supply circuit 17 ... Screening write circuit 18 ... Input / output circuit 22 ... Input Buffer 24 ... Read circuit MC ... Memory cell SA ... Sense amplifier TG ... Access transistor CM ... Memory capacitor T0A-T3A, T0B-T3B ... N-channel MOS transistors G0-G3 ... OR logic gates WL0-WL3 ... Word lines BL0-BL3, (BL0 bar) to (BL3 bar) ... Bit line DL, (DL bar) ... Data line Vp ... Plate potential SE ... Sense signal BTM ... Stress application signal DI ... Input data DO ... Output data CA ... Column address Y0-Y3 ... Address signal

Claims (2)

[Claims] 1. A memory cell using memory capacitors arranged in a matrix for storing bit data by accumulated charges, a word line driven by a row decoder,
And select by the bit line selected by the column selector,
In a dynamic random access memory configured to perform write access and read access through the bit line, a mode selection circuit for setting either a normal operation mode or a stress application mode for screening a potential defect. And a plate potential supply circuit for applying a normal plate potential in the normal operation mode, while applying a screening plate potential that causes a larger potential difference in the memory capacitor than in applying the normal plate potential in the stress application mode. And a screening write circuit for simultaneously writing bit data with accumulated charges to the memory capacitor, the number of which is larger than the number of bits selected during write access in the normal operation mode. Click random access memory. 2. The screening write circuit according to claim 1, wherein all the bit lines provided in the dynamic random access memory are used at least at the same time for use in write access, so that more memory capacitors are provided. At the same time, the dynamic random access memory is characterized in that bit data with accumulated charge is written at the same time.