JPH0748318B2 - Semiconductor memory circuit and test method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit and a method of testing the same, and particularly to an insulated gate field effect transistor (hereinafter
Testing a memory cell by improving the voltage generation circuit that supplies to the power supply side electrode of the memory cell capacity of a dynamic RAM (hereinafter abbreviated as DRAM) using a plurality of memory cells consisting of a MOS transistor) and a capacitor The present invention relates to such a semiconductor memory circuit and a test method thereof.

[Prior Art] Due to the progress of manufacturing technology of semiconductor integrated circuits and the demand for price reduction by users, the integration density of DRAM has increased at a rate of about four times in almost three years, and the DRAM having a capacity of 4 Mbits is now available. Is being put to practical use. In this DRAM, for example, "0" data is written to all memory cells, "0" data is read from all memory cells, and the same applies to "1" data with a cycle time of 10 μsec [RAS (row address Strobe) maximum pulse width of signal], the test time T1 is expressed by the following equation (1).

T1 = 4 ("0" write → "0" read → "1" write → "1" read) x 4 x 10 ⁶ (memory capacity) x 10 μsec (cycle time) = 160 seconds (1) Normal In the case of dynamic RAM, it is necessary to perform at least the above-mentioned tests under the four conditions of the maximum value of the operating power supply voltage range of 5.5V, the minimum value of 4.5V, and the operating temperature range of high temperature 70 ℃ side and low temperature 0 ℃ side. is there.

In this case, the test time T2 is expressed by the equation (2).

T2 = 160 seconds × 4 = 640 seconds (2) The above value is a very long test time of the integrated circuit, which causes a decrease in productivity and an increase in price.

In addition, in some cases, it may not be possible to detect only with the above items. For example, it is necessary to perform a combination test of the timing conditions of the input signal, the address designation order of the address signal, the pattern of the data written in the memory cell, and the like. is there.
In such a case, the test time becomes extremely long.

As a countermeasure against this, pay attention to the fact that most of the memory cells with a small operation margin cause the malfunction in these combination tests, and the power supply voltage fluctuation test that can test the operation margin of these memory cells in a short time. (Hereinafter, abbreviated as V bump test) has been used,
As the storage capacity has increased, the effect of the V bump test has become unobtainable, as described below. The reason for this will be described below with reference to FIGS. 11 to 15.

FIG. 11 shows a DR which has been conventionally used and to which the present invention is applied.
FIG. 3 is a block diagram showing a schematic configuration of an entire AM reading unit.

In FIG. 11, the DRAM is composed of a memory cell array MA, an address buffer AB, an X decoder ADX, a Y decoder ADY, a sense amplifier, I / OSI and an output buffer OB. The memory cell array MA has a plurality of memory cells for storing information arranged in rows and columns,
The address buffer AB receives an external address signal given from the outside and generates an internal address signal.
The X decoder ADX decodes the internal address signal supplied from the address buffer AB and selects the corresponding row of the memory cell array. The Y decoder ADY decodes the internal column address signal supplied from the address buffer AB and selects the corresponding column of the memory cell array MA.

The sense amplifier and I / OSI detect and amplify the information stored in the selected memory cell of the memory cell array MA, and output the information as read data to the output buffer OB according to the signal from the Y decoder ADY. To do. The output buffer OB receives the read data and outputs the output data OUT to the outside. Further, a control signal generation system CG that generates a control signal for controlling the timing of various operations of the DRAM is provided as a peripheral circuit.

FIG. 12 is a diagram showing a schematic configuration of the memory cell array portion shown in FIG.

In FIG. 12, the memory cell array MA includes a plurality of word lines WL1, WL2, ..., WLn and a plurality of bit lines BL0, BL0, BL1, BL.
Including 1, ..., BLm, BLm. One row of memory cells is connected to each of the word lines WL1, ..., WLn. The bit lines form a folded bit line, and the two bit lines form a pair of bit lines. That is, the bit lines BL0, ▲ ▼ form one pair of bit line pairs, BL1, ▲ ▼ form one pair of bit line pairs, and so on. Similarly, the bit lines BLm, BLm form a bit line pair. is doing.

A memory cell 1 is connected to an intersection of each bit line BL0, ▲ ▼, ..., BLn, ▲ ▼ and every other word line. That is, in each bit line pair, the memory cell is connected to the intersection of one word line and any one of the pair of bit lines. Each bit line pair has a precharge / equalize circuit 15 for balancing the potential of each bit line pair and precharging to a predetermined potential V _B.
0 is provided. In addition, each bit line pair has a signal line 2
_A sense amplifier 50 is provided which is activated in response to signals φ _A and φ _B transmitted on 0 and 30, senses a potential difference between the bit line pair and differentially amplifies. Each bit line pair is selectively connected to the data input / output bus I / O, ▲ ▼ according to the address decode signal from the Y decoder ADY. That is, the bit line BL0, ▲ ▼ is connected to the data input / output bus I / O, ▲ ▼ via the transfer gates T0, T0 ', respectively.
Connected to.

Similarly, the bit lines BL1, ▲ ▼ are connected to the data input / output bus I / O, ▲ via the transfer gates T1, T1 ′, respectively.
The bit lines BLm, BLm connected to ▼ are connected to the data input / output bus I / O, I / O, via transfer gates Tm, Tm ′, respectively.
Connected to ▲ ▼. Each transfer gate T0, T
The address decode signal from the Y decoder ADY is transmitted to the gates of 0 ', ..., Tm, Tm'. As a result, a pair of bit lines is connected to the data input / output bus I / O, ▲ ▼.

FIG. 13 is a diagram showing a detailed structure of a pair of bit lines of the bit line pair shown in FIG. Note that, in FIG. 13, only one word line and one pair of bit lines are shown for simplification of the drawing.

In FIG. 13, a pair of bit lines 2 and 7 are precharged to a predetermined potential V _B during standby of the memory, and
A precharge / equalize circuit 150 is provided to equalize the potential of 7 to a predetermined potential. This precharge / equalize circuit 150 has a precharge signal φ
An n-channel MOS transistor for transmitting a predetermined precharge potential to the bit lines 2 and 7 according to _P to electrically connect the bit lines 2 and 7 and thereby equalize the potentials of the bit lines 2 and 7. Includes transistors 10 and 11. These n
The channel MOS transistors 10 and 11 are both turned on in response to the precharge signal φ _P given via the signal line 12,
The precharge potential V _B transmitted on the signal line 9 is applied to the bit lines 2 and 7.

The memory cell 1 is composed of a transfer gate 5 composed of an n-channel insulated gate field effect transistor and a capacitor 6. The gate of the transfer gate 5 is connected to the word line 3 and the source thereof is connected to the bit line 2. The capacitor 6 is connected to the drain of the transfer gate 5 via the node 4, and the data of the memory cell 1 is stored in this node 4. That is, the node 4 constitutes a so-called storage node.

When the word line 3 is selected, the word line drive signal Rn is transmitted to the transfer gate 5, whereby the transfer gate 5 becomes conductive, and the information stored in the memory cell 1 is transmitted onto the bit line 2. . Although a memory cell (not shown) is connected to the bit line 7, the word line 3
No memory cell is connected to the intersection of the bit line 7 and the bit line 7. Therefore, when the memory cell 1 shown in FIG. 4 is selected, the bit line 7 provides the reference potential for the bit line 2. The bit lines 2 and 7 include parasitic capacitances 13 and 14, respectively.

Further, resistors 17 and 18 which form a constant voltage generating circuit are connected in series between the power source 16 and the ground, and these resistors 17 and 18 are connected in series.
A constant voltage determined by resistance division is generated at the connection point with. The resistance values of the resistors 17 and 18 are selected so that this voltage is half the level of the normal power supply voltage. The output voltage of the constant voltage generating circuit is given to the other electrode of the capacitor 6 via the signal line 8. The capacitor 6 is a capacitor composed of a thin insulating film, for example, a balanced plate electrode having a single layer of silicon oxide or a laminated film of silicon oxide and silicon nitride as a dielectric, and its size depends on the area of the memory cell. is doing.

On the other hand, due to the increase in the degree of integration (storage capacity), the area of the memory cell becomes smaller, and the memory cell capacity tends to decrease accordingly. However, the malfunction of the DRAM due to α-rays emitted from the DRAM exterior package (soft error)
To prevent this, a memory cell capacitance value of about 50 fF is generally required. For this reason, it is common practice to compensate for the decrease in memory cell capacitance due to the decrease in memory cell area by reducing the thickness of the dielectric film. However, when the film thickness of the dielectric is reduced, the electric field applied to the insulating film forming the dielectric is increased, the insulating film is easily broken, and the reliability of the DRAM is deteriorated. In particular, this problem begins to become more noticeable with the 1 Mbit DRAM currently in practical use, and as a countermeasure against this, the electrode on the power supply side of the memory cell capacitor (hereinafter referred to as the cell plate electrode) is shown in FIG. like,
It is common to supply a voltage that is half the power supply voltage divided by resistors 17 and 18. In this regard, Japanese Patent Publication No. 60-50065 (US Application No. 7
22841). According to this method, the electric field is determined by the voltage difference between the storage node 4 and the cell plate electrode, and the cell plate voltage becomes an intermediate value between the data of "1" and "0", so that the electric field is 1/2. become.

[Problems to be Solved by the Invention] However, by applying a voltage half the power supply voltage to the cell plate electrode as described above, it becomes difficult to detect a memory cell with a small operation margin by the V bump test. It's coming. The reason will be described below.

In DRAMs up to 1 Mbit, the insulating film that constitutes the dielectric of the memory cell capacity was relatively thick (256 kbit DRAM
About 150Å to 200Å), the voltage of the cell plate electrode is 1/2 Vcc
The need to set to was small. Therefore, since the power line or the ground line having a low impedance can be connected to the cell plate, the noise of the cell plate can be reduced. On the other hand, the constant voltage generating circuit shown in FIG. 13 has a relatively high impedance, is likely to generate noise during the operation of the DRAM, and causes a decrease in the operation margin, and thus has not been used until now.

Next, the effect of the V bump test when the level of the cell plate electrode is the power supply voltage Vcc, ground (fixed level) and Vcc / 2 will be compared.

When the level of the cell plate electrode is the power supply voltage Vcc level FIGS. 14 and 15 are voltage waveform diagrams of each node related to the V bump test. In the V bump test, data is written in the memory cell 1 for a certain period with a certain power source voltage Vcc, and the first
As shown in FIG. 4 (a), this is performed by raising the power supply voltage Vcc by a certain level and then reading data from the memory cell 1 for a certain period. In FIG. 14, data is written at the power supply voltage Vcc, and data is read at Vcc + ΔV. Since the precharge voltage V _B is set to a half of the power supply voltage Vcc, it becomes as shown in FIG. 14 (b). Since the storage node 4 is supposed to be written with "0" data, it is 0 V at the time of writing, but as shown in FIG. 14 (c), the fluctuation of the power supply voltage is caused via the capacitor 6. By combining
It is assumed that the fluctuation will rise by almost the same amount. At this time, the bit lines 2 and 7 vary with the precharge potential V _B, is substantially the same level as the precharge potential V _B.

Next, the operation of reading data from the memory cell 1 will be described with reference to FIG. As shown in Fig. 15 (a), the time
When the precharge signal φ _P becomes low level at t ₀ ,
The signal line 9 and the bit lines 2 and 7 are separated. Then, as shown in FIG. 15B, at time t ₁ , when the word line drive signal Rn rises, the MOS transistor 5 becomes conductive, and a current flows from the bit line side having a high potential to the storage node 4 side, The potential of the bit line 2 drops as shown in FIG.
As shown in FIG. 15D, the potential on the storage node 4 side rises. At time t ₂ , there is almost no change in the potential, and the read levels of the bit lines 2 and 7 are set. Bit line at this time
The 2,7 level is calculated by the following formula.

Considering that the law of conservation of charge is established between the bit line 2 and the storage node 4 before and after the conduction of the MOS transistor 5, 1/2 · (Vcc + ΔV) · C ₁₃ + ΔV · C ₆ = (C ₁₃ + C ₆ ) ・ V _BO・ ・ ・ (3) V _BO = 1 / (C ₁₃ + C ₆ ) ・ [1/2 ・ (Vcc + ΔV) ・ C ₁₃ + ΔV ・ C ₆ ] ・ ・ ・ (4) Voltage difference V _{SO from the} bit line 7 side Is V _SO = 1 / (C ₁₃ + C ₆ ) ・ [1/2 ・ Vcc + ΔV) ・ C ₁₃ + ΔV ・ C ₆ ] −1/2 ・ (Vcc + ΔV) (5) = −1 / 2 ・ C ₆ / ( C ₁₃ + C ₆ ) · (Vcc−ΔV) (6) On the other hand, when there is no V bump, the voltage difference between the bit line 2 and the bit line 7 when the “0” data is read from the memory cell 1 is expressed by the following formula. Calculated by

Considering that the law of conservation of charge is established between the bit line 2 and the storage node 4 before and after the conduction of the MOS transistor 5 as in the case of the equation (3), 1/2 · Vcc · C ₁₃ = ( C ₁₃ + C ₆ ) ・ V _BO … (6-1) V _BO = 1/2 ・ C ₁₃ / (C ₁₃ + C ₆ ) ・ Vcc… (6-2) The voltage difference V _SO from the bit line 7 side is _{V SO = 1/2 · C} 13 / (C 13 + C 6) · Vcc -1/2 · Vcc ... (6-3) = -1 / 2 · C 6 / (C 13 + C 6) · Vcc ... (6 -4) Comparing the expressions (6) and (6-4) by absolute values,
The formula (6) has a smaller voltage difference by 1/2 · C ₆ / (C ₁₃ + C ₆ ) · ΔV, which is effective for V bumping.

1/2 when "1" data is written in the memory cell
_{(Vcc + ΔV) · C 13} + (Vcc + ΔV) · C 6 = (C 13 + C 6)
・ V _B1 (7) V _B1 = 1/2 ・ (Vcc + ΔV) +1/2 ・ (Vcc + ΔV) ・ C ₆ / (C ₁₃ + C ₆ ) ・ ・ ・ (8) The voltage difference V _S1 from the bit line 7 side is V _S1 = 1/2 ・ (Vcc + ΔV) +1/2 ・ (Vcc + ΔV) ・ C ₆ / (C ₁₃ + C ₆ ) −1/2 (Vcc + ΔV) ... (9) = 1/2 (Vcc + ΔV) ・ C ₆ / ( C ₁₃ + C ₆ ) (10) On the other hand, when there is no V bump, the voltage difference between the bit line 2 and the bit line 7 when the “1” data is read from the memory cell 1 is calculated by the following formula.

Considering that the law of conservation of charge is established between the bit line 2 and the storage node before and after the conduction of the MOS transistor 5 as in the equation (3), 1/2 · Vcc · C ₁₃ + Vcc · C ₆ = (C ₁₃ + C ₆ ) ・ V _B1 … (10-1) V _B1 = 1/2 ・ Vcc ＋ 1/2 ・ Vcc ・ C ₆ / (C ₁₃ + C ₆ )… (10-2) Voltage with bit line 7 side the difference V _{S1 is, V S1 = 1/2 ·} Vcc + 1/2 · Vcc · C 6 / (C 13 + C 6) -1/2 · Vcc ... (10-3) = 1/2 · Vcc · C 6 / ( When _{C 13 + C 6) ... (} 10-4) comparing the equation (10) and a second (10-4) below, for data "1", the (10) it is large voltage difference equation The V bump has the opposite effect.

In case of fixed level (when cell plate voltage is fixed against Vcc fluctuation) When "0" data is written in memory cell 1, 1/2 · (Vcc + ΔV) · C ₁₃ = (C ₁₃ + C ₆ ) ・ V _BO … (11) V _BO = 1 / (C ₁₃ + C ₆ ) [1/2 (Vcc + ΔV) ・ C ₁₃ ]… (12) V _SO = 1 / (C ₁₃ + C ₆ ) [1 / 2 ・ (Vcc + ΔV) ・ C ₁₃ ] −1/2 ・ (Vcc + ΔV)… (13) V _SO = −1 / 2 ・ C ₆ / (C ₁₃ + C ₆ ) ・ (Vcc + ΔV)… (14) Number (14) ) And the equation (6-4) are compared in absolute value,
The formula (14) works to increase the voltage difference by 1/2 · C ₆ / (C ₁₃ + C ₆ ) · ΔV, and the V bump has the opposite effect. When "1" data is written in memory cell 1, 1/2 · (Vcc + ΔV) · C ₁₃ + (Vcc + ΔV) C ₆ = (C ₁₃ + C ₆ ) V _B1 … (16) V _B1 = 1 _{/ (C 13 + C 6)} · [1/2 · (Vcc + ΔV) · C 13 + (Vcc + ΔV) · C 6] ... (17) V S1 = 1/2 · C 6 / (C 13 + C 6) · (Vcc + ΔV ) (18) Comparing the equation (18) with the equation (10-4), it works in the direction of reducing the voltage difference with respect to the data "1", and there is the effect of V bump.

In case of 1/2 Vcc level In this case, the voltage level of the cell plate electrode is 1 / 2.ΔV
Since only the change occurs, the level change of the storage node 4 of the memory cell 1 also becomes 1 / 2ΔV. Then, when calculated in the same way as described above, 1/2 · (Vcc + ΔV) · C ₁₃ + 1/2 · ΔV · C ₆ = (C ₁₃ + C ₆ ) · V _BO (19) V _BO = 1 / ( _{C 13 + C 6) [1/2} · (Vcc + ΔV) · C 13 +1/2 · ΔV · C 6] ... (20) V SO = 1 / (C 13 + C 6) [1/2 · (Vcc + ΔV) · C ₁₃ + 1/2 · ΔV · C ₆ ] -1/2 (Vcc + ΔV) (21) = -1/2 · C ₆ / (C ₁₃ + C ₆ ) · Vcc (22) Formula (22) and formula (22) Comparing with the expression 6-4), they are the same and there is no effect of the V bump.

When “1” data is written in the memory cell, 1/2 · (Vcc + ΔV) · C ₁₃ + (Vcc + 1/2 · ΔV) · C ₆ = (C ₁₃ + C ₆ ) · V _B1 … ( 23) V _B1 = 1 / (C ₁₃ + C ₆ ) [1/2 ・ (Vcc + ΔV) ・ C ₁₃ + (Vcc + 1/2 ・ ΔV) ・ C ₆ … (24) V _S1 = 1 / (C ₁₃ + C ₆ ) [1/2 ・ (Vcc + ΔV) ・ C ₁₃ + (Vcc + 1/2 ・ ΔV) ・ C ₆ … (25) = 1/2 ・ C ₆ / (C ₁₃ + C ₆ ) ・ Vcc… (26) Number (26) Comparing the equation and the equation (10-4), they are the same and there is no effect of the V bump.

The above results are summarized in Fig. 16.

From the above results, it can be seen that there is a difference between the case where the cell plate voltage is Vcc or fixed and the case where the cell plate voltage is 1/2 Vcc. That is, when the cell plate voltage is set to Vcc or fixed, the voltage difference between the pair of bit lines, that is, the input voltage difference of the sense amplifier changes depending on ΔV, so that the read margin of the memory cell can be tested based on ΔV. it can. However, in the case of 1 / 2.Vcc, since the input voltage difference of the sense amplifier cannot be changed by ΔV, the read margin of the memory cell cannot be tested by ΔV.

Therefore, the main object of the present invention is to keep the cell plate voltage at 1 / 2.Vcc during normal operation of the DRAM and set the cell plate voltage at the Vcc level or fixed level only during the V bump test. It is an object of the present invention to provide a semiconductor memory circuit and a method for testing the same, which can test a memory cell having a small operation margin in a short time and which can reduce the breakdown of the insulating film of the memory cell capacity.

[Means for Solving the Problems] The present invention relates to an insulated gate field effect transistor in which one main electrode is connected to a corresponding bit line and a gate electrode is connected to a corresponding word line, and one electrode is In a semiconductor memory circuit including a memory cell having a capacitance connected to the other main electrode of the insulated gate field effect transistor, the output node connected to the other electrode of the capacitance of the memory cell is supplied to the output node during normal operation. Intermediate potential generating means for applying an intermediate potential between the power supply potential and the ground potential, a first transistor connected between the power supply potential node to which the power supply potential is applied and the output node, and the ground to which the ground potential is applied. It has a second transistor connected between the potential node and the output node, and the first and second transistors are non-conductive during normal operation. The intermediate potential is output from the intermediate potential generating means to the output node, and the first transistor is rendered conductive and the second transistor is rendered non-conductive during the first test period of the test mode. A potential higher than the intermediate potential from the intermediate potential generation means is output to the output node, and the first transistor is rendered non-conductive and the second transistor is rendered conductive during the second test period of the test mode to generate the intermediate potential. It comprises a cell plate voltage generating circuit for outputting a potential lower than the intermediate potential from the generating means to an output node.

[Operation] In the semiconductor memory circuit and the test method thereof according to the present invention, during normal operation, an intermediate potential between the power supply potential and the ground potential is applied to the other electrode of the capacitor in the memory cell to write data in the test mode. A power supply potential is sometimes applied to the other electrode of the capacitor, and a potential higher than the power supply potential is applied to the other electrode of the capacitor during data reading in the test mode, so that a test of a memory cell having a small margin is performed in a short time.

[Embodiment of the Invention] FIG. 1 is an electric circuit diagram of an embodiment of the present invention.

First, the configuration of an embodiment of the present invention will be described with reference to FIG. This embodiment includes two circuits 100 and 200, and the circuit 100 is provided to check the operation margin of the data "1" of the memory cell 1. This circuit
An arbitrary external input signal (for example, CAS signal) of DRAM is applied to the input terminal 101 of 100. The input signal may be given to any input / output terminal. Voltage detection circuit
A plurality of N-channel MOS transistors N1, N2 ... Nn are connected in series at 120, and the drain and gate electrode of each transistor are connected. The source of the N-channel MOS transistor Nn at the final stage is grounded by the resistor 103 having a relatively high resistance value. N channel M
Node 102, which is the connection point between the OS transistor and resistance element 103
Includes the source of the P-channel MOS transistor 104, the gate electrode of the P-channel MOS transistor 107 and the N-channel MOS transistor.
The gate electrode of the transistor 105 is connected. The P-channel MOS transistor 107 and the N-channel MOS transistor 105 are connected in series between the power supply terminal 16 and the ground to form an inverter circuit. The P-channel MOS described above
The drain of the transistor 104 is connected to the power supply terminal 16,
The gate electrode is connected to the node 106 which is the output point of the inverter circuit constituted by the P channel MOS transistor 107 and the N channel MOS transistor 105.

Further, the P-channel MOS transistor 11 is connected to the node 106.
The gate electrode of 0 and the gate electrode of the N-channel MOS transistor 108 are connected. P-channel MOS transistor 110
The N-channel MOS transistor 108 is connected in series between the power supply terminal 16 and the ground to form an inverter circuit. The gate electrode of the N-channel MOS transistor 111 is connected to the node 109 which is the output point of this inverter circuit. The drain of the N-channel MOS transistor 111 is connected to the cell plate voltage supply line 8 and the source is grounded. The cell plate voltage supply line 8 is connected to a connection point between resistors 17 and 18 which form a constant voltage circuit connected between the power supply terminal 16 and the ground.

On the other hand, the circuit 200 is provided to test the operation margin of the data “0” of the memory cell. The voltage detection circuit 220 included in the circuit 200 is configured in the same manner as the voltage detection circuit 120 described above, and has a plurality of N-channel MOS transistors N ₁ ′,
N ₂ ′ ... Nn ′, resistance element 203 and P-channel MOS transistor
Includes 204 and 207 and N-channel MOS transistor 205. The P channel MOS transistor 207 and the N channel MOS
The transistor 205 is connected between the power supply terminal 16 and the ground,
An inverter circuit is configured by these. The node 206 which is the output terminal of this inverter circuit is a P channel M
It is connected to the gate electrode of the OS transistor 211, the drain of this P-channel MOS transistor 211 is connected to the power supply terminal 16, and the source is connected to the voltage supply line 8.

Next, the operation of the electric circuit shown in FIG. 1 will be described. Now, the threshold voltage (V _TH ) of the MOS transistor is 0.5V
Assuming that n = 13, these N-channel MOS transistors N ₁ , N ₂ ... Nn do not conduct unless a voltage of 0.5V × 13 = 6.5V or more is applied between the input terminal 101 and the node 102. . At this time, the input terminal of the other voltage detection circuit 220 is externally supplied with an input signal within the normal operating range, and the N-channel MOS transistors N _{1 ′} , N _{2 ′} ... N.
_n'is non-conductive. The maximum value of the "H" level side of the input signal of the DRAM is specified to be 6.5V, and in normal operation, the node 102 is grounded by the resistance element 103 and is at the "L" level. As a result, the P-channel MOS transistor 107 becomes conductive, and the node 106 becomes "H".
Then, the N-channel MOS transistor 108 becomes conductive, and the node 109 becomes "L" level. For this reason, the N-channel MOS transistor 111 becomes non-conductive and the memory cell plate voltage is 1 / 2.Vcc, so that a strong electric field is not applied to the insulating film of the memory cell capacitor.

Next, when the voltage of the input terminal 101 is set to 6.5V or more, for example, 10V, a voltage of approximately 10V−6.5V = 3.5V is generated at the node 102. For this purpose, the N-channel MOS transistor 1
05 becomes conductive, and the level of the node 106 becomes "L" level.
As a result, the P-channel MOS transistor 104 becomes conductive,
Node 102 is pulled up to the level of power supply voltage Vcc, P-channel MOS transistor 107 is rendered non-conductive, and N-channel MOS transistor 105 is rendered conductive. As a result, node 106 attains a complete "L" level, P-channel MOS transistor 110 becomes conductive, N-channel MOS transistor 108 becomes non-conductive, and node 109 attains the level of power supply voltage Vcc. Further, the N-channel MOS transistor 111 becomes conductive,
Resistor 17 is set to a relatively high value in order to reduce power consumption, and the conduction resistance of N-channel MOS transistor 111 is set low, so that the cell plate voltage becomes approximately the ground level.

That is, by the V bump test, "1" of the memory cell 1
It is possible to test the operation margin with respect to the above data. V
If terminals for bump test are provided, the above is not necessary, but high-density mounting is required.
In DRAM, it is necessary to reduce the number of terminals as much as possible, and normally no test terminals are provided. Therefore, according to the embodiment of the present invention, the V bump test can be performed without providing a test terminal.

It is applied in pulse form and its voltage is 0V which is the normal operating condition.
The test can be easily performed by changing the voltage between (“0”) and 6.5V (“1”). In this case, if the level of the CAS input signal is once set to 10V before the V bump test, the level of the node 102 is kept at the level of the power supply voltage Vcc by the P-channel MOS transistor 104. After setting ▲ ▼ input signal to 10V, ▲ ▼ input signal can be changed from 0V to 6.5V.
Bump test can be done easily.

Conversely, in order to get out of this V bump test state,
The power supply voltage should be once reduced to 0V. As a result, the level of the node 102 becomes the ground level, and as a result, the MOS transistor 111 becomes non-conductive, and the level of the terminal 8 becomes 1/2 · Vc.
c, and normal operation can be performed. The terminal 201 is a terminal to which the control signal W is input because external data is written in the memory cell.

When a W input signal is externally applied to the input terminal 201 of the voltage detection circuit 220 at a voltage higher than the normal operation range, and an input signal less than the normal operation range is externally applied to the input terminal 101 of one of the voltage detection circuits 120, N-channel MOS transistor N ₁ ′,
N ₂ ′ ... Nn ′ are turned on, and the node 202 becomes “H” level. This “H” level signal is the P channel MOS transistor 2
Inverted by 07 and N-channel MOS transistor 205,
The node 206 becomes the “L” level. Therefore, the P-channel MOS transistor 211 becomes conductive and the cell plate voltage is set to the power supply voltage Vcc. In this case, the V bump test enables the operation margin test for the data "0" of the memory cell 1. That is, the V bump test can be performed on the data "0" and data "1" of the memory cell by using the terminals 101 and 201, respectively. In this embodiment, the cell plate voltage becomes the power supply voltage Vcc, but this value is not limited to Vcc and changes with the power supply voltage Vcc, and the second term (1 / According to 2 · ΔV · C ₆ ), the effect of the V bump test can be obtained if the voltage value is such that the amount of change is larger than 1/2 · Vcc.

FIG. 2 is a schematic block diagram showing another embodiment of the present invention. The embodiment shown in FIG. 2 generates a cell plate voltage in response to an input timing condition. For this purpose, a timing detection circuit 31 is provided, and the timing detection circuit 31 has a signal ▲ ▼ and a signal ▲
▼ A signal and a signal are given. Timing detection circuit 31
▲ ▼ When the signal rises to the “L” level, ▲
If the signal and the W signal are "L" level, the test signal T is given to the switching signal generating circuit 32. Switching signal generation circuit 32
Can be given an arbitrary signal, but in this case, the address signal A ₀ is given. Switching signal generating circuit 32 switches the cell plate voltage output from cell plate voltage generating circuit 33 in response to test signal T and address signal A ₀ .

3 is a circuit diagram of the timing detection circuit shown in FIG. 2, FIG. 4 is a circuit diagram showing the switching signal generation circuit shown in FIG. 2, and FIG. 5 shows a cell plate voltage generation circuit. It is a circuit diagram shown.

Next, a more specific configuration of another embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 3, the signal () is applied to inverter 311 and inverted, and its output is applied to one input terminal of 3-input AND gate 313 and to the drain of n-channel MOS transistor 316. Signal is inverter 312
Is applied to the AND gate 313 and is also applied to the drain of the n-channel MOS transistor 317.

The signal ▲ ▼ is given to the inverter 314, inverted, and given to the one-shot pulse generation circuit 315. The one-shot pulse generation circuit 315 generates a one-shot pulse at the timing of the falling edge of the signal and gives it to the AND gate 313. The output of the AND gate 313 is given to the respective gates of the n-channel MOS transistors 316 and 317. The source of n-channel MOS transistor 316 is connected to the input of the latch circuit formed of inverters 318 and 319, and the source of n-channel MOS transistor 317 is connected to the input of the latch circuit formed of inverters 320 and 321.
The output of each latch circuit is input to the AND gate 322, and the test signal T is output from the output of the AND gate 322.

Next, the configuration of the switching signal generating circuit 32 will be described with reference to FIG. The test signal T is given to one input end of the one-shot pulse generation circuit 324 and the AND gate 330, inverted by the inverter 327 and given to one input end of the OR gate 329. One-shot pulse generation circuit 324
Generates a one-shot pulse in response to the test signal T and supplies it to the gate of the n-channel MOS transistor 323.
The address signal A ₀ is applied to the drain of the n-channel MOS transistor 323. The source of the n-channel MOS transistor 323 is connected to the input terminal of the latch circuit including the inverters 325 and 326, the output of the latch circuit is inverted by the inverter 328, and the other input terminal of the OR gate 329 and the AND gate.
It is given to the other input terminal of 330. The OR gate 329 outputs the V _A signal from its output and the AND gate 330 outputs from its output.
Output V _B signal.

Next, referring to FIG. 5, a cell plate voltage generating circuit 33
Will be described. The cell plate voltage generating circuit 33 includes a p-channel MOS transistor 211, an n-channel MOS transistor 111, and resistors 17 and 18. The p-channel MOS transistor 211 and the n-channel MOS transistor 111 are connected in series between the power supply and the ground, the V _A signal output from the switching signal generation circuit 32 is given to the gate of the p-channel MOS transistor 211, and the V _B signal is n. It is applied to the gate of the channel MOS transistor 111. Furthermore, a p-channel MOS transistor 211 and an n-channel connected in series are connected between the power supply and ground.
Resistors 17 and 18 are connected in parallel to the MOS transistor 111 in series. The cell plate voltage is output from the connection point between the resistors 17 and 18.

FIG. 6 is a timing chart for explaining the operation of the timing detection circuit shown in FIG.

Next, the operation of another embodiment of the present invention will be described with reference to FIGS. When the power is turned on, the inverters 318 and 319 and 320 and 321 of the timing detection circuit 35
Each output of the latch circuit composed of is automatically set to "L" level. Therefore,
The output of the AND gate 322 which receives the outputs of these latch circuits is at the “L” level. Since this state is held by the latch circuit, the test signal T is at "L" level in a normal operation state.

From this state, when the CAS signal and the W signal become "L" level at the fall of the ▲ ▼ signal, the test state is entered. That is, as shown in FIG. 6 (a), when the signal ▼ falls, the inverter 314 inverts the signal ▼, and the one-shot pulse generation circuit 315 operates as shown in FIG. Pulse signal is generated and given to the AND gate 313. At this time, as shown in FIG.
As shown in (c), if the ▲ ▼ signal and the signal are both "L", the respective signals are inverter 311,
It is inverted by 312 and the AND gate 313 is opened. As a result, the one-shot pulse is applied to the n-channel MOS transistors 316 and 317, and these n-channel MOS transistors 316 and 317 become conductive.

Since the n-channel MOS transistors 316 and 317 are turned on, the signal and the signal falling to the "L" level are applied to the latch circuit composed of the inverters 318 and 319 and the latch circuit composed of the inverters 320 and 321 respectively. As a result, the output of each latch circuit is inverted,
The “H” level signal is applied to AND gate 322. Therefore, the test signal T, which is the output of the AND gate 322, becomes the “H” level, and the test state is entered. After that, since the ▲ ▼ signal and the ▲ ▼ signal and the timing condition of the signal become normal conditions, the above condition is not satisfied, and the n-channel MOS
Since the transistors 316 and 317 are not conducting, the latch circuit is not inverted, the level of the test signal T is held at "H" level, and the test state continues.

As described above, when the test signal T becomes "H" level, the one-shot pulse generation circuit 324 of the switching signal detection circuit 32 shown in FIG. 4 generates a one-shot pulse, and the n-channel MOS transistor 323 becomes conductive. As a result, address signal A ₀ is applied to the latch circuit formed of inverters 325 and 326. When the address signal A ₀ is "L" level, the output of the latch circuit is "H" level,
The output of 328 becomes “L” level. The “H” level test signal T is inverted by the inverter 327 and applied to the OR gate 329. Since the output of the inverter 328 is also at the “L” level, the OR gate 329 outputs the “L” level V _A signal. The AND gate 330 also outputs the "L" level V _B signal.

The "L" level V _A signal is applied to the gate of p channel MOS transistor 211 of cell plate voltage generating circuit 33 shown in FIG. 5, and the V _B signal is applied to the gate of n channel MOS transistor 111. Accordingly, p-channel MOS transistor 211 becomes conductive and n-channel MOS transistor 111 becomes non-conductive. As a result, the Vcc cell plate voltage is output from the power supply line.

If the address signal A ₀ goes to “H” level, the output of the latch circuit goes to “L” level and the output of the inverter 328 goes to “H” level, so the V _A signal output from the OR gate 329 becomes It goes to "H" level and the output of AND gate 330, V _B
The signal also goes to "H" level. As a result, the p-channel MOS transistor 211 of the cell plate voltage generation circuit 33 becomes non-conductive and the n-channel MOS transistor 111 becomes conductive,
The cell plate voltage becomes the ground potential.

In the normal operation, since the since the test signal T is at the "L" level, V _A signal becomes "H" level, V _B signal is at the "L" level, p-channel MOS transistor The 211 and n-channel MOS transistor 111 are not conducting, respectively, and are divided by the resistors 17 and 18 to be 1/2 V.
The cc voltage will be output.

As described above, the cell plate voltage shown in the following table is generated depending on the input condition.

FIG. 7 is a schematic block diagram showing another embodiment of the present invention. In the embodiment shown in FIG. 7, the test state is set by combining the high voltage detection circuit 34 and the timing detection circuit 35. That is, the high voltage detection circuit 34
▼ Detect that high voltage is applied as a signal,
The detection output and timing detection circuit 35 is the above-mentioned second
Similar to the embodiment shown in the figure, the test signal T is generated in response to the detection of the signal and the signal being "L" at the fall of the signal. The switching signal detection circuit 32 and the cell plate voltage generation circuit 33 are the same as those in the embodiment shown in FIG.

8 is a circuit diagram of the high voltage detection circuit shown in FIG. 7, and FIG. 9 is a circuit diagram of the timing detection circuit.

Next, referring to FIG. 8 and FIG. 9, a more specific structure of another embodiment of the present invention will be described. The high voltage detection circuit 34 is similar to that shown in FIG.
S transistors N ₁ , N _2, ... N _n , 105, 108, p-channel MOS transistors 104, 107, 110, and a resistor 103 are included. As shown in FIG. 9, the timing detection circuit 35 receives the output of the AND gate 322 and the AN to which the detection signal C2 from the high voltage detection circuit 34 is input.
The structure is the same as that of FIG. 3 except that the D gate 323 is provided.

Next, the operation of another embodiment of the present invention will be described. Referring to FIG. 8, the high voltage generating circuit 34 is
When high voltage is not applied as a signal, for example ▲
▼ If the signal is 6.5 V or less, the p-channel MOS transistor 107 becomes conductive and becomes "H" in the same manner as described in FIG.
A level signal is applied to n channel MOS transistor 108. As a result, the n-channel MOS transistor 108 becomes conductive, and the output signal C2 becomes "L" level.

When a voltage of 6.5 V or more, for example, 10 V is applied as a signal, a voltage of 3.5 V is generated at the node 102 and n
The channel MOS transistor 105 becomes conductive and the node 106 becomes "L" level. As a result, p-channel MOS transistor 104 becomes conductive, node 102 is pulled up to the level of power supply voltage Vcc, p-channel MOS transistor 107 becomes non-conductive, and n-channel MOS transistor 105 becomes conductive.
This brings node 106 to a full “L” level,
The p-channel MOS transistor 110 becomes conductive and the n-channel MO
The S transistor 108 becomes non-conductive, and the node 109 is “H”.
Become a level. Therefore, the high voltage detection circuit 34 outputs "H".
The level detection signal C2 is included in the timing detection circuit 35.
Given to AND gate 323. Also, the timing detection circuit
In the same manner as in the explanation of FIG. 3 described above, 35 is an AND gate 322 outputs an “H” level signal if the signal and the signal are “L” level at the fall of the signal.
Give to gate 323. As a result, AND gate 323 outputs “H”
The level test signal T is applied to the switching signal detection circuit 32. Switching signal detection circuit 32 causes cell plate voltage generation circuit 33 to generate a cell plate voltage in response to address signal A ₀ in the same manner as described above with reference to FIG.

FIG. 10 is a diagram showing another example of the cell plate voltage generating circuit.

In each of the above embodiments, the cell plate voltage is shown as the power supply voltage Vcc and the ground voltage. However, when the insulating film thickness of the memory cell capacitor becomes thin, the power supply voltage Vcc and the ground voltage are relatively short only during the test. There is a possibility that the reliability of the insulating film may be deteriorated just by applying a voltage. Therefore, the power supply voltage Vc
The voltage may be set to a level closer to 1/2 Vcc than c and the ground voltage. The example shown in FIG. 10 shows such an example. A p-channel MOS transistor 212 is connected in series on the power supply side of the p-channel MOS transistor 211,
An n-channel MO is provided on the ground side of the channel MOS transistor 111.
The S transistor 112 is connected in series. The p-channel MOS transistor 212 has a threshold voltage V _THP and is
OS transistor 112 has a threshold voltage V _THN .
Therefore, the high potential side applied to the cell plate is the power supply voltage Vc.
c-threshold voltage V _THP , and the threshold voltage V
It becomes _THN .

[Effects of the Invention] As described above, according to the present invention, in response to the detection of the test mode, the first voltage higher than the voltage applied during normal use and the second voltage lower than that. Since and are given to one electrode of the capacity of the memory cell,
A memory cell with a small margin can be tested in a short time.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of an embodiment of the present invention. Second
The figure is a schematic block diagram showing another embodiment of the present invention. FIG. 3 is a circuit diagram of the timing detection circuit shown in FIG. FIG. 4 is a circuit diagram showing the switching signal generating circuit shown in FIG. FIG. 5 is a circuit diagram showing the cell plate voltage generating circuit shown in FIG. FIG. 6 is a timing chart for explaining the operation of another embodiment of the present invention. FIG. 7 is a schematic block diagram showing another embodiment of the present invention. FIG. 8 is a circuit diagram of the high voltage detection circuit shown in FIG. FIG. 9 is a circuit diagram of the timing detection circuit shown in FIG. FIG. 10 is a circuit diagram showing the cell plate voltage generating circuit shown in FIG. FIG. 11 is a schematic block diagram showing the overall structure of a read section of a conventional DRAM. FIG. 12 is a diagram showing an outline of the configuration of the memory cell array shown in FIG. FIG. 13 is an electric circuit diagram showing a detailed structure of a pair of bit lines of the bit line pair shown in FIG. FIG. 14 and FIG. 15 are voltage waveform diagrams of each node related to the V bump test. FIG. 16 is a diagram showing the levels of various cell plate electrodes. In the figure, 1 is a memory cell, 2 and 7 are bit lines, 3 is a word line, 5 is a transfer gate, 6 is a capacitor, 8 is a cell plate voltage supply line, 17 and 18 are resistors, and 31 and 35 are timing detection circuits. , 32 is a switching signal detection circuit, 33 is a cell plate voltage generation circuit, 34 is a high voltage detection circuit, 120 and 220 are voltage detection circuits, 101 and 201 are input terminals, N ₁ , N ₂ ... N _n , N ₁ ′, N ₂ ′. …
N _n ′, 105,108,111,112,205,316,317,323 is an n-channel MO
S-transistors 104,107,110,204,207,211,212 are p-channel MOS transistors, 311,312,314,318 to 321,325
328 is an inverter, 313, 322, 323, 330 are AND gates, 315, 324 are one-shot pulse generation circuits, and 329 is an OR gate.

Claims (4)

[Claims] 1. An insulated gate field effect transistor in which one main electrode is connected to a corresponding bit line and a gate electrode is connected to a corresponding word line, and one electrode is the insulated gate field effect transistor. A memory cell having a capacitance connected to the other main electrode of the memory cell, and an output node connected to the other electrode of the capacitance of the memory cell to an intermediate potential between a power supply potential and a ground potential applied during normal operation. A first transistor connected between a power supply potential node to which a power supply potential is applied and the output node, and a ground potential node to which a ground potential is applied and the output node. A second transistor connected to the intermediate potential generating means, wherein the first and second transistors are turned off during normal operation. Is output to the output node, and the first transistor is turned on and the second transistor is turned off during the first test period of the test mode to output the intermediate potential from the intermediate potential generating means. A potential higher than the intermediate potential is output to the output node, and the first transistor is rendered non-conductive and the second transistor is rendered conductive during the second test period of the test mode to generate the intermediate potential generating means. A semiconductor memory device including a cell plate voltage generation circuit for outputting a potential lower than the intermediate potential from the output node to the output node. 2. An insulated gate field effect transistor in which one main electrode is connected to a corresponding bit line and a gate electrode is connected to a corresponding word line, and one electrode is connected to this insulated gate field effect transistor. A memory cell having a capacitance connected to the other main electrode of the transistor, and an output node connected to the other electrode of the capacitance in the memory cell, between the power supply potential and the ground potential applied during normal operation. Intermediate potential generating means for applying a potential, a first potential higher than the intermediate potential from the intermediate potential generating means during normal operation, and the first potential during data writing in the test mode, A first transistor connected between a power supply potential node to which a second potential higher than the first potential is applied at the time of data reading in the test mode and the output node. And a second transistor connected between the output node and a ground potential node to which a ground potential is applied, and the first and second transistors are rendered non-conductive during normal operation to generate the intermediate potential. The intermediate potential from the generating means is output to the output node, and in the test mode, the first transistor becomes conductive,
A semiconductor memory device, comprising: a cell plate voltage generating circuit that outputs a potential applied to the power supply potential node to the output node by turning off the second transistor. 3. An insulated gate field effect transistor in which one main electrode is connected to a corresponding bit line and a gate electrode is connected to a corresponding word line, and one electrode is the insulated gate field effect transistor. A memory cell having a capacity connected to the other main electrode of the memory cell, and to the other electrode of the capacity of the memory cell, in the normal operation, a potential intermediate between the power supply potential and the ground potential applied in the normal operation is applied. The same potential as the power supply potential applied during normal operation is applied when writing data to the memory cell in the test mode, and higher than the power supply potential applied during normal operation when reading data from the memory cell in the test mode. A semiconductor memory device comprising a cell plate voltage generating circuit for applying a potential. 4. An insulated gate field effect transistor in which one main electrode is connected to a corresponding bit line and a gate electrode is connected to a corresponding word line, and one electrode is the insulated gate field effect transistor. A memory cell having a capacity connected to the other main electrode of the memory cell, and to the other electrode of the capacity of the memory cell, in the normal operation, a potential intermediate between the power supply potential and the ground potential applied in the normal operation is applied. , The same potential as the power supply potential given in the normal operation when writing data to the memory cell in the first period in the test mode,
Cell plate voltage generating circuit for applying a potential higher than the power supply potential applied during normal operation during data reading to the memory cell during the above period and applying a ground potential during data writing and during data reading during the second period during the test mode. A semiconductor memory device comprising: