JP2001084799A - Semiconductor memory - Google Patents

Semiconductor memory

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Publication number
JP2001084799A
JP2001084799A JP25968299A JP25968299A JP2001084799A JP 2001084799 A JP2001084799 A JP 2001084799A JP 25968299 A JP25968299 A JP 25968299A JP 25968299 A JP25968299 A JP 25968299A JP 2001084799 A JP2001084799 A JP 2001084799A
Authority
JP
Japan
Prior art keywords
offset
potential
bit line
semiconductor memory
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25968299A
Other languages
Japanese (ja)
Other versions
JP3551858B2 (en
Inventor
Hironori Koike
洋紀 小池
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP25968299A priority Critical patent/JP3551858B2/en
Publication of JP2001084799A publication Critical patent/JP2001084799A/en
Application granted granted Critical
Publication of JP3551858B2 publication Critical patent/JP3551858B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Abstract

PROBLEM TO BE SOLVED: To obtain an offset adding circuit which can set an offset independent from the potential of a signal read out onto a bit line when a memory cell of a semiconductor memory is tested by adding an offset to the potential of a signal read out from the memory cell onto the bit line and monitoring the potential difference of the read out signal on the bit line. SOLUTION: An offset adding circuit OFk comprises a single transistor T1 and a single capacitor CD1 for one bit line BLNk. At the time of test, the transistor T1 is turned on by an offset effective signal OC1, an offset addition control signal OPL1 is pulled from low level to high level, and an offset adding voltage from the capacitor CD1 is superposed on the bit line BLNk through the transistor T1. According to the arrangement, an offset voltage can be generated independently from the potential of the bit line.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】半導体メモリ装置に関し、特に信頼性試験を短時間で行う機能を搭載した半導体メモリ装置に関するものである。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a function of performing a reliability test in a short time.

【0002】 [0002]

【従来の技術】従来の半導体メモリLSIの例として、
ここでは強誘電体メモリ(FeRAM)をとりあげる。
先ず、強誘電体メモリの回路およびその動作について説
明した後、強誘電体メモリの信頼性試験における課題に
ついて述べることにする。
2. Description of the Related Art As an example of a conventional semiconductor memory LSI,
Here, a ferroelectric memory (FeRAM) will be described.
First, the circuit of the ferroelectric memory and its operation will be described, and then the issues in the reliability test of the ferroelectric memory will be described.

【0003】かかる強誘電体メモリの回路および動作については、例えば特開平6−324558号公報や特開平10−233100号公報等に詳しく開示されている。図8に、従来の強誘電体メモリのメモリセルアレイ回路を、また、図9に図8の回路の動作タイミングチャートを夫々示す。 The circuit and operation of such a ferroelectric memory are disclosed in detail in, for example, JP-A-6-324558 and JP-A-10-233100. FIG. 8 shows a memory cell array circuit of a conventional ferroelectric memory, and FIG. 9 shows an operation timing chart of the circuit of FIG.

【0004】先ず、図8の半導体メモリ装置を構成する各要素について説明する。メモリセルアレイMCAは、
1つのトランジスタと1つの強誘電体キャパシタとからなる、いわゆる1T/1C型メモリセルMCjkを、行方向にm行、列方向にn列のアレイ状に配列したものである。 A so-called 1T / 1C type memory cell MCjk composed of one transistor and one ferroelectric capacitor is arranged in an array of m rows in the row direction and n columns in the column direction. 尚、ここで、jは行番号系の添え字を表し、1〜m Here, j represents a line number system subscript, and is 1 to m.
の整数値をとり、またkは列番号系の添え字を表し、1 Takes an integer value of, and k represents a subscript of the column number system, 1
〜nの値をとる。 Takes a value of ~ n. 本明細書においては、今後、特にことわりのない限りこの添え字記法を用いることにする。 In the present specification, this subscript notation will be used in the future unless otherwise specified. First, each element constituting the semiconductor memory device of FIG. 8 will be described. The memory cell array MCA is First, each element individually the semiconductor memory device of FIG. 8 will be described. The memory cell array MCA is
This is a so-called 1T / 1C type memory cell MCjk composed of one transistor and one ferroelectric capacitor, arranged in an array of m rows in the row direction and n columns in the column direction. Here, j represents a subscript of the line number system, and 1 to m This is a so-called 1T / 1C type memory cell MCjk composed of one transistor and one ferroelectric capacitor, arranged in an array of m rows in the row direction and n columns in the column direction. Here, j represents a subscript of the line number system, and 1 to m
And k represents a subscript of the column number system and 1 And k represents a subscript of the column number system and 1
Nn. In the present specification, this subscript notation will be used unless otherwise specified. Nn. In the present specification, this subscript notation will be used unless otherwise specified.

【0005】各メモリセルでは、上記トランジスタのゲ
ート端子にワード線WLj 、同トランジスタのドレイン
端子にビット線BLNk ,BLTk 、上記強誘電体キャ
パシタの一方の電極にプレート線PLj がそれぞれ接続
されている。上記トランジスタのソース端子と、上記強
誘電体キャパシタのプレート線と対極側の電極とは、メ
モリセル内部にて相互に接続されている。
In each memory cell, the word line WLj is connected to the gate terminal of the transistor, the bit lines BLNk and BLTk are connected to the drain terminal of the transistor, and the plate line PLj is connected to one electrode of the ferroelectric capacitor. The source terminal of the transistor, the plate line of the ferroelectric capacitor and the electrode on the counter electrode side are connected to each other inside the memory cell.

【0006】上記ワード線およびプレート線の各信号は
行方向のメモリセルを選択する信号である。これ等ワー
ド線およびプレート線の各信号は、本強誘電体メモリ装
置の外部より入力されるアドレス信号Ai を、アドレス
プリデコーダADPDECによりプリデコードされた信
号XPa を元にXデコーダXDEC、プレートデコーダ
PLDECにてそれぞれ発生される信号である。
The word line and plate line signals are signals for selecting memory cells in the row direction. These word line and plate line signals are obtained by converting an address signal Ai input from outside of the ferroelectric memory device into an X decoder XDEC and a plate decoder PLDEC based on a signal XPa predecoded by an address predecoder ADDEC. , Respectively.

【0007】上記ビット線はBLNk とBLTk との2
本で一対となっており、このビット線対に対し、メモリ
セルから読出されたデータを増幅するためのセンスアン
プSAk が、トランスファゲートTGk を介して接続さ
れている。場合によっては、TGk なしに直接ビット線
対とセンスアンプが接続されていることもある。このセ
ンスアンプの動作は、センスアンプ制御回路SADRV
で発生されるセンスアンプ活性化信号SAEで制御される。 It is controlled by the sense amplifier activation signal SAE generated in. また、このビット線には、ビット線プリチャージ回路PBLk 、読出し動作時に必要なリファレンス電位発生用のダミーメモリセルDCNk 、DCTk も接続されている。 Further, a bit line precharge circuit PBLk, a dummy memory cell DCNk for generating a reference potential required for a read operation, and a DCTk are also connected to this bit line. The above-mentioned bit line has two lines, BLNk and BLTk. The above-mentioned bit line has two lines, BLNk and BLTk.
A pair of bit lines is connected to a sense amplifier SAk for amplifying data read from a memory cell via a transfer gate TGk. In some cases, the bit line pair and the sense amplifier are directly connected without TGk. The operation of this sense amplifier depends on the sense amplifier control circuit SADRV. A pair of bit lines is connected to a sense amplifier SAk for enhancing data read from a memory cell via a transfer gate TGk. In some cases, the bit line pair and the sense amplifier are directly connected without TGk. The operation of this sense amplifier depends on the sense amplifier control circuit SADRV.
And is controlled by a sense amplifier activation signal SAE generated by the control circuit. The bit line is also connected to a bit line precharge circuit PBLk and dummy memory cells DCNk and DCTk for generating a reference potential required for a read operation. And is controlled by a sense amplifier activation signal SAE generated by the control circuit. The bit line is also connected to a bit line precharge circuit PBLk and dummy memory cells DCNk and DCTk for generating a reference potential required for a read operation.

【0008】プリチャージ回路の動作はビット線プリチ
ャージ制御回路PBLCで発生されるビット線プリチャ
ージ信号PBLで制御される。ダミーメモリセルはダミ
ーメモリセル制御回路DWLDECで発生されるダミー
ワード線DWLN,DWLTで制御される。
The operation of the precharge circuit is controlled by a bit line precharge signal PBL generated by a bit line precharge control circuit PBLC. Dummy memory cells are controlled by dummy word lines DWLN and DWLT generated by a dummy memory cell control circuit DWLDEC.

【0009】メモリセルに対してデータの書込みならび
に読出しを行うには、I/Oバス対ION,IOTを介
して行う。アドレス信号Ai をもとにアドレスプリデコ
ーダADPDECにて発生したYアドレスプリデコード
信号YPb により、Y選択信号YSWk のうちの1本を
選択電位(図8の例では、ハイレベル)とする。これに
より、対応するY選択トランスファゲートYSTk が導
通状態となり、アドレス信号Ai にて指定されたビット
線対BLNk ,BLTk に対して、ION,IOTを介
したデータの読み書きが可能となる。
Writing and reading of data to and from a memory cell are performed via an I / O bus pair ION and IOT. One of the Y selection signals YSWk is set to a selection potential (high level in the example of FIG. 8) by a Y address predecode signal YPb generated by the address predecoder ADPDEC based on the address signal Ai. As a result, the corresponding Y selection transfer gate YSTk is rendered conductive, and data can be read from or written to the bit line pair BLNk, BLTk specified by the address signal Ai via ION, IOT.

【0010】図8において、細い線で示された配線(例
えば、SAE,PBL等)は1本の配線を意味し、太い
線で示された配線(Ai ,XPa ,YPb )は複数の配
線を1つにまとめて表したものを意味している。以後、
本明細書の図面における配線の表し方はこのルールに従
うことにする。
In FIG. 8, a thin line (for example, SAE, PBL, etc.) indicates one line, and a thick line (Ai, XPa, YPb) indicates a plurality of lines. It means what is expressed as one. Since then
The way of representing the wiring in the drawings of this specification follows this rule.

【0011】次に、図9を用いて図8に示された回路の
動作について説明する。最初に、待機時には、ワード線
WLj 、プレート線PLj 、ダミーワード線DWLN,
DWLT、Y選択線YSWk 、トランスファゲート信号
TG、センスアンプ活性化信号SAEは、全てロウレベ
ルであり、メモリセルMCjk 、ダミーメモリセルDC
Nk ,DCTk 、センスアンプSAk 、Y選択トランスファゲートYSTk は全て非活性化状態である。 Nk, DCTk, sense amplifier SAk, and Y-selection transfer gate YSTk are all in the inactive state. ビット線プリチャージ信号PBLはハイレベルであり、ビット線BLNk ,BLTk は接地電位にプリチャージされている。 The bit line precharge signal PBL is at a high level, and the bit lines BLNk and BLTk are precharged to the ground potential. Next, the operation of the circuit shown in FIG. 8 will be described with reference to FIG. First, during standby, the word line WLj, plate line PLj, dummy word line DWLN, Next, the operation of the circuit shown in FIG. 8 will be described with reference to FIG. First, during standby, the word line WLj, plate line PLj, dummy word line DWLN,
DWLT, the Y selection line YSWk, the transfer gate signal TG, and the sense amplifier activation signal SAE are all at the low level, and the memory cell MCjk, the dummy memory cell DC DWLT, the Y selection line YSWk, the transfer gate signal TG, and the sense amplifier activation signal SAE are all at the low level, and the memory cell MCjk, the dummy memory cell DC
Nk, DCTk, sense amplifier SAk, and Y select transfer gate YSTk are all inactive. The bit line precharge signal PBL is at a high level, and the bit lines BLNk and BLTk are precharged to the ground potential. Nk, DCTk, sense amplifier SAk, and Y select transfer gate YSTk are all inactive. The bit line precharge signal PBL is at a high level, and the bit lines BLNk and BLTk are precharged to the ground potential.

【0012】ここで、メモリセルMC22がアドレス信
号Ai により選択された場合を例にとり、図8の強誘電
体メモリの読出しおよび書込み動作例について説明す
る。先ず、ビット線プリチャージ信号PBLをロウレベ
ルとし、ビット線をフローティング状態とする。このと
き、ビット線BLNk ,BLTk は先に接地電位にプリ
チャージされていたので、リーク等の影響が無視できる
間はロウレベルを維持する。
Here, an example of reading and writing operations of the ferroelectric memory shown in FIG. 8 will be described by taking as an example a case where the memory cell MC22 is selected by the address signal Ai. First, the bit line precharge signal PBL is set to a low level, and the bit line is set in a floating state. At this time, since the bit lines BLNk and BLTk have been precharged to the ground potential first, the bit lines BLNk and BLTk maintain the low level as long as the influence of leakage or the like can be ignored.

【0013】次に、メモリセルMC22を選択する。具体
的には、ワード線WL2 をハイレベル、プレート線PL
2 をハイレベルとする。WL2 のハイレベルは、通常、
セルトランジスタのしきい値電位Vtn分を補償するため
に、(電源電位+Vtn)程度に昇圧した電位である。P
L2 のハイレベルは、通常、電源電位である。なお、W
L2 およびPL2 をハイレベルにすることにより、この行に連なるメモリセルMC2kは全て選択状態となる。 By setting L2 and PL2 to high levels, all the memory cells MC2k connected to this row are selected. すなわち、プレート線PL2 がハイレベルとなることにより、PL2 とビット線BLTk との間に電位差が発生する。 That is, when the plate wire PL2 becomes high level, a potential difference is generated between PL2 and the bit wire BLTk. これは、j=2の行に接続されているメモリセル内の強誘電体キャパシタに対して、前記電位差が印加されるということである。 This means that the potential difference is applied to the ferroelectric capacitor in the memory cell connected to the row j = 2. その電位差に応じた電荷が強誘電体キャパシタからビット線BLTk に出力されることにより、BLTk 上に読出し電位があらわれる。 A read potential appears on the BLTk when the electric charge corresponding to the potential difference is output from the ferroelectric capacitor to the bit line BLTk. Next, the memory cell MC22 is selected. Specifically, the word line WL2 is set to the high level, Next, the memory cell MC22 is selected. Specifically, the word line WL2 is set to the high level,
Set 2 to high level. The high level of WL2 is usually Set 2 to high level. The high level of WL2 is usually
In order to compensate for the threshold potential Vtn of the cell transistor, this is a potential that has been boosted to about (power supply potential + Vtn). P In order to compensate for the threshold potential Vtn of the cell transistor, this is a potential that has been boosted to about (power supply potential + Vtn). P
The high level of L2 is usually the power supply potential. Note that W The high level of L2 is usually the power supply potential. Note that W
By setting L2 and PL2 to high level, all the memory cells MC2k connected to this row are in the selected state. That is, when the plate line PL2 goes high, a potential difference is generated between PL2 and the bit line BLTk. This means that the potential difference is applied to the ferroelectric capacitors in the memory cells connected to the row of j = 2. When a charge corresponding to the potential difference is output from the ferroelectric capacitor to the bit line BLTk, a read potential appears on BLTk. By setting L2 and PL2 to high level, all the memory cells MC2k connected to this row are in the selected state. That is, when the plate line PL2 goes high, a potential difference is generated between PL2 and the bit line BLTk. This means that the potential difference is applied to the communicating voltages in the memory cells connected to the row of j = 2. When a charge corresponding to the potential difference is output from the ferroelectric capacitors to the bit line BLTk, a read potential appears on BLTk.

【0014】他方、BLTk と対となっているビット線
BLNk には、BLTk 上にあらわれたビット線読出し
電位が、データ“0”に対応するものか、データ“1”
に対応するものかを判別するためのリファレンス電位を
発生させる必要がある。このリファレンス電位はダミー
メモリセルDCNk によって生成される。DCNk は、
ダミーワード線DWLNをハイレベルとすることにより
活性化され、ビット線BLNk 上にリファレンス電位を
出力する。リファレンス電位の具体的な発生方法として
は、例えば、特開平10−233100号公報、特開平
9−97496号公報に開示されているもの等がある。
ここではリファレンス電位発生方法に関する詳細な説明は省略する。 Here, a detailed description of the reference potential generation method will be omitted. On the other hand, on the bit line BLNk paired with BLTk, the bit line read potential appearing on BLTk corresponds to data "0" or data "1". On the other hand, on the bit line BLNk paired with BLTk, the bit line read potential appearing on BLTk corresponds to data "0" or data "1".
It is necessary to generate a reference potential for determining whether the reference potential is satisfied. This reference potential is generated by the dummy memory cell DCNk. DCNk is It is necessary to generate a reference potential for determining whether the reference potential is satisfied. This reference potential is generated by the dummy memory cell DCNk. DCNk is
It is activated by setting the dummy word line DWLN to high level, and outputs a reference potential on the bit line BLNk. Specific methods for generating the reference potential include, for example, those disclosed in JP-A-10-233100 and JP-A-9-97496. It is activated by setting the dummy word line DWLN to high level, and outputs a reference potential on the bit line BLNk. Specific methods for generating the reference potential include, for example, those disclosed in JP-A-10-233100 and JP- A-9-97496.
Here, a detailed description of the reference potential generation method is omitted. Here, a detailed description of the reference potential generation method is omitted.

【0015】ビット線BLTk にメモリセルMC2kから
の読出し電位が、ビット線BLNkにダミーメモリセル
DCNk からのリファレンス電位が、それぞれ出力され
た後、トランスファゲート信号TGをハイレベルとし
て、このBLTk とBLNk 上の電位をセンスアンプS
Ak に伝達する。続いて、センスアンプ活性化信号SA
Eをハイレベルとすることにより、センスアンプSAk
を活性化して、BLNkとBLTk との電位差を差動増
幅する。
After the read potential from the memory cell MC2k is output to the bit line BLTk and the reference potential from the dummy memory cell DCNk is output to the bit line BLNk, the transfer gate signal TG is set to the high level. Potential of the sense amplifier S
To Ak. Subsequently, the sense amplifier activation signal SA To Ak. Previously, the sense amplifier activation signal SA
By setting E to a high level, the sense amplifier SAk By setting E to a high level, the sense amplifier SAk
Is activated to differentially amplify the potential difference between BLNk and BLTk. Is activated to differentially excited the potential difference between BLNk and BLTk.

【0016】読出し動作を行う場合には、Y選択信号Y
SW2 をハイレベルとし、Y選択トランスファゲートY
ST2 を導通させる。こうして、ビット線対BLN2 ,
BLT2 とI/Oバス対ION,IOTとを接続し、B
LN2 ,BLT2 の差動増幅されたデータをION,I
OTを介して出力バッファに転送する。また、書込み動作を行う場合には、データ入力バッファから、ION,

IOTを介してビット線対BLN2 ,BLT2 に所望の書込みデータに対応する電位を書込む。 The potential corresponding to the desired write data is written to the bit line pairs BLN2 and BLT2 via IOT. When performing a read operation, the Y selection signal Y When performing a read operation, the Y selection signal Y
SW2 is set to the high level, and the Y selection transfer gate Y SW2 is set to the high level, and the Y selection transfer gate Y
ST2 is made conductive. Thus, the bit line pair BLN2, ST2 is made conductive. Thus, the bit line pair BLN2,
BLT2 is connected to the I / O bus pair ION, IOT, and B BLT2 is connected to the I / O bus pair ION, IOT, and B
The differentially amplified data of LN2 and BLT2 is transferred to ION, ILT. The differentially amplified data of LN2 and BLT2 is transferred to ION, ILT.
Transfer to output buffer via OT. Also, when performing a write operation, ION, Transfer to output buffer via OT. Also, when performing a write operation, ION,
A potential corresponding to desired write data is written to the bit line pair BLN2, BLT2 via the IOT. A potential corresponding to desired write data is written to the bit line pair BLN2, BLT2 via the IOT.

【0017】上に述べた動作は、破壊読出し動作(デー
タ読出しを行った後、メモリセルの記憶データは破壊さ
れている)であるので、記憶を保持するためには、メモ
リセルへのデータ再書込み動作が必要である。強誘電体
メモリにおけるメモリセルへのデータ再書込み動作は次
の動作によって達成される。(1)再書込みデータ
“0”に対しては、ビット線=ロウレベル、プレート線
=ハイレベルという状態から、プレート線=ロウレベル
として、強誘電体キャパシタにかかる電圧をゼロとす
る。(2)再書き込みデータ“1”に対しては、ビット
線=ハイレベル,プレート線=ロウレベルという状態か
ら、ビット線=ロウレベルとして、強誘電体キャパシタ
にかかる電圧をゼロとする。
The above-described operation is a destructive read operation (the data stored in the memory cell has been destroyed after the data is read). A write operation is required. The operation of rewriting data to the memory cell in the ferroelectric memory is achieved by the following operation. (1) With respect to the rewrite data "0", from the state where the bit line is at the low level and the plate line is at the high level, the plate line is at the low level and the voltage applied to the ferroelectric capacitor is set to zero. (2) For the rewrite data "1", the bit line is set to the low level from the state where the bit line is set to the high level and the plate line is set to the low level, and the voltage applied to the ferroelectric capacitor is set to zero.

【0018】図9のタイミングチャートで説明すると、
先ず、センスアンプによるデータ増幅後にロウレベルと
なっているビット線につながるメモリセルに対しては、
先にプレート線がハイレベル、ビット線がロウレベルと
なっている状態から、プレート線がロウレベルになった
ときに、メモリセル内の強誘電体キャパシタにかかる電
圧がゼロとなる。従って、Y選択信号YSW2 をロウレ
ベルとした後、プレート線PL2 をロウレベルとした時
点でデータ再書込みが終了する。
Referring to the timing chart of FIG.
First, for a memory cell connected to a bit line that is at a low level after data amplification by a sense amplifier,
When the plate line goes low from the state where the plate line goes high and the bit line goes low first, the voltage applied to the ferroelectric capacitor in the memory cell becomes zero. Therefore, after the Y selection signal YSW2 is set to low level, the data rewriting is completed when the plate line PL2 is set to low level. When the plate line goes low from the state where the plate line goes high and the bit line goes low first, the voltage applied to the ferroelectric capacitor in the memory cell becomes zero. Therefore, after the Y selection signal YSW2 is set to low level , the data rewriting is completed when the plate line PL2 is set to low level.

【0019】センスアンプによるデータ増幅後にハイレ
ベルとなっているビット線につながるメモリセルに対し
ては、プレート線がロウレベルになったときに、ビット
線がハイレベルとなっており、続けてビット線をロウレ
ベルとしたときに、メモリセル内の強誘電体キャパシタ
にかかる電圧がゼロとなる。従って、センスアンプ活性
化信号SAEをロウレベル、ビット線プリチャージ信号
PBLをハイレベルとして、ビット線電位を接地電位
(=ロウレベル)にした時点でデータ再書込みが終了す
る。データ再書込み動作の後、ワード線WL2 をロウレ
ベルとして、メモリセルを非選択状態に戻す。最後に、
トランスファゲート信号TGをロウレベルとする。 The transfer signal TG is set to the low level. 以上で、強誘電体メモリに対する読出しもしくは書込み動作の1サイクルが完了である。 This completes one cycle of the read or write operation for the ferroelectric memory. For a memory cell connected to a bit line which is at a high level after data amplification by a sense amplifier, the bit line is at a high level when the plate line is at a low level. Becomes low level, the voltage applied to the ferroelectric capacitor in the memory cell becomes zero. Therefore, when the sense amplifier activation signal SAE is set to the low level, the bit line precharge signal PBL is set to the high level, and the bit line potential is set to the ground potential (= low level), the data rewriting ends. After the data rewriting operation, the word line WL2 is set to the low level to return the memory cells to the non-selected state. Finally, For a memory cell connected to a bit line which is at a high level after data amplification by a sense amplifier, the bit line is at a high level when the plate line is at a low level. Becomes low level, the voltage applied to the Therefore, when the sense amplifier activation signal SAE is set to the low level, the bit line precharge signal PBL is set to the high level, and the bit line potential is set to the ground potential ( = low level), the data rewriting ends. After the data rewriting operation, the word line WL2 is set to the low level to return the memory cells to the non-selected state. Finally,
The transfer gate signal TG is set to low level. Thus, one cycle of the read or write operation for the ferroelectric memory is completed. The transfer gate signal TG is set to low level. Thus, one cycle of the read or write operation for the efficiently memory is completed.

【0020】ここまでに述べた強誘電体メモリの動作は、1T/1C型メモリセル1つに対し、1ビットのデータを記憶させる、いわゆる「1T/1C型動作方式」
と呼ばれるものであった。この方式は、上にも述べたように、読出し動作時にリファレンス電位を必要とする。
それに対し、1T/1C型メモリセル2つに対し、1ビットのデータを記憶させる、いわゆる「2T/2C型動作方式」と呼ばれる方式も存在する。
The operation of the ferroelectric memory described above is a so-called "1T / 1C type operation method" in which one bit data is stored in one 1T / 1C type memory cell.

Was called. This method requires a reference potential at the time of a read operation, as described above. Was called. This method requires a reference potential at the time of a read operation, as described above.
On the other hand, there is a method called a “2T / 2C type operation method” that stores 1-bit data in two 1T / 1C type memory cells. On the other hand, there is a method called a “2T / 2C type operation method” that stores 1-bit data in two 1T / 1C type memory cells.

【0021】この方式では、ビット線のN側(BLNk
)とT側(BLTk )に接続されている1T/1C型メモリセル同士をペアとして、1ビットの記憶単位とする。これを図8を用いて説明する。MC11とMC21、M
C12とMC22、…というようにペアをつくる。BLN1
とBLT1 は差動動作を行うため、BLN1 がハイレベルならばBLT1 はロウレベル、逆に、BLN1 がロウレベルならばBLT1 はハイレベルとなる。すなわち、

各々の場合について、MC11とMC21には、互いに逆極性のデータが保持されることになる。 In each case, MC11 and MC21 will hold data of opposite polarities. 例えば、前者の場合を(2T/2C型動作方式に対する)データ“0”、 For example, in the former case, the data "0" (for the 2T / 2C type operation method),
後者の場合をデータ“1”というように割り付ける。 The latter case is assigned as data "1". こうすることで、2つの1T/1C型メモリセルに対して1ビットのデータ記憶を行うことができる。 By doing so, 1-bit data storage can be performed for two 1T / 1C type memory cells. In this method, the N side of the bit line (BLNk In this method, the N side of the bit line (BLNk
) And 1T / 1C type memory cells connected to the T side (BLTk) are paired to form a 1-bit storage unit. This will be described with reference to FIG. MC11 and MC21, M ) And 1T / 1C type memory cells connected to the T side (BLTk) are paired to form a 1-bit storage unit. This will be described with reference to FIG. MC11 and MC21, M
Make a pair with C12 and MC22, etc. BLN1 Make a pair with C12 and MC22, etc. BLN1
Since BLT1 and BLT1 perform a differential operation, if BLN1 is at a high level, BLT1 is at a low level. Conversely, if BLN1 is at a low level, BLT1 is at a high level. That is, Since BLT1 and BLT1 perform a differential operation, if BLN1 is at a high level, BLT1 is at a low level. Journey, if BLN1 is at a low level, BLT1 is at a high level. That is,
In each case, data of opposite polarities are held in MC11 and MC21. For example, in the former case, data “0” (for the 2T / 2C type operation system), In each case, data of opposite polarities are held in MC11 and MC21. For example, in the former case, data “0” (for the 2T / 2C type operation system),
The latter case is assigned as data "1". In this way, 1-bit data can be stored in two 1T / 1C type memory cells. The latter case is assigned as data "1". In this way, 1-bit data can be stored in two 1T / 1C type memory cells.

【0022】この場合、メモリセル自身から、ビット線
対BLN1 ,BLT1 上に差動でデータ電位が出力され
るので、1T/1C型動作方式の場合に必要であった読
出し動作時のリファレンス電位がなくても、センスアン
プが差動増幅動作できる。つまり、リファレンス電位が
不要である。
In this case, since the data potential is differentially output from the memory cell itself to the pair of bit lines BLN1 and BLT1, the reference potential at the time of the read operation required for the 1T / 1C type operation system is reduced. Without this, the sense amplifier can perform the differential amplification operation. That is, no reference potential is required.

【0023】以上に説明してきた強誘電体メモリにおい
て、繰り返し書込みもしくは読出しに対するメモリセル
の耐性を評価することが、強誘電体メモリの信頼性試験
上の重要な項目となっている。具体的な故障モードとし
て、強誘電体メモリのメモリセルに対し、データを多数
回繰り返して書込むことによって強誘電体特性が劣化
し、ついには正しい記憶動作ができなくなるということ
が一般に知られている。従来、このような繰り返し書込
み/読出しに対する耐性の試験として、特開平11−1
49796号公報に記載されているものがある。 Some are described in Japanese Patent Application Laid-Open No. 49996. In the ferroelectric memory described above, evaluating the resistance of the memory cell to repeated writing or reading is an important item in the reliability test of the ferroelectric memory. As a specific failure mode, it is generally known that ferroelectric characteristics are degraded by repeatedly writing data to a memory cell of a ferroelectric memory many times, and finally, a correct storage operation cannot be performed. I have. Conventionally, as a test of resistance to such repeated writing / reading, Japanese Patent Application Laid-Open No. As a specific failure mode, it is generally known that particularly characteristic are degraded by repeatedly writing. In the reproduced memory described above, evaluating the resistance of the memory cell to repeated writing or reading is an important item in the reliability test of the efficiently memory. data to a memory cell of a recently memory many times, and finally, a correct storage operation cannot be performed. I have. Conventionally, as a test of resistance to such repeated writing / reading, Japanese Patent Application Laid-Open No.
There is one described in Japanese Patent No. 49796. There is one described in Japanese Patent No. 49796.

【0024】この試験方法は、読出し動作時にデータの
判別を行うセンスアンプに意図的にオフセットを付加す
ることにより、正しい読出し動作に必要なメモリセルか
らの読出し電位差が、当該オフセット量よりも小さいメ
モリセルを含む強誘電体メモリ装置を、初期試験の段階
で不良とするというものである。
According to this test method, an offset is intentionally added to a sense amplifier that determines data at the time of a read operation, so that a difference in read potential from a memory cell required for a correct read operation is smaller than the offset amount. A ferroelectric memory device including a cell is determined to be defective at an initial test stage.

【0025】図10に特開平11−149796号公報
に記載されている強誘電体メモリ回路を示す。強誘電体
メモリとして動作するためには、図8に示されているよ
うな構成が必要であるが、図10では、簡単のために、
「センスアンプにオフセットを付加する」という機能の
説明に必要な部分のみを抜き出して記載した。また、図
8と同様の役割を果たす部分については、同じ記号を用
いて説明を省略する。
FIG. 10 shows a ferroelectric memory circuit described in JP-A-11-149796. In order to operate as a ferroelectric memory, a configuration as shown in FIG. 8 is necessary, but in FIG. 10, for simplicity,
Only the parts necessary for the description of the function of "adding an offset to the sense amplifier" are extracted and described. In addition, parts that perform the same functions as those in FIG. Only the parts necessary for the description of the function of "adding an offset to the sense amplifier" are extracted and described. In addition, parts that perform the same functions as those in FIG.

【0026】図10において、記号OFk で示されている部分がセンスアンプにオフセットを付加する回路である。この回路はトランジスタ4つからなり、ゲート端子とドレイン端子を交差接続したトランジスタTR1 ,T
R2 に、スイッチングトランジスタTR3 ,TR4 が接続されている。 Switching transistors TR3 and TR4 are connected to R2. TR3 ,TR4 は、それぞれオフセット有効化信号OC1 ,OC2 によって制御されている。 TR3 and TR4 are controlled by offset activation signals OC1 and OC2, respectively. In FIG. 10, a portion indicated by the symbol OFk is a circuit for adding an offset to the sense amplifier. This circuit comprises four transistors, transistors TR1 and TR1 having gate terminals and drain terminals cross-connected. In FIG. 10, a portion indicated by the symbol OFk is a circuit for adding an offset to the sense amplifier. This circuit is four transistors, utilizing TR1 and TR1 having gate terminals and drain terminals cross-connected.
Switching transistors TR3 and TR4 are connected to R2. TR3 and TR4 are controlled by offset enable signals OC1 and OC2, respectively. Switching transistors TR3 and TR4 are connected to R2. TR3 and TR4 are controlled by offset enable signals OC1 and OC2, respectively.

【0027】この回路でセンスアンプにオフセットが付加される機構は次の通りである。通常のセンスアンプの動作においては、オフセット有効化信号OC1 ,OC2
ともにロウレベルである。 Both are low level. このときには、センスアンプは通常の差動増幅動作を行い、理想的にはオフセットはない。 At this time, the sense amplifier performs a normal differential amplification operation, and ideally there is no offset. 但し、センスアンプの差動対トランジスタTR5 However, the differential pair transistor TR5 of the sense amplifier
とTR6 、TR7 とTR8 との間のしきい値電圧等の製造上の特性ばらつきに起因する数十mV以下程度の微小なオフセットは存在しうるが、ここではその微小オフセットは無視するものとする。 There may be a minute offset of several tens of mV or less due to variations in manufacturing characteristics such as the threshold voltage between TR6 and TR6, and TR7 and TR8, but the minute offset shall be ignored here. .. The mechanism for adding an offset to the sense amplifier in this circuit is as follows. In the normal operation of the sense amplifier, the offset enable signals OC1 and OC2 The mechanism for adding an offset to the sense amplifier in this circuit is as follows. In the normal operation of the sense amplifier, the offset enable signals OC1 and OC2
Both are at low level. At this time, the sense amplifier performs a normal differential amplification operation, and ideally has no offset. However, the differential pair transistor TR5 of the sense amplifier Both are at low level. At this time, the sense amplifier performs a normal differential amplification operation, and ideally has no offset. However, the differential pair transistor TR5 of the sense amplifier
And a small offset of several tens of mV or less due to variations in manufacturing characteristics such as a threshold voltage between the transistors TR6 and TR7 and the transistor TR8. However, the small offset is ignored here. . And a small offset of several tens of mV or less due to variations in manufacturing characteristics such as a threshold voltage between the utilizing TR6 and TR7 and the transistor TR8. However, the small offset is ignored here.

【0028】オフセットを付加する場合には、OC1 をハイレベル、OC2 をロウレベルとした状態で、信号S
ANをロウレベル、SAPをハイレベルとして、センスアンプSAk を活性化する。すると、トランジスタTR

3 が導通状態、TR4 が非導通状態となっているために、ビット線BLNj の電位が、BLTj の電位に比べて、ロウレベル側に引かれやすくなる。 Since 3 is in the conductive state and TR4 is in the non-conducting state, the potential of the bit line BLNj is more likely to be drawn to the low level side than the potential of BLTj. これは、等価的には、センスアンプ内差動対トランジスタTR5 の導通時の電流(オン電流)が、オフセットトランジスタTR This means that, equivalently, the current (on-current) at the time of conduction of the differential pair transistor TR5 in the sense amplifier is the offset transistor TR.
1 のオン電流分だけ、TR6 のオン電流よりも大きくなっているというアンバランスが生じていることに等しい。 It is equivalent to the imbalance that the on-current of 1 is larger than the on-current of TR6. このことにより、BLNj がハイレベルになるような読出しデータに対して厳しい動作条件となっている。 As a result, the operating conditions are strict for the read data such that BLNj becomes high level.
いいかえると、BLNj がハイレベルとなるようなデータ読出し動作に対してオフセットが付加された状態となっている。 In other words, an offset is added to the data read operation such that BLNj becomes a high level. When an offset is to be added, the signal S is kept high while OC1 is at a high level and OC2 is at a low level. When an offset is to be added, the signal S is kept high while OC1 is at a high level and OC2 is at a low level.
By setting AN to low level and SAP to high level, the sense amplifier SAk is activated. Then, the transistor TR By setting AN to low level and SAP to high level, the sense amplifier SAk is activated. Then, the transistor TR
Since 3 is conducting and TR4 is non-conducting, the potential of the bit line BLNj is more likely to be pulled to the low level side than the potential of BLTj. This is equivalent to the fact that the current (on-current) when the differential pair transistor TR5 in the sense amplifier is conducting becomes equal to the offset transistor TR5. Since 3 is conducting and TR4 is non-conducting, the potential of the bit line BLNj is more likely to be pulled to the low level side than the potential of BLTj. This is equivalent to the fact that the current (on-current) when the differential pair transistor TR5 in the sense amplifier is conducting becomes equal to the offset transistor TR5.
This is equivalent to the occurrence of an imbalance that the ON current of 1 is larger than the ON current of TR6. This places severe operating conditions on read data such that BLNj goes high. This is equivalent to the occurrence of an imbalance that the ON current of 1 is larger than the ON current of TR6. This places severe operating conditions on read data such that BLNj goes high.
In other words, an offset is added to a data read operation in which BLNj goes high. In other words, an offset is added to a data read operation in which BLNj goes high.

【0029】逆に、BLNj がロウレベルとなるようなデータ読出し動作に対してオフセットを付加するには、
OC1 をロウレベル、OC2 をハイレベルとする。 OC1 is the low level and OC2 is the high level. 上記のようにしてセンスアンプにオフセットを付加した試験を行うことにより、読出し電位差の小さいメモリセルが含まれる強誘電体メモリは、正しいデータ読出し動作が行われず不良となる。 By performing the test in which the offset is added to the sense amplifier as described above, the ferroelectric memory including the memory cell having a small read potential difference is defective because the correct data read operation is not performed. 製造直後の段階において、このようにビット線に読出される信号電位差の小さいメモリセルは繰り返し動作に対して弱い傾向がある。 In the stage immediately after manufacturing, a memory cell having a small signal potential difference read into a bit line in this way tends to be vulnerable to repeated operation. 従って、この試験方法を用いると、繰り返し耐性の悪い強誘電体メモリを初期段階試験において選別することができるという効果がある。 Therefore, using this test method has the effect of being able to select ferroelectric memories having poor repeatability in the initial stage test. この試験方式をオフセットセンスアンプ試験方式と呼ぶ。 This test method is called an offset sense amplifier test method. Conversely, to add an offset to a data read operation in which BLNj goes low, Poorly, to add an offset to a data read operation in which BLNj goes low,
OC1 is at a low level and OC2 is at a high level. By performing the test in which an offset is added to the sense amplifier as described above, a ferroelectric memory including a memory cell with a small read potential difference fails to perform a correct data read operation and becomes defective. Immediately after manufacturing, memory cells with a small signal potential difference read to the bit lines in this manner tend to be weak against repeated operations. Therefore, the use of this test method has an effect that a ferroelectric memory having poor repetition resistance can be selected in the initial stage test. This test method is called an offset sense amplifier test method. OC1 is at a low level and OC2 is at a high level. By performing the test in which an offset is added to the sense amplifier as described above, a particularly memory including a memory cell with a small read potential difference fails to perform a correct data read operation and becomes defective. Immediately after manufacturing, memory cells with a small signal potential difference read to the bit lines in this manner tend to be weak against repeated operations. Therefore, the use of this test method has an effect that a operating memory. having poor repetition resistance can be selected in the initial stage test. This test method is called an offset sense amplifier test method.

【0030】 [0030]

【発明が解決しようとする課題】しかしながら、従来の
オフセットセンスアンプ試験方式には、次に述べるよう
な問題点がある。従来のオフセット回路は、上に述べた
ように、センスアンプ差動対トランジスタ(図10のT
R5 とTR6 )のオン電流にアンバランスを生じさせることによって、オフセットを発生させるというものであった。 The offset was generated by causing an imbalance in the on-currents of R5 and TR6). 図10に示された従来回路の場合、オフセット回路内のトランジスタTR1 のオン電流は、このトランジスタTR1 のゲート−ソース間電位差に依存する。 In the case of the conventional circuit shown in FIG. 10, the on-current of the transistor TR1 in the offset circuit depends on the gate-source potential difference of the transistor TR1. ソース電位はここでは接地電位なので、ゲート電位すなわちBLTj の電位がトランジスタTR1 のオン電流に依存することになる。 Since the source potential is the ground potential here, the gate potential, that is, the potential of BLTj, depends on the on-current of the transistor TR1. However, the conventional offset sense amplifier test method has the following problems. The conventional offset circuit, as described above, uses a differential pair of sense amplifier transistors (T However, the conventional offset sense amplifier test method has the following problems. The conventional offset circuit, as described above, uses a differential pair of sense amplifier transistors (T
An offset is generated by causing an imbalance in the ON currents of R5 and TR6). In the case of the conventional circuit shown in FIG. 10, the ON current of the transistor TR1 in the offset circuit depends on the potential difference between the gate and the source of the transistor TR1. Since the source potential is the ground potential here, the gate potential, that is, the potential of BLTj depends on the ON current of the transistor TR1. An offset is generated by causing an imbalance in the ON currents of R5 and TR6). In the case of the conventional circuit shown in FIG. 10, the ON current of the transistor TR1 in the offset circuit depends on the potential difference between the gate and the source of the transistor TR1. Since the source potential is the ground potential here, the gate potential, that is, the potential of BLTj depends on the ON current of the transistor TR1.

【0031】図10の回路により生成されるオフセット量を、ビット線BLTj の電位の関数として、回路シミュレーションを用いて計算した。その結果を図11に示す。この計算は、ゲート長0.55μmのトランジスタを用いた強誘電体メモリのセンスアンプおよびオフセット回路を前提としている。図11から明らかなように、
このオフセット回路によって生成されるオフセット量はビット線電位に極めて強く依存する。 The amount of offset generated by this offset circuit is extremely dependent on the bit line potential. ビット線電位が0.5〜2.0Vの範囲で、オフセット量が100〜8 The bit line potential is in the range of 0.5 to 2.0 V, and the offset amount is 100 to 8.
50mVも変わっている。 50 mV has also changed. このようにオフセット量が読出しビット線電位に強く依存すると、最適なオフセット量の設定が困難になる。 If the offset amount strongly depends on the read bit line potential in this way, it becomes difficult to set the optimum offset amount. つまり、オフセットが効きすぎて、本来は信頼性上問題のないレベルにある強誘電体メモリまで不良と選別されたり、逆にオフセットが効かず、信頼性上問題ある強誘電体メモリが選別されなかったりするという問題が生ずる。 In other words, the offset is too effective, and even the ferroelectric memory that is originally at a level that does not have a reliability problem is selected as defective, or conversely, the offset does not work and the ferroelectric memory that has a reliability problem is not selected. There is a problem of offsetting. The offset generated by the circuit of FIG. 10 was calculated using a circuit simulation as a function of the potential of the bit line BLTj. The result is shown in FIG. This calculation is based on a sense amplifier and an offset circuit of a ferroelectric memory using a transistor having a gate length of 0.55 μm. As is clear from FIG. The offset generated by the circuit of FIG. 10 was calculated using a circuit simulation as a function of the potential of the bit line BLTj. The result is shown in FIG. This calculation is based on a sense amplifier and an offset circuit of a recently memory using a transistor having a gate length of 0.55 μm. As is clear from FIG.
The amount of offset generated by this offset circuit depends very strongly on the bit line potential. When the bit line potential is in the range of 0.5 to 2.0 V and the offset amount is 100 to 8 The amount of offset generated by this offset circuit depends very strongly on the bit line potential. When the bit line potential is in the range of 0.5 to 2.0 V and the offset amount is 100 to 8
50 mV has also changed. When the offset amount strongly depends on the read bit line potential, it is difficult to set an optimum offset amount. In other words, a ferroelectric memory that is too effective and that is originally at a level where there is no problem in reliability is classified as defective, or a ferroelectric memory that is not effective in offset and that is problematic in reliability cannot be selected. Problem arises. 50 mV has also changed. When the offset amount strongly depends on the read bit line potential, it is difficult to set an optimum offset amount. In other words, a particularly memory that is too effective and that is originally at a level where there is no problem in reliability is classified as defective, or a frequently memory that is not effective in offset and that is problematic in reliability cannot be selected. Problem arises.

【0032】本発明は、上記問題点を克服すべくなされたものであってその目的とするところは、ビット線上に読出される読出し信号電位に依存せずオフセット量を設定できるオフセット付加回路を有する半導体メモリ装置を提供することにある。 The present invention has been made to overcome the above problems, and has as its object to provide an offset adding circuit capable of setting an offset amount without depending on a read signal potential read on a bit line. An object of the present invention is to provide a semiconductor memory device.

【0033】 [0033]

【課題を解決するための手段】本発明による半導体メモ
リ装置は、データを記憶する複数のメモリセルをマトリ
ックス状に配列したメモリセルアレイと、アドレスに従
って前記メモリセルアレイ内のメモリセルを選択するた
めのワード線と、この選択されたメモリセルに対してデ
ータの書込み及び読出しをなすためのビット線と、この
選択されたメモリセルから前記ビット線上に読出された
データ信号の電位差を増幅するセンスアンプ回路とを含
む半導体メモリ装置であって、前記ビット線上に読出さ
れたデータ信号の電位差を減少させる電圧であって、か
つ前記ビット線上に読出される信号電圧に依存しないオ
フセット電圧を前記ビット線に付加するオフセット付加
手段を含むことを特徴とする。
A semiconductor memory device according to the present invention comprises a memory cell array in which a plurality of memory cells for storing data are arranged in a matrix, and a word for selecting a memory cell in the memory cell array according to an address. A bit line for writing and reading data to and from the selected memory cell; and a sense amplifier circuit for amplifying a potential difference of a data signal read from the selected memory cell onto the bit line. And adding an offset voltage to the bit line, the offset voltage being a voltage for reducing a potential difference of a data signal read on the bit line and independent of a signal voltage read on the bit line. It is characterized by including offset adding means.

【0034】そして、前記オフセット付加手段は、ゲー
トにオフセット有効化信号が供給され、ソースに前記ビ
ット線が接続された第一の電界効果トランジスタと、一
方の電極に前記トランジスタのドレイン端子が接続され
他方の電極にオフセット付加制御信号が供給されたキャ
パシタとを有することを特徴とする。
The offset adding means includes a first field-effect transistor having a gate supplied with an offset enable signal, a source connected to the bit line, and a drain terminal connected to one electrode. A capacitor to which the offset addition control signal is supplied to the other electrode.

【0035】上記構成に加えて更に、待機時において前
記オフセット付加制御信号を第一の電位に設定し、試験
時において前記オフセット有効化信号を前記第一の電界
効果トランジスタが導通する電位に設定し、続いて前記
オフセット付加制御信号を前記第一の電位とは異なる第
二の電位に設定する制御手段を含むことを特徴とする。
In addition to the above configuration, the offset addition control signal is set to a first potential during standby, and the offset enable signal is set to a potential at which the first field effect transistor conducts during a test. And a control unit for setting the offset addition control signal to a second potential different from the first potential.

【0036】そして、前記オフセット付加手段として、
センスアンプの一対の第一及び第二の差動入力端子に夫々接続された第一及び第二のオフセット付加回路が設けられており、更に、待機時において前記第一及び第二のオフセット付加回路に対応する第一及び第二のオフセット付加制御信号を第一及び第二の電位の中間電位に設定し、試験時において前記第一及び第二のオフセット付加回路に対応する第一及び第二のオフセット有効化信号を、前記第一及び第二のオフセット付加回路に対応する第一及び第二の電界効果トランジスタが導通する電位に設定し、続いて前記第一のオフセット付加制御信号を前記中間電位から前記第二の電位に設定すると共に、前記第二のオフセット付加制御信号を前記中間電位から前記第一の電位に設定する制御手段を含むことを特徴とする。 The first and second offset addition circuits connected to the pair of first and second differential input terminals of the sense amplifier, respectively, are provided, and further, the first and second offset addition circuits are provided during standby. The first and second offset addition control signals corresponding to the above are set to the intermediate potentials of the first and second potentials, and the first and second offset addition circuits corresponding to the first and second offset addition circuits are set at the time of the test. The offset activation signal is set to the potential at which the first and second electric field effect transistors corresponding to the first and second offset addition circuits conduct, and then the first offset addition control signal is set to the intermediate potential. The second potential is set to the second potential, and the second offset addition control signal is set from the intermediate potential to the first potential. Then, as the offset adding means, Then, as the offset adding means,
First and second offset adding circuits respectively connected to a pair of first and second differential input terminals of a sense amplifier are provided, and further, the first and second offset adding circuits are in a standby state. The first and second offset addition control signals corresponding to the first and second potentials are set to an intermediate potential, and during the test, the first and second offset addition circuits corresponding to the first and second offset addition circuits are set. The offset enable signal is set to a potential at which the first and second field-effect transistors corresponding to the first and second offset adding circuits conduct, and then the first offset adding control signal is set to the intermediate potential. And a control unit for setting the second offset addition control signal from the intermediate potential to the first potential while setting the second potential to the second potential. First and second offset adding circuits respectively connected to a pair of first and second differential input terminals of a sense amplifier are provided, and further, the first and second offset adding circuits are in a standby state. The first and second offset addition control signals corresponding The offset enable signal is set to a potential at which the first to the first and second potentials are set to an intermediate potential, and during the test, the first and second offset addition circuits corresponding to the first and second offset addition circuits are set. And a control unit for setting the second offset addition control signal from the intermediate potential to the second field-effect corresponding to the first and second offset adding circuits conduct, and then the first offset adding control signal is set to the intermediate potential. first potential while setting the second potential to the second potential.

【0037】また、前記オフセット付加手段は、前記第
一の電界効果トランジスタと前記キャパシタとの接続点
と基準電位との間に接続されゲートにオフセット付加手
段待機時電位制御信号が供給された第三の電界効果トラ
ンジスタを、更に有することを特徴とする。そして、前
記オフセット付加手段の待機時において、前記オフセッ
ト付加手段待機時電位制御信号を前記第三の電界効果ト
ランジスタが導通する電位に設定すると共に、前記オフ
セット付加制御信号を第一の電位に設定し、試験時にお
いて前記オフセット付加手段待機時電位制御信号を前記
第三の電界効果トランジスタが非導通となる電位に設定
すると共に、前記オフセット有効化信号を前記第一の電
界効果トランジスタが導通する電位に設定し、続いて前
記オフセット付加制御信号を前記第一の電位とは異なる
第二の電位に設定する制御手段を、更に含むことを特徴
とする。
The offset adding means is connected between a connection point between the first field-effect transistor and the capacitor and a reference potential, and has a gate supplied with the offset adding means standby potential control signal. And a field-effect transistor. Then, during standby of the offset addition unit, the offset addition unit standby potential control signal is set to a potential at which the third field effect transistor conducts, and the offset addition control signal is set to a first potential. In the test, the offset addition means standby potential control signal is set to a potential at which the third field-effect transistor is turned off, and the offset enable signal is set to a potential at which the first field-effect transistor is turned on. The apparatus further comprises control means for setting and subsequently setting the offset addition control signal to a second potential different from the first potential.

【0038】また、前記オフセット付加手段は、一方の
電極に前記ビット線が接続され、他方の電極にオフセッ
ト付加制御信号が供給されたキャパシタからなることを
特徴とする。そして、待機時において前記オフセット付
加制御信号を第一の電位に設定し、試験時において前記
オフセット付加制御信号を第一の電位とは異なる第二の
電位に設定する制御手段を、更に含むことを特徴とす
る。
Further, the offset adding means comprises a capacitor having one bit connected to the bit line and another electrode supplied with an offset adding control signal. And a control unit that sets the offset addition control signal to a first potential during standby, and sets the offset addition control signal to a second potential different from the first potential during a test. Features.

【0039】そして、前記オフセット付加手段として、
センスアンプの一対の第一及び第二の差動入力端子に夫
々接続された第一及び第二のオフセット付加回路が設け
られており、更に、前記待機時において前記第一及び第
二のオフセット付加回路に対応する第一及び第二のオフ
セット付加制御信号を第一及び第二の電位の中間電位に
設定し、試験時において前記第一のオフセット付加制御
信号を前記中間電位から前記第二の電位に設定すると共
に、前記第二のオフセット付加制御信号を前記中間電位
から前記第一の電位に設定する制御手段を含むことを特
徴とする。
And, as the offset adding means,
There are provided first and second offset adding circuits respectively connected to a pair of first and second differential input terminals of the sense amplifier, and further, the first and second offset adding circuits are provided during the standby. The first and second offset addition control signals corresponding to the circuit are set to an intermediate potential between the first and second potentials, and the first offset addition control signal is changed from the intermediate potential to the second potential during a test. And control means for setting the second offset addition control signal from the intermediate potential to the first potential. There are provided first and second offset adding circuits respectively connected to a pair of first and second differential input terminals of the sense amplifier, and further, the first and second offset adding circuits are provided during the standby. The first and second offset addition control signals And control means for setting the second offset addition control signal from the corresponding to the circuit are set to an intermediate potential between the first and second potentials, and the first offset addition control signal is changed from the intermediate potential to the second potential during a test. the intermediate potential to the first potential.

【0040】また、前記メモリセルの試験時においての
み、前記オフセット付加手段を有効化する有効化手段
を、更に含み、前記有効化手段は、少なくとの一つのピ
ンに対して所定電位が印加された場合に、前記試験時で
あるとする判定して前記オフセット付加手段を有効化す
るようにしたことを特徴とし、また前記有効化手段は、
複数のピンに対して所定の組合わせ電位が供給された場合に、前記試験時であるとする判定して前記オフセット付加手段を有効化するようにしたことを特徴とする。 When a predetermined combination potential is supplied to a plurality of pins, it is determined that the test is being performed, and the offset adding means is enabled. 更に、前記有効化手段は、少なくとも一つのピンに対して所定電位の組合わせが時系列で供給された場合に、前記試験時であるとする判定して前記オフセット付加手段を有効化するようにしたことを特徴とする。 Further, when the combination of predetermined potentials is supplied to at least one pin in time series, the activation means determines that it is the time of the test and activates the offset addition means. It is characterized by having done it. [0040] Further, the memory device further includes an enabling means for enabling the offset adding means only at the time of testing the memory cell, wherein the enabling means applies a predetermined potential to at least one pin. In the case, it is characterized in that it is determined that it is the time of the test and the offset adding means is enabled, and the enabling means, [0040] Further, the memory device further includes an enabling means for enabling the offset adding means only at the time of testing the memory cell, wherein the enabling means applies a predetermined potential to at least one pin. In the case, it is characterized. in that it is determined that it is the time of the test and the offset adding means is enabled, and the enabling means,
When a predetermined combination potential is supplied to a plurality of pins, it is determined that the test is being performed, and the offset adding means is enabled. Further, when the combination of the predetermined potentials is supplied in time series to at least one pin, the enabling unit determines that the test is being performed and activates the offset adding unit. It is characterized by having done. When a predetermined combination potential is supplied to a plurality of pins, it is determined that the test is being performed, and the offset adding means is enabled. Further, when the combination of the predetermined potentials is supplied in time series to at least one pin , the enabling unit determines that the test is being performed and activates the offset adding unit. It is characterized by having done.

【0041】 [0041]

【発明の実施の形態】本発明の実施例について図面を用
いて説明する。図1は本発明の一実施例の強誘電体メモ
リ回路を示すブロック図である。なお、今後記す実施例
の回路図においても、簡単のために、強誘電体メモリ回
路のうち、本発明の主旨である「オフセットを付加す
る」という機能の説明に必要な部分のみを抜き出して記
載するものとする。また、これまでに説明した構成要素
と同じものについては、同じ符号を用いることとし、そ
の詳しい説明を省略する。さらに、以下の実施例は全て
強誘電体メモリを用いて説明するが、本発明は強誘電体
メモリに限らず、ダイナミックランダムアクセスメモリ
(DRAM)等、ビット線上にあらわれるデータ電位を
増幅して読出し動作を行う形式をとる全ての半導体メモ
リに対して適用可能である。
Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a ferroelectric memory circuit according to one embodiment of the present invention. In the circuit diagrams of the embodiments described below, for the sake of simplicity, only the portions of the ferroelectric memory circuit necessary for explaining the function of "adding an offset" which is the gist of the present invention are extracted and described. It shall be. The same components as those described above are denoted by the same reference numerals, and detailed description thereof will be omitted. Further, although the following embodiments are all described using ferroelectric memories, the present invention is not limited to ferroelectric memories, and amplifies and reads out data potentials appearing on bit lines, such as dynamic random access memories (DRAMs). The present invention can be applied to all semiconductor memories that take a form of performing an operation.

【0042】図1は、センスアンプSAk 、トランスフ
ァゲートTGk 、ビット線BLNk、BLTk およびビ
ット線に接続されているメモリセルMCからなる強誘電
体メモリ回路に、オフセットを付加するオフセット回路
OFk を接続した例である。オフセット回路は、1本の
ビット線に対して1個のトランジスタT1 (T2 )と1
個のキャパシタCD1 (CD2 )とで構成されている。
このトランジスタは、ゲート端子がオフセット有効化信号OC1 (OC2 )に、ドレイン端子がビット線に、ソース端子がキャパシタの一方の電極に、それぞれ接続されている。 In this transistor, the gate terminal is connected to the offset activation signal OC1 (OC2), the drain terminal is connected to the bit wire, and the source terminal is connected to one electrode of the capacitor. キャパシタの他方の電極は、オフセット付加制御信号OPL1 (OPL2 )に接続されている。 The other electrode of the capacitor is connected to the offset addition control signal OPL1 (OPL2). In FIG. 1, an offset circuit OFk for adding an offset is connected to a ferroelectric memory circuit including a sense amplifier SAk, a transfer gate TGk, bit lines BLNk and BLTk, and a memory cell MC connected to the bit line. It is an example. The offset circuit includes one transistor T1 (T2) and one transistor for one bit line. In FIG. 1, an offset circuit OFk for adding an offset is connected to a enabling memory circuit including a sense amplifier SAk, a transfer gate TGk, bit lines BLNk and BLTk, and a memory cell MC connected to the bit line. It is an example. The offset circuit includes one transistor T1 (T2) and one transistor for one bit line.
Capacitor CD1 (CD2). Capacitor CD1 (CD2).
This transistor has a gate terminal connected to the offset enable signal OC1 (OC2), a drain terminal connected to the bit line, and a source terminal connected to one electrode of the capacitor. The other electrode of the capacitor is connected to the offset addition control signal OPL1 (OPL2). This transistor has a gate terminal connected to the offset enable signal OC1 (OC2), a drain terminal connected to the bit line, and a source terminal connected to one electrode of the capacitor. The other electrode of the capacitor is connected to the offset addition. control signal OPL1 (OPL2).

【0043】これ等オフセット有効化信号OC1 ,OC
2 やオフセット付加制御信号OPL1 ,OPL2 はオフセット回路を制御するためのオフセット回路制御部3から生成されるものであり、このオフセット回路制御部3

は有効化部2からの有効化信号により制御される。 Is controlled by the activation signal from the activation unit 2. そして、当該半導体メモリ装置の外部ピンの一つまたは複数ピンへ外部から供給されるテスト(試験)指令に応答して、有効化部2は有効化信号を生成してオフセット回路制御部3を制御し、上記各制御信号を予め定められたタイミングに従って生成して、メモリセルの試験のためのオフセットをビット線対BLNk ,BLTk へ付加する様になっている。 Then, in response to a test (test) command supplied from the outside to one or a plurality of external pins of the semiconductor memory device, the activation unit 2 generates an activation signal to control the offset circuit control unit 3. Then, each of the above control signals is generated according to a predetermined timing, and an offset for testing the memory cell is added to the bit line pairs BLNk and BLTk. These offset enable signals OC1, OC These offset enable signals OC1, OC
2 and the offset addition control signals OPL1 and OPL2 are generated by the offset circuit control unit 3 for controlling the offset circuit. 2 and the offset addition control signals OPL1 and OPL2 are generated by the offset circuit control unit 3 for controlling the offset circuit.
Is controlled by an enabling signal from the enabling unit 2. Then, in response to a test (test) command externally supplied to one or more external pins of the semiconductor memory device, the validating unit 2 generates a validating signal and controls the offset circuit control unit 3. Then, the control signals are generated in accordance with a predetermined timing, and an offset for testing a memory cell is added to the pair of bit lines BLNk and BLTk. Is controlled by an enabling signal from the enabling unit 2. Then, in response to a test (test) command externally supplied to one or more external pins of the semiconductor memory device, the validating unit 2 generates a validating signal and controls the offset circuit control unit 3. Then, the control signals are generated in accordance with a predetermined timing, and an offset for testing a memory cell is added to the pair of bit lines BLNk and BLTk.

【0044】図1の回路を用いて実際にオフセットを付
加する動作を行うときの各信号のタイミングチャートを
図2に示す。以下、図1の回路で、図2のタイミングチ
ャートにて本発明を実施する場合について説明する。な
お、本発明のオフセットを付加する動作を適用するにあ
たり、強誘電体メモリ本体の動作方式としては、1T/
1C型、2T/2C型のいずれでもよい。 Either 1C type or 2T / 2C type may be used. FIG. 2 is a timing chart of each signal when an operation of actually adding an offset is performed using the circuit of FIG. Hereinafter, the case where the present invention is implemented in the circuit of FIG. 1 with reference to the timing chart of FIG. 2 will be described. In applying the operation of adding an offset according to the present invention, the operation method of the ferroelectric memory body is 1T / FIG. 2 is a timing chart of each signal when an operation of actually adding an offset is performed using the circuit of FIG. Inc., the case where the present invention is implemented in the circuit of FIG. 1 with reference to the timing chart of FIG. FIG. 2 will be described. In applying the operation of adding an offset according to the present invention, the operation method of the implementing memory body is 1T /
Any of 1C type and 2T / 2C type may be used. Any of 1C type and 2T / 2C type may be used.

【0045】図2には、オフセットを付加する動作を行
うタイミングを(A)と記している。1T/1C型動作
の場合は、ワード線、プレート線をそれぞれ選択してビ
ット線(例えば、BLNk )上にメモリセルからのデー
タを読出し、かつ一方で、リファレンス電位発生回路
(図1には示されていない)を用いてビット線と対にな
るビット線(BLTk )上にリファレンス電位を生成し
た後に、ビット線(BLNk もしくはBLTk )上にオ
フセットを付加する。オフセットを付加するには、オフ
セット有効化信号OC1 (もしくはOC2 )をハイレベ
ルとし、オフセット付加制御信号OPL1 (もしくはO
PL2 )をロウレベルからハイレベルに駆動する。 Drive PL2) from low level to high level. FIG. 2A shows the timing at which the operation of adding an offset is performed. In the case of 1T / 1C type operation, a word line and a plate line are each selected to read data from a memory cell on a bit line (for example, BLNk), and, on the other hand, a reference potential generating circuit (shown in FIG. 1). After the reference potential is generated on the bit line (BLTk) paired with the bit line using the bit line (BLNk or BLTk), an offset is added on the bit line (BLNk or BLTk). To add an offset, the offset enable signal OC1 (or OC2) is set to a high level, and the offset addition control signal OPL1 (or O2) is set. FIG. 2A shows the timing at which the operation of adding an offset is performed. In the case of 1T / 1C type operation, a word line and a plate line are each selected to read data from a memory cell on a bit line (for) example, BLNk), and, on the other hand, a reference potential generating circuit (shown in FIG. 1). After the reference potential is generated on the bit line (BLTk) paired with the bit line using the bit line (BLNk or BLTk), an offset is added on the bit line (BLNk or BLTk). To add an offset, the offset enable signal OC1 (or OC2) is set to a high level, and the offset addition control signal OPL1 (or O2) is set.
PL2) is driven from a low level to a high level. PL2) ​​is driven from a low level to a high level.

【0046】こうすることにより、オフセット回路内のキャパシタを介したカップリングによって、ビット線B
LNk (OPL2 を駆動した場合にはBLTk )の電位が高電位側にシフトする。 The potential of LNk (BLTk when OPL2 is driven) shifts to the high potential side. この電位シフトによって、図2に示したように読出し信号電位差が減少する、すなわちオフセットそのものとなる。 As shown in FIG. 2, this potential shift reduces the potential difference of the read signal, that is, the offset itself. こうしてビット線にオフセットを生成した後、センスアンプを活性化して読出しデータの判別動作を行う。 After generating the offset in the bit line in this way, the sense amplifier is activated to perform the operation of discriminating the read data. 最後に、読出しの1サイクル動作が終了する以前にOC1 (OC2 )とOPL1 (O Finally, OC1 (OC2) and OPL1 (O) before the end of one read cycle operation.
PL2 )をロウレベルに戻しておく。 PL2) ​​is returned to the low level. By doing so, coupling via the capacitor in the offset circuit causes the bit line B By doing so, coupling via the capacitor in the offset circuit causes the bit line B
The potential of LNk (BLTk when OPL2 is driven) shifts to the higher potential side. Due to this potential shift, the read signal potential difference decreases as shown in FIG. 2, ie, the offset itself. After the offset is generated in the bit line, the sense amplifier is activated to perform the operation of determining the read data. Finally, OC1 (OC2) and OPL1 (O2) are read before the end of one cycle of read operation. The potential of LNk (BLTk when OPL2 is driven) shifts to the higher potential side. Due to this potential shift, the read signal potential difference decreases as shown in FIG. 2, ie, the offset itself. After the offset is generated in the bit line, the sense amplifier is activated to perform the operation of determining the read data. Finally, OC1 (OC2) and OPL1 (O2) are read before the end of one cycle of read operation.
PL2) is returned to the low level. PL2) ​​is returned to the low level.

【0047】重要な点は、(A)の期間にオフセット有効化信号(OC1 もしくはOC2 )がハイレベルであり、かつ、その期間にオフセット付加制御信号(OPL
1 もしくはOPL2 )がロウレベルからハイレベルに駆動されるということである。 1 or OPL2) is driven from low level to high level. それ以外の本発明に関わる信号の動作タイミングは任意でよい。 Other than that, the operation timing of the signal according to the present invention may be arbitrary. It is important that the offset enable signal (OC1 or OC2) is at the high level during the period (A) and the offset addition control signal (OPL) is It is important that the offset enable signal (OC1 or OC2) is at the high level during the period (A) and the offset addition control signal (OPL) is
1 or OPL2) from the low level to the high level. Other operation timings of the signal according to the present invention may be arbitrary. 1 or OPL2) from the low level to the high level. Other operation timings of the signal according to the present invention may be arbitrary.

【0048】2T/2C型動作の強誘電体メモリに対してオフセットを付加する場合も、上記1T/1C型とほぼ同様である。異なる点は、2T/2C型動作ではリファレンス電位発生回路を用いていない点である。すなわち、メモリセルからビット線対(BLNk ,BLTk )
に差動でデータを出力するので、オフセットを付加するのは、ワード線、プレート線をそれぞれ選択して、ビット線対(BLNk 、BLTk )上にメモリセルからのデータが読出された後ということになる。 Since the data is output differentially to, the offset is added after the word line and plate line are selected respectively and the data from the memory cell is read on the bit line pair (BLNk, BLTk). become. その後の動作は1T/1C型の場合と全く同様である。 Subsequent operations are exactly the same as for the 1T / 1C type. The case where an offset is added to a ferroelectric memory of the 2T / 2C type operation is almost the same as that of the 1T / 1C type. The difference is that the 2T / 2C type operation does not use the reference potential generation circuit. That is, the bit line pair (BLNk, BLTk) is transferred from the memory cell. The case where an offset is added to a communicating memory of the 2T / 2C type operation is almost the same as that of the 1T / 1C type. The difference is that the 2T / 2C type operation does not use the reference potential generation circuit. That is, the bit line pair (BLNk, BLTk) is transferred from the memory cell.
Since the data is output differentially, the offset is added after the data is read from the memory cell on the bit line pair (BLNk, BLTk) by selecting the word line and the plate line, respectively. become. The subsequent operation is exactly the same as in the case of the 1T / 1C type. Since the data is output differentially, the offset is added after the data is read from the memory cell on the bit line pair (BLNk, BLTk) by selecting the word line and the plate line, respectively. Become. The subsequent operation is exactly the same as in the case of the 1T / 1C type.

【0049】以上に説明したように、本発明では、メモ
リセルからビット線上にデータ電位差を読出した後、こ
のデータ電位差を減少させるようにビット線電位を変化
させる動作を行うことにより、オフセットを生成するこ
とが要点である。この動作によれば、メモリセルからビ
ット線への読出し電位差がオフセット以下である場合に
は、センスアンプによるデータ判定動作がフェイルとな
る。すなわち、オフセット以下の読出し電位差を持つメ
モリセルを含む強誘電体メモリが不良となって、信頼性
上問題のあるメモリの選別が可能となる。
As described above, in the present invention, the offset is generated by reading the data potential difference from the memory cell onto the bit line, and then performing the operation of changing the bit line potential so as to reduce the data potential difference. The point is to do it. According to this operation, when the read potential difference from the memory cell to the bit line is equal to or smaller than the offset, the data determination operation by the sense amplifier fails. That is, a ferroelectric memory including a memory cell having a read potential difference equal to or smaller than the offset becomes defective, and a memory having a problem in reliability can be selected.

【0050】本発明の方式を用いた場合のオフセット量
を簡単に見積もってみる。ビット線の寄生容量値をC
B、オフセット回路内のキャパシタの静電容量値をC
D、オフセット付加制御信号OPL1 ,OPL2 のハイ
レベルの電位をVDPとする。ここで、上記の動作方式
により生成されるオフセットΔVoffsetは、OPL1
(またはOPL2 )がロウレベルの状態からハイレベル
の状態へ駆動される前後において、ビット線上の電荷が
保存されるという条件を用いることにより計算でき、そ
の結果は、 ΔVoffset=CD×VDP/(CD+CB)……(1) となる。
The offset amount when the method of the present invention is used will be simply estimated. The parasitic capacitance of the bit line is C
B, the capacitance value of the capacitor in the offset circuit is C B, the capacitance value of the capacitor in the offset circuit is C
D, the high-level potential of the offset addition control signals OPL1 and OPL2 is VDP. Here, the offset ΔVoffset generated by the above operation method is OPL1 D, the high-level potential of the offset addition control signals OPL1 and OPL2 is VDP. Here, the offset ΔVoffset generated by the above operation method is OPL1
(Or OPL2) can be calculated by using the condition that the charge on the bit line is preserved before and after being driven from the low level state to the high level state, and the result is: ΔVoffset = CD × VDP / (CD + CB) (1) (Or OPL2) can be calculated by using the condition that the charge on the bit line is preserved before and after being driven from the low level state to the high level state, and the result is: ΔVoffset = CD × VDP / (CD + CB) (1)

【0051】この(1)式の右辺にある量は、CB,C
D,VDPであり、これらCDやVDPを適当な値にすることで任意のオフセット量を設定することができる。

かつ、これら右辺に含まれる量は全てビット線に読出された電位によらない量である。 Moreover, all the amounts contained in these right-hand sides are amounts that do not depend on the potential read out on the bit line. 従って、本発明の方式によれば、従来のようなビット線読み出し電位に対する依存性はなく、最適なオフセット値を容易に設定できるという利点がある。 Therefore, according to the method of the present invention, there is an advantage that the optimum offset value can be easily set without dependence on the bit line readout potential as in the conventional case. The quantities on the right side of the equation (1) are CB, C The quantities on the right side of the equation (1) are CB, C
D and VDP, and an arbitrary offset amount can be set by setting these CD and VDP to appropriate values. D and VDP, and an arbitrary offset amount can be set by setting these CD and VDP to appropriate values.
In addition, the amounts included in these right sides are all amounts not depending on the potential read to the bit line. Therefore, according to the method of the present invention, there is an advantage that the optimum offset value can be easily set without being dependent on the bit line read potential as in the related art. In addition, the amounts included in these right sides are all amounts not depending on the potential read to the bit line. Therefore, according to the method of the present invention, there is an advantage that the optimum offset value can be easily set without being dependent on the bit line read potential as in the related art.

【0052】図2では、オフセットを付加する(A)の
時期に、オフセット付加制御信号OPL1 もしくはOP
L2 をロウレベルからハイレベルに駆動することによってオフセットを生成していた。 The offset was generated by driving L2 from low level to high level. 逆に、オフセット付加制御信号をハイレベルからロウレベルに駆動することによってもオフセットを生成することができる。 Conversely, the offset can also be generated by driving the offset addition control signal from the high level to the low level. 図1の回路に対して、この方式によってオフセットを付加する例を図3に示した。 An example of adding an offset to the circuit of FIG. 1 by this method is shown in FIG. 図3の場合には、例えばOC2 をハイレベル、OPL2 をハイレベルからロウレベルに駆動したときには、キャパシタを介したカップリングにより、ビット線BLTkに対し電位が低くなる方向に電位シフトが起こる。 In the case of FIG. 3, for example, when OC2 is driven to a high level and OPL2 is driven from a high level to a low level, the potential shift occurs in the direction in which the potential becomes lower with respect to the bit line BLTk due to the coupling via the capacitor. この電位シフトは、図3に示したようにオフセットとなる。 This potential shift is an offset as shown in FIG. In FIG. 2, when the offset is added (A), the offset addition control signal OPL1 or OP In FIG. 2, when the offset is added (A), the offset addition control signal OPL1 or OP
The offset was generated by driving L2 from low level to high level. Conversely, an offset can also be generated by driving the offset addition control signal from a high level to a low level. FIG. 3 shows an example in which an offset is added to the circuit of FIG. 1 by this method. In the case of FIG. 3, for example, when OC2 is driven to a high level and OPL2 is driven from a high level to a low level, a potential shift occurs in a direction in which the potential becomes lower with respect to the bit line BLTk due to coupling via a capacitor. This potential shift becomes an offset as shown in FIG. The offset was generated by driving L2 from low level to high level. Method, an offset can also be generated by driving the offset addition control signal from a high level to a low level. FIG. 3 shows an example in which an offset is added to the circuit of FIG. 1 by this method. In the case of FIG. 3, for example, when OC2 is driven to a high level and OPL2 is driven from a high level to a low level, a potential shift occurs in a direction in which the potential becomes lower with respect to the bit line BLTk due to coupling via a capacitor. This potential shift becomes an offset as shown in FIG.

【0053】図4に、図1の回路を用いてオフセットを
発生する動作方式の第3の例を示す。図4の例では、オ
フセット付加制御信号OPL1 ,OPL2 の待機時の電
位を、電源電位VDPと接地電位GNDとの中間電位
(VDP/2、VDP/3、等々)に設定する。オフセ
ット有効化信号OC1 ,OC2 をともにハイレベルとし
て(A)の期間に入ってから、OPL1 をVDPレベル
へ、OPL2 をGNDレベルへ駆動する。こうすること
により、キャパシタを介したカップリングにより、ビッ
ト線BLNk は高電位側へ、BLTk は低電位側へ、そ
れぞれ電位シフトが起こる。この電位シフトがオフセッ
トとなる。
FIG. 4 shows a third example of an operation method for generating an offset using the circuit of FIG. In the example shown in FIG. 4, the standby potentials of the offset addition control signals OPL1 and OPL2 are set to an intermediate potential (VDP / 2, VDP / 3, etc.) between the power supply potential VDP and the ground potential GND. OPL1 is driven to the VDP level and OPL2 is driven to the GND level after the offset enable signals OC1 and OC2 are both set to the high level and the period (A) is entered. Thus, the potential shift of the bit line BLNk to the high potential side and the potential shift of the BLTk to the low potential side occur due to the coupling via the capacitor. This potential shift becomes an offset.

【0054】図5に、図1とは異なるオフセット回路の
例を示す。本回路は図1に示したオフセット回路内のト
ランジスタとキャパシタとの接続点が、オフセット有効
化信号OC1 ,OC2 がロウレベルのときにフローティ
ングとなることの対策を施した回路である。すなわち、
トランジスタとキャパシタとの接続点を、待機時のオフセット付加制御信号OPL1 ,OPL2 の電位VSと等しくするためのトランジスタTS1 ,TS2 が付加された回路である。 This is a circuit to which transistors TS1 and TS2 are added to make the connection point between the transistor and the capacitor equal to the potential VS of the offset addition control signals OPL1 and OPL2 during standby. TS1 ,TS2 はオフセット回路待機時電位制御信号OC1B,OC2Bがゲート端子に、ドレイン端子にオフセット回路内のトランジスタとキャパシタとの接続点に、ソース端子はVSを供給する配線に接続されている。 In TS1 and TS2, the offset circuit standby potential control signals OC1B and OC2B are connected to the gate terminal, the drain terminal is connected to the connection point between the transistor and the capacitor in the offset circuit, and the source terminal is connected to the wiring that supplies VS. VSの電位は、図2の動作の場合には接地電位、図3の動作の場合はVDP電位、図4の動作の場合にはVDPと接地電位の中間電位である。 The potential of VS is the ground potential in the case of the operation of FIG. 2, the VDP potential in the case of the operation of FIG. 3, and the intermediate potential between VDP and the ground potential in the case of the operation of FIG. FIG. 5 shows an example of an offset circuit different from that of FIG. This circuit is a circuit in which a connection point between a transistor and a capacitor in the offset circuit shown in FIG. 1 is made to be floating when the offset enable signals OC1 and OC2 are at a low level. That is, FIG. 5 shows an example of an offset circuit different from that of FIG. This circuit is a circuit in which a connection point between a transistor and a capacitor in the offset circuit shown in FIG. 1 is made to be floating when the offset enable signals OC1 and OC2 are at a low level. That is,
This circuit is provided with transistors TS1 and TS2 for making the connection point between the transistor and the capacitor equal to the potential VS of the offset addition control signals OPL1 and OPL2 during standby. In TS1 and TS2, the potential control signals OC1B and OC2B at the time of standby of the offset circuit are connected to the gate terminal, the drain terminal is connected to the connection point between the transistor and the capacitor in the offset circuit, and the source terminal is connected to the wiring for supplying VS. The potential of VS is the ground potential in the case of the operation of FIG. 2, the VDP potential in the case of the operation of FIG. 3, and the intermediate potential between VDP and the ground potential in the case of the operation of FIG. This circuit is provided with communicating TS1 and TS2 for making the connection point between the transistor and the capacitor equal to the potential VS of the offset addition control signals OPL1 and OPL2 during standby. In TS1 and TS2, the potential control signals OC1B and OC2B at the time of standby of the offset circuit are connected to the gate terminal, the drain terminal is connected to the connection point between the transistor and the capacitor in the offset circuit, and the source terminal is connected to the wiring for supplying VS. The potential of VS is the ground potential in the case of the operation of FIG. 2, the VDP potential in the case of the operation of FIG. 3, and the intermediate potential between VDP and the ground potential in the case of the operation of FIG.

【0055】尚、図5の回路においても、図1に示した
テスト指令用のピン1、有効化部2およびオフセット回
路制御部3が設けられているが、図では省略して示して
いる。
The circuit of FIG. 5 also includes the test command pin 1, the validating unit 2, and the offset circuit control unit 3 shown in FIG. 1, but is omitted in the figure.

【0056】図5の回路を用いてオフセット付加動作を
行うには、先ず、待機時に導通状態となっているトラン
ジスタTS1 ,TS2 を、オフセット回路待機時電位制
御信号を用いて非導通状態にする。その後は、図2、図
3もしくは図4と全く同様に動作させればよい。最後
に、TS1 ,TS2 を導通状態とする。
In order to perform the offset adding operation using the circuit of FIG. 5, first, the transistors TS1 and TS2 which are in the conductive state during standby are turned off using the potential control signal during standby in the offset circuit. Thereafter, the operation may be performed in exactly the same manner as in FIG. 2, FIG. 3, or FIG. Finally, TS1 and TS2 are turned on.

【0057】図6は、さらに別なるオフセット回路の例
である。本回路は図1に示したオフセット回路内のトラ
ンジスタを削除し、直接ビット線とキャパシタを接続し
た形式の回路である。動作方式についても、図2、図3
もしくは図4からオフセット有効化信号OC1 ,OC2
の動作を除いた動作で、オフセット付加が可能である。
以上のオフセット付加回路は、メモリセルからのデータ読み出し電位差をあえて減少させるものであるため、通常動作時には働かせないことが望ましい。 Since the above offset addition circuit intentionally reduces the data read potential difference from the memory cell, it is desirable not to operate it during normal operation. このため、本発明のオフセット付加回路は、テストモードとして使われることが推奨される。 Therefore, it is recommended that the offset addition circuit of the present invention be used as a test mode. FIG. 6 shows another example of the offset circuit. This circuit is a circuit in which the transistor in the offset circuit shown in FIG. 1 is deleted and the bit line and the capacitor are directly connected. As for the operation method, FIGS. FIG. 6 shows another example of the offset circuit. This circuit is a circuit in which the transistor in the offset circuit shown in FIG. 1 is deleted and the bit line and the capacitor are directly connected. As for the operation method, FIGS.
Alternatively, as shown in FIG. 4, the offset enable signals OC1 and OC2 Alternatively, as shown in FIG. 4, the offset enable signals OC1 and OC2
With the exception of the above operation, offset addition is possible. With the exception of the above operation, offset addition is possible.
Since the above offset adding circuit intentionally reduces the data read potential difference from the memory cell, it is desirable that the offset adding circuit does not operate during normal operation. For this reason, it is recommended that the offset adding circuit of the present invention be used as a test mode. Since the above offset adding circuit intentionally reduces the data read potential difference from the memory cell, it is desirable that the offset adding circuit does not operate during normal operation. For this reason, it is recommended that the offset adding circuit of the present invention be used as a test mode.

【0058】強誘電体メモリの通常動作とテストモード
動作とを区別する手段としては、例えば、(1)強誘電
体メモリに、テスト用の付加ピンを設ける、(2)強誘
電体メモリがすでに持っている1つまたは複数のピン
(たとえばアドレスピン、データピン、制御信号ピン
等)に、ある組み合わせの信号が入力されたとき、また
はあるシーケンスの信号列が入力されたときに、テスト
モードに入る、(3)強誘電体メモリが持つあるピン
に、推奨動作電圧以上の高電圧をかける、等という方法
がある。
As means for distinguishing between the normal operation of the ferroelectric memory and the test mode operation, for example, (1) an additional pin for test is provided in the ferroelectric memory, and (2) the ferroelectric memory has already been used. When a certain combination of signals is input to one or a plurality of pins (for example, an address pin, a data pin, a control signal pin, etc.) or a signal sequence of a certain sequence is input, the test mode is set. And (3) applying a high voltage higher than the recommended operating voltage to a certain pin of the ferroelectric memory.

【0059】上記の(1)〜(3)における各ピンが図
1に示したテスト指令用のピン1であり、このピン1に
上述した(1)〜(3)の信号や電圧が供給された時
に、有効化部2がこれを検出してテストモードであると
判断し、オフセット回路制御部3を動作せしめるのであ
る。このオフセット回路制御部3は図2、図3もしくは
図4のタイミングチャートに従って信号OPL1 ,OP
L2 ,OC1 ,OC2 ,OC1B,OC2Bを制御するのである。 It controls L2, OC1, OC2, OC1B, and OC2B. Each of the pins (1) to (3) is the test command pin 1 shown in FIG. 1, and the signals and voltages (1) to (3) described above are supplied to this pin 1. At this time, the validating unit 2 detects this, determines that the test mode is set, and causes the offset circuit control unit 3 to operate. This offset circuit control unit 3 outputs signals OPL1 and OPL according to the timing charts of FIG. 2, FIG. 3 or FIG. Each of the pins (1) to (3) is the test command pin 1 shown in FIG. 1, and the signals and voltages (1) to (3) described above are supplied to this pin 1. At this time, the validating unit 2 detects this, determines that the test mode is set, and causes the offset circuit control unit 3 to operate. This offset circuit control unit 3 outputs signals OPL1 and OPL according to the timing charts of FIG. 2, FIG. 3 or FIG. ..
L2, OC1, OC2, OC1B, and OC2B are controlled. L2, OC1, OC2, OC1B, and OC2B are controlled.

【0060】従来のオフセットセンスアンプ試験方式に
よって得られるオフセット量のビット線読出し電位に対
する依存性は、図11に示した通りであるが、本発明の
効果を示すため、同図上に、本発明を用いた場合のオフ
セット量を回路シミュレーションにより求めてプロット
したグラフを、図7に示す。図7では、ビット線寄生容
量CB=250fF、オフセット回路内部のキャパシタ
の静電容量値CD=25fF、電源電位VDP=5Vと
仮定した。従来方式によるオフセット量が実線で、本発
明によるオフセット量を点線で示した。この図7から、
本発明では、ビット線読出し電位に対する依存性の小さいオフセット値が得られることがわかる。 In the present invention, it can be seen that an offset value having a small dependence on the bit line reading potential can be obtained. このことにより、本発明を用いると、強誘電体メモリの信頼性に即した最適なオフセット値を容易に設定できることがわかる。 From this, it can be seen that the optimum offset value according to the reliability of the ferroelectric memory can be easily set by using the present invention. The dependence of the offset amount obtained by the conventional offset sense amplifier test method on the bit line read potential is as shown in FIG. 11, but the effect of the present invention is shown in FIG. FIG. 7 shows a graph obtained by plotting the offset amount obtained by using circuit simulation in the case of using. In FIG. 7, it is assumed that the bit line parasitic capacitance CB is 250 fF, the capacitance value CD of the capacitor inside the offset circuit is 25 fF, and the power supply potential VDP is 5 V. The offset amount according to the conventional method is indicated by a solid line, and the offset amount according to the present invention is indicated by a dotted line. From FIG. 7, The dependence of the offset amount obtained by the conventional offset sense amplifier test method on the bit line read potential is as shown in FIG. 11, but the effect of the present invention is shown in FIG. FIG. 7 shows a graph obtained by plotting The offset amount obtained by using circuit simulation in the case of using. In FIG. 7, it is assumed that the bit line parasitic capacitance CB is 250 fF, the capacitance value CD of the capacitor inside the offset circuit is 25 fF, and the power supply potential VDP is 5 V. The offset amount according to the conventional method is indicated by a solid line, and the offset amount according to the present invention is indicated by a dotted line. From FIG. 7,
It can be seen that in the present invention, an offset value having a small dependence on the bit line read potential can be obtained. This indicates that the use of the present invention makes it possible to easily set an optimum offset value in accordance with the reliability of the ferroelectric memory. It can be seen that in the present invention, an offset value having a small dependence on the bit line read potential can be obtained. This indicates that the use of the present invention makes it possible to easily set an optimum offset value in accordance with the reliability of the invention memory.

【0061】以上、本発明の種々の実施例を説明してきたが、これまで各個に述べてきた実施例を、各々組み合わせて本発明を実施することももちろん可能である。 While the various embodiments of the present invention have been described above, it is of course possible to implement the present invention by combining the embodiments described above.

【0062】 [0062]

【発明の効果】以上述べた様に、本発明によれば、ビッ
ト線読出し電位に対する依存性の小さいオフセット値が
簡単に得られるので、メモリセルの試験において、オフ
セットが効きすぎて、本来は信頼性上問題のないレベル
にある強誘電体メモリまで不良と選別されたり、逆にオ
フセットが効かず、信頼性上問題ある強誘電体メモリが
選別されなかったりするという問題を有効に解決可能と
なるという効果がある。
As described above, according to the present invention, an offset value having a small dependence on the bit line read potential can be easily obtained. It is possible to effectively solve the problem that a ferroelectric memory at a level that does not have a problem in reliability is selected as a defect, or conversely, an offset does not work and a ferroelectric memory with a problem in reliability is not selected. This has the effect.

【図面の簡単な説明】 [Brief description of the drawings]

【図1】本発明の実施例であるオフセット付加回路を搭載した強誘電体メモリ装置の第1の例を示す図である。 FIG. 1 is a diagram showing a first example of a ferroelectric memory device equipped with an offset adding circuit according to an embodiment of the present invention.

【図2】図1の回路を用いてオフセット付加を行う動作方式のタイミングチャートの第1の例を示す図である。 FIG. 2 is a diagram showing a first example of a timing chart of an operation method for performing offset addition using the circuit of FIG. 1;

【図3】図1の回路を用いてオフセット付加を行う動作方式のタイミングチャートの第2の例を示す図である。 FIG. 3 is a diagram showing a second example of a timing chart of an operation method of performing offset addition using the circuit of FIG. 1;

【図4】図1の回路を用いてオフセット付加を行う動作方式のタイミングチャートの第3の例を示す図である。 FIG. 4 is a diagram showing a third example of a timing chart of an operation method for performing offset addition using the circuit of FIG. 1;

【図5】本発明の実施例であるオフセット付加回路を搭載した強誘電体メモリ装置の第2の例を示す図である。 FIG. 5 is a diagram showing a second example of a ferroelectric memory device equipped with an offset adding circuit according to an embodiment of the present invention.

【図6】本発明の実施例であるオフセット付加回路を搭載した強誘電体メモリ装置の第3の例を示す図である。 FIG. 6 is a diagram showing a third example of a ferroelectric memory device equipped with an offset adding circuit according to an embodiment of the present invention.

【図7】本発明の方式により発生したオフセット量と従来方式により発生したオフセット量とを比較したグラフである。 FIG. 7 is a graph comparing the offset amount generated by the method of the present invention with the offset amount generated by the conventional method.

【図8】強誘電体メモリ回路全体構成の例を示す図である。 FIG. 8 is a diagram illustrating an example of the entire configuration of a ferroelectric memory circuit.

【図9】図8の回路の動作タイミングチャートである。 FIG. 9 is an operation timing chart of the circuit in FIG. 8;

【図10】従来のオフセット回路例を示す図である。 FIG. 10 is a diagram showing an example of a conventional offset circuit.

【図11】図10の回路により発生されるオフセット量を示すグラフである。 FIG. 11 is a graph showing an offset amount generated by the circuit of FIG. 10;

【符号の説明】 [Explanation of symbols]

1 テスト指令用ピン 2 有効化部 3 オフセット回路制御部 WLj ワード線 PLj プレート線 BLNk ,BLTk ビット線 YSWk Y選択信号 PBL ビット線プリチャージ信号 SAE センスアンプ活性化信号 SAN,SAP センスアンプ活性化信号 TG トランスファゲート信号 DWLN,DWLT ダミーワード線 ION,IOT I/Oバス Ai アドレス信号 XPa Xアドレスプリデコード信号 YPb Yアドレスプリデコード信号 OC1 ,OC2 オフセット有効化信号 OPL1 ,OPL2 オフセット付加制御信号 OC1B,OC2B オフセット回路待機時電位制御信号 VS オフセット回路待機時電位 MCA FeRAMセルアレイ MCjk FeRAMセル DCNk ,DCTk ダミーメモリセル PBLk ビット線プリチャージ回路 SAk センスアンプ回路 TGk トランスファゲート回路 YSTk Y選択トランスファゲート XDEC Xデコーダ PLDEC プレートデコーダ YDEC Yデコーダ DWLDEC ダミーメモリセル制御回路 PBLC ビット線プリチャージ制御回路 SADRV センスアンプ制御回路 ADPDEC アドレスプリデコーダ OFk オフセット回路 T1 ,T2 ,TR1 ,TR2 ,TR3 ,TR4 オフセ
ット回路を構成するトランジスタ TR5 ,TR6 ,TR7 ,TR8 センスアンプ回路を
構成するトランジスタ TS1 ,TS2 オフセット回路内節点の待機時電位を
補償するトランジスタ CB ビット線寄生容量値 CD1 ,CD2 オフセット回路内キャパシタの静電容
量値
DESCRIPTION OF SYMBOLS 1 Test command pin 2 Validation part 3 Offset circuit control part WLj Word line PLj Plate line BLNk, BLTk Bit line YSWk Y selection signal PBL Bit line precharge signal SAE Sense amplifier activation signal SAN, SAP Sense amplifier activation signal TG Transfer gate signal DWLN, DWLT Dummy word line ION, IOT I / O bus Ai Address signal XPa X address predecode signal YPb Y address predecode signal OC1, OC2 offset enable signal OPL1, OPL2 offset additional control signal OC1B, OC2B offset circuit Standby potential control signal VS Offset circuit Standby potential MCA FeRAM cell array MCjk FeRAM cell DCNk, DCTk Dummy memory cell PBLk Bit line precharge circuit SAk Sense Transfer circuit TGk transfer gate circuit YSTk Y selection transfer gate XDEC X decoder PLDEC plate decoder YDEC Y decoder DWLDEC dummy memory cell control circuit PBLC bit line precharge control circuit SADRV sense amplifier control circuit ADPDEC address predecoder OFk offset circuit T1, T2, TR1 , TR2, TR3, TR4 Transistors constituting an offset circuit TR5, TR6, TR7, TR8 Transistors constituting a sense amplifier circuit TS1, TS2 Transistors for compensating a standby potential at a node in the offset circuit CB Bit line parasitic capacitance values CD1, CD2 Capacitance value of capacitor in offset circuit

Claims (13)

    【特許請求の範囲】 [Claims]
  1. 【請求項1】 データを記憶する複数のメモリセルをマトリックス状に配列したメモリセルアレイと、アドレスに従って前記メモリセルアレイ内のメモリセルを選択するためのワード線と、この選択されたメモリセルに対してデータの書込み及び読出しをなすためのビット線と、
    この選択されたメモリセルから前記ビット線上に読出されたデータ信号の電位差を増幅するセンスアンプ回路とを含む半導体メモリ装置であって、前記ビット線上に読出されたデータ信号の電位差を減少させる電圧であって、かつ前記ビット線上に読出される信号電圧に依存しないオフセット電圧を前記ビット線に付加するオフセット付加手段を含むことを特徴とする半導体メモリ装置。 A semiconductor memory device including a sense amplifier circuit that amplifies the potential difference of the data signal read on the bit line from the selected memory cell, and at a voltage that reduces the potential difference of the data signal read on the bit line. A semiconductor memory device including an offset adding means for applying an offset voltage independent of a signal voltage read on the bit line to the bit line. A memory cell array in which a plurality of memory cells for storing data are arranged in a matrix; a word line for selecting a memory cell in the memory cell array according to an address; A bit line for writing and reading data, A memory cell array in which a plurality of memory cells for storing data are arranged in a matrix; a word line for selecting a memory cell in the memory cell array according to an address; A bit line for writing and reading data,
    A sense amplifier circuit for amplifying a potential difference of a data signal read on the bit line from the selected memory cell, wherein the potential difference of the data signal read on the bit line is reduced by a voltage. A semiconductor memory device, comprising: offset adding means for adding to the bit line an offset voltage independent of a signal voltage read on the bit line. A sense amplifier circuit for enhancing a potential difference of a data signal read on the bit line from the selected memory cell, wherein the potential difference of the data signal read on the bit line is reduced by a voltage. A semiconductor memory device, comprising: offset adding means for adding to the bit line an offset voltage independent of a signal voltage read on the bit line.
  2. 【請求項2】 前記オフセット付加手段は、ゲートにオ
    フセット有効化信号が供給され、ソースに前記ビット線
    が接続された第一の電界効果トランジスタと、一方の電
    極に前記トランジスタのドレイン端子が接続され他方の
    電極にオフセット付加制御信号が供給されたキャパシタ
    とを有することを特徴とする請求項1記載の半導体メモ
    リ装置。
    2. The offset adding means includes a first field-effect transistor having a gate supplied with an offset enabling signal, a source connected to the bit line, and a drain terminal connected to one electrode. 2. The semiconductor memory device according to claim 1, further comprising a capacitor to which an offset addition control signal is supplied to the other electrode.
  3. 【請求項3】 待機時において前記オフセット付加制御
    信号を第一の電位に設定し、試験時において前記オフセ
    ット有効化信号を前記第一の電界効果トランジスタが導
    通する電位に設定し、続いて前記オフセット付加制御信
    号を前記第一の電位とは異なる第二の電位に設定する制
    御手段を、更に含むことを特徴とする請求項2記載の半
    導体メモリ装置。
    3. The apparatus according to claim 1, wherein the offset addition control signal is set to a first potential during a standby state, and the offset enable signal is set to a potential at which the first field-effect transistor conducts during a test. 3. The semiconductor memory device according to claim 2, further comprising control means for setting the additional control signal to a second potential different from said first potential.
  4. 【請求項4】 前記オフセット付加手段として、センス
    アンプの一対の第一及び第二の差動入力端子に夫々接続
    された第一及び第二のオフセット付加回路が設けられて
    おり、更に、待機時において前記第一及び第二のオフセ
    ット付加回路に対応する第一及び第二のオフセット付加
    制御信号を第一及び第二の電位の中間電位に設定し、試
    験時において前記第一及び第二のオフセット付加回路に
    対応する第一及び第二のオフセット有効化信号を、前記
    第一及び第二のオフセット付加回路に対応する第一及び
    第二の電界効果トランジスタが導通する電位に設定し、
    続いて前記第一のオフセット付加制御信号を前記中間電位から前記第二の電位に設定すると共に、前記第二のオフセット付加制御信号を前記中間電位から前記第一の電位に設定する制御手段を含むことを特徴とする請求項2 Subsequently, the control means for setting the first offset addition control signal from the intermediate potential to the second potential and setting the second offset addition control signal from the intermediate potential to the first potential is included. 2.
    記載の半導体メモリ装置。 The semiconductor memory device described. 4. A first and a second offset adding circuit connected to a pair of first and second differential input terminals of a sense amplifier, respectively, as said offset adding means, and further comprising: Setting the first and second offset addition control signals corresponding to the first and second offset addition circuits to an intermediate potential between the first and second potentials; The first and second offset enabling signals corresponding to the additional circuit, the first and second field effect transistors corresponding to the first and second offset additional circuit is set to a potential to conduct, 4. A first and a second offset adding circuit connected to a pair of first and second differential input terminals of a sense amplifier, respectively, as said offset adding means, and further comprising: Setting the first and second offset addition control signals corresponding to the first and second offset addition circuits to an intermediate potential between the first and second potentials; The first and second offset enabling signals corresponding to the additional circuit, the first and second field effect transistors corresponding to the first and second offset additional circuits is set to a potential to conduct,
    A control unit that sets the first offset addition control signal from the intermediate potential to the second potential and sets the second offset addition control signal from the intermediate potential to the first potential. 3. The method according to claim 2, wherein A control unit that sets the first offset addition control signal from the intermediate potential to the second potential and sets the second offset addition control signal from the intermediate potential to the first potential. 3. The method according to claim 2, wherein
    The semiconductor memory device according to claim 1. The semiconductor memory device according to claim 1.
  5. 【請求項5】 前記オフセット付加手段は、前記第一の
    電界効果トランジスタと前記キャパシタとの接続点と基
    準電位との間に接続されゲートにオフセット付加手段待
    機時電位制御信号が供給された第三の電界効果トランジ
    スタを、更に有することを特徴とする請求項2記載の半
    導体メモリ装置。
    5. The offset adding means is connected between a connection point between the first field-effect transistor and the capacitor and a reference potential, and a gate to which the offset adding means standby potential control signal is supplied. 3. The semiconductor memory device according to claim 2, further comprising: the field effect transistor.
  6. 【請求項6】 待機時において、前記オフセット付加手
    段待機時電位制御信号を前記第三の電界効果トランジス
    タが導通する電位に設定すると共に、前記オフセット付
    加制御信号を第一の電位に設定し、試験時において前記
    オフセット付加手段待機時電位制御信号を前記第三の電
    界効果トランジスタが非導通となる電位に設定すると共
    に、前記オフセット有効化信号を前記第一の電界効果ト
    ランジスタが導通する電位に設定し、続いて前記オフセ
    ット付加制御信号を前記第一の電位とは異なる第二の電
    位に設定する制御手段を、更に含むことを特徴とする請
    求項5記載の半導体メモリ装置。
    6. In a standby mode, the offset addition means standby potential control signal is set to a potential at which the third field-effect transistor conducts, and the offset addition control signal is set to a first potential. At the time, the offset adding means standby potential control signal is set to a potential at which the third field effect transistor is turned off, and the offset enabling signal is set to a potential at which the first field effect transistor is turned on. 6. The semiconductor memory device according to claim 5, further comprising control means for setting said offset addition control signal to a second potential different from said first potential.
  7. 【請求項7】 前記オフセット付加手段は、一方の電極
    に前記ビット線が接続され、他方の電極にオフセット付
    加制御信号が供給されたキャパシタからなることを特徴
    とする請求項1記載の半導体メモリ装置。
    7. The semiconductor memory device according to claim 1, wherein said offset adding means comprises a capacitor having one bit connected to said bit line and another electrode supplied with an offset adding control signal. .
  8. 【請求項8】 待機時において前記オフセット付加制御
    信号を第一の電位に設定し、試験時において前記オフセ
    ット付加制御信号を第一の電位とは異なる第二の電位に
    設定する制御手段を、更に含むことを特徴とする請求項
    7記載の半導体メモリ装置。
    8. A control means for setting the offset addition control signal to a first potential during standby and setting the offset addition control signal to a second potential different from the first potential during a test. The semiconductor memory device according to claim 7, wherein the semiconductor memory device includes:
  9. 【請求項9】 前記オフセット付加手段として、センス
    アンプの一対の第一及び第二の差動入力端子に夫々接続
    された第一及び第二のオフセット付加回路が設けられて
    おり、更に、前記待機時において前記第一及び第二のオ
    フセット付加回路に対応する第一及び第二のオフセット
    付加制御信号を前記第一及び第二の電位の中間電位に設
    定し、試験時において前記第一のオフセット付加制御信
    号を前記中間電位から前記第二の電位に設定すると共
    に、前記第二のオフセット付加制御信号を前記中間電位
    から前記第一の電位に設定する制御手段を含むことを特
    徴とする請求項7記載の半導体メモリ装置。
    9. The offset adding means includes first and second offset adding circuits connected to a pair of first and second differential input terminals of a sense amplifier, respectively. At the time, the first and second offset addition control signals corresponding to the first and second offset addition circuits are set to an intermediate potential between the first and second potentials, and during the test, the first offset addition control signal is set. 8. A control device for setting a control signal from the intermediate potential to the second potential and for setting the second offset addition control signal from the intermediate potential to the first potential. The semiconductor memory device according to claim 1.
  10. 【請求項10】 前記メモリセルの試験時においての
    み、前記オフセット付加手段を有効化する有効化手段
    を、更に含むことを特徴とする請求項1〜9記載の半導
    体メモリ装置。
    10. The semiconductor memory device according to claim 1, further comprising an enabling unit for enabling said offset adding unit only when testing said memory cell.
  11. 【請求項11】 前記有効化手段は、少なくとの一つの
    ピンに対して所定電位が印加された場合に、前記試験時
    であるとする判定して前記オフセット付加手段を有効化
    するようにしたことを特徴とする請求項10記載の半導
    体メモリ装置。
    11. The validating means, when a predetermined potential is applied to at least one pin, determines that it is the time of the test, and activates the offset adding means. 11. The semiconductor memory device according to claim 10, wherein:
  12. 【請求項12】 前記有効化手段は、複数のピンに対し
    て所定の組合わせ電位が供給された場合に、前記試験時
    であるとする判定して前記オフセット付加手段を有効化
    するようにしたことを特徴とする請求項10記載の半導
    体メモリ装置。
    12. The validation unit, when a predetermined combination potential is supplied to a plurality of pins, determines that the test is being performed, and activates the offset addition unit. 11. The semiconductor memory device according to claim 10, wherein:
  13. 【請求項13】 前記有効化手段は、少なくとも一つの
    ピンに対して所定電位の組合わせが時系列で供給された
    場合に、前記試験時であるとする判定して前記オフセッ
    ト付加手段を有効化するようにしたことを特徴とする請
    求項10記載の半導体メモリ装置。
    13. When the combination of predetermined potentials is supplied in time series to at least one pin, the validating means determines that the test is being performed and activates the offset adding means. 11. The semiconductor memory device according to claim 10, wherein the operation is performed.
JP25968299A 1999-09-14 1999-09-14 Semiconductor memory device Expired - Fee Related JP3551858B2 (en)

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KR1020000053655A KR100349955B1 (en) 1999-09-14 2000-09-09 Semiconductor memory device capable of generating offset voltage independent of bit line voltage
US09/662,144 US6288950B1 (en) 1999-09-14 2000-09-14 Semiconductor memory device capable of generating offset voltage independent of bit line voltage
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