JPH08180671A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To prevent the destruction of stored data due to the erroneous inversion of the polarity of a capacitor in the nonselecting state of a DRAM type nonvolatile memory cell having a ferroelectric capacitor. CONSTITUTION: This memory is provided with a capacitor C11 inserting a ferroelectric film between a first and a second electrodes, an N type transistor T11 and a P channel transistor T12 connected to the second electrode of the capacitor in parallel. A cell plate line CP is connected to the first electrode, a bit line BL is connected to the second electrode through two transistors T11, T12 and word lines ML are connected to the gates of the respective transistors T11, T12. A node between the second electrode and the respective transistors T11, T12 and a grounded power source are connected through a transistor T13, at the time of non-selection, the transistors T11, T12 are turned OFF and the transistor T13 is turned ON. Consequently, the potential on the second electrode of the capacitor C11 is fixed and erroneous inversion is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a capacitor having a ferroelectric film is arranged in a memory cell, and more particularly, a measure for preventing destruction of stored data in a non-selected state of the memory cell. Regarding

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device, a device of a type in which charges are stored in a capacitor formed inside and data is stored depending on the presence or absence of the charges is mainly used. Such a semiconductor memory device is generally called a dynamic type memory (hereinafter referred to as DRAM), and a silicon oxide film has been used as an insulating film of its capacitor. In recent years, a semiconductor memory device has been known in which a ferroelectric film made of a ferroelectric material is used as an insulating film of a capacitor to make data storage non-volatile.

FIG. 10 is a diagram showing the relationship between the voltage applied to the ferroelectric substance and the self-polarization of the ferroelectric substance. As shown in the figure, the transition of the polarization state of the ferroelectric shows a so-called hysteresis characteristic, and even when the voltage applied to the ferroelectric becomes zero (state of point S2 in the figure), The residual polarization Pr remains. If the capacitor part of a semiconductor memory device is made up of a film made of such a ferroelectric material, it becomes possible to retain data in the capacitor even after the voltage is no longer applied, realizing a non-volatile storage of data. can do.

A conventional semiconductor memory device having a capacitor having a ferroelectric film will be described below with reference to the drawings.

FIG. 9 is an electric circuit diagram showing the structure of the conventional semiconductor memory device 1. In the figure, a semiconductor memory device 1 includes a memory cell 2 for storing 1-bit data,
3, the dummy cells 4 and 5, the sense amplifier 6, and the memory cells 2 and 3, and the bit lines BLB1 and BLB2 for writing and reading the data from the memory cells 2 and 3, and the memory cells 2 and 3, respectively. Are provided with word lines WLB1 and WLB2 for selecting the respective, the cell plate line CPB, and the dummy word lines DWL1 and DWL2.

The memory cells 2 and 3 each have a ferroelectric film 2
Memory cell capacitors C1 and C sandwiched by two electrodes
2 and pass transistors T1 and T2, each of which is a field effect MOS transistor. Similarly,
The dummy cells 4 and 5 have dummy cell capacitors C3 and C4 each having a ferroelectric film sandwiched between two electrodes, and pass transistors T3 and T4. The memory cell capacitors C1 and C2 and the dummy cell capacitor C
One of the electrodes C3 and C4 is connected to the common cell plate line CPB. When the transistors T1 and T2 are on, that is, when the memory cells 2 and 3 to be arranged are selected, the memory cell capacitors C1 and C2 and the bit lines BLB1 and BLB2 become conductive, and the transistors T3 and T4. Is on, dummy cell capacitors C3 and C4 and bit line B
A conduction state is established between LB2 and BLB1.

Next, the write operation of the semiconductor memory device 1 as described above will be described. For example, when writing data “1” to the memory cell 2, first, the bit line BLB1
By applying a high level potential to the word line and the word line WLVI and a low level potential to the cell plate line CPB, a positive voltage is applied to the memory cell capacitor C1,
The polarization state of the memory cell capacitor C1 is point S1 in FIG.
It becomes the state of. Next, the potential applied to the cell plate CPB transitions to a high level, the voltage applied to the memory cell capacitor C1 becomes zero, and the polarization state of the memory cell capacitor C1 transitions to the state at point S2 in FIG. Next, the cell plate line CPB, the word line WLB1,
Even if the potential applied to the bit line BLB1 is returned to the low level, the polarization state of the memory cell capacitor C1 is as shown in FIG.
Remains at the point S2. In this way, the data "1" is written in the memory cell 2, and the polarization state of the memory cell capacitor C1 of the memory cell 2 is maintained without change even if the application of voltage is stopped.

On the other hand, when writing data "0" to the memory cell 2, first, a low-level potential is applied to the bit line BLB1, a high-level potential is applied to the word line WLB1, and further the cell plate line CPB. A low level potential is applied to. Next, by shifting the potential applied to the cell plate line CPB to a high level, a negative voltage is applied to the memory cell capacitor C1, and the polarization state of the memory cell capacitor C1 becomes the state of point S3 in FIG. . next,
If the potential applied to the cell plate line CPB and the word line WLB1 in this order returns to the low level, the memory cell capacitor C
The polarization state of 1 becomes the state of point S4 in FIG. 10, and the data “0” is written in the memory cell 2. The polarization state of the memory cell capacitor C1 is maintained without change even when the voltage application is stopped, as in the case where the data “1” is written.

Next, the read operation of the semiconductor memory device 1 will be described by taking the case of reading the stored data in the memory cell 2 as an example. First, a low-level potential is applied to the bit lines BLB1 and BLB2 prior to the read operation. Then, by applying a high-level potential to the word line WLB1, the transistor T1 is turned on, and the bit line BLB1 and the memory cell capacitor C1 are brought into conduction. At this time, the voltage applied to the memory cell capacitor C1 is zero, and the polarization state of the memory cell capacitor C1 is held at the preset state of point S2 or S4 in FIG.

Next, by changing the potential applied to the cell plate line CPB to a high level, a negative voltage is applied to the memory cell capacitor C1, and the polarization state of the memory cell capacitor C1 is point S2 in FIG. Alternatively, the state of S4 transits to the state of point S3. At this time, the bit line BL
The potential of B1 differs depending on the data previously written in the memory cell 2. When the data “1” is written in the memory cell 2, the polarization state of the memory cell capacitor C1 transits from the state of point S2 to the state of point S3 in FIG. 10, and the charge released from the memory cell capacitor C1. The amount is relatively large, and the potential of the bit line BLB1 becomes a high read potential L1 as shown in FIG. On the other hand, when the data “0” is written in the memory cell 2, the polarization state of the memory cell capacitor C1 transits from the state of point S4 to the state of point S3 in FIG. 10 and is discharged from the memory cell capacitor C1. The amount of electric charge is smaller than that in the case where the data “1” is written, and the potential of the bit line BLB1 becomes a low read potential L2 as shown in FIG. Then, the sense amplifier 6 causes the read potential L1 or L2 to be read.
Is received and it is determined whether the stored data is "1" or "0" depending on which of these potentials. L3 is an intermediate potential between the high potential L1 and the low potential L2.

In the above conventional example, one transistor and one transistor are used.
An example has been described in which one DRAM type ferroelectric non-volatile memory cell is formed by using one ferroelectric capacitor (hereinafter referred to as a 1T1C type memory cell).

Next, an example in which one memory cell is formed by two transistors and two ferroelectric capacitors will be described with reference to FIG. 10 (US Pat. No. 4,873, US Pat. No. 4,873). 664 specification). After that,
This memory cell is called a 2T2C type memory cell. FIG.
As shown in FIG. 2, the 2T2C type memory cell includes a memory cell 10 for storing 1-bit data and a sense amplifier 1
1, bit lines BL and XBL for writing and reading data in the memory cell 10, a word line WL for selecting the memory cell 10, and a cell plate line CP are arranged. Further, the memory cell 10 has a ferroelectric film 2
Capacitors 16 and 17 sandwiched between two electrodes and transistors 18 and 19 are provided. The operation of the word line WL and the cell plate line CP at the time of writing / reading data to / from the memory cell is the same as that of the 1T1C type memory cell of the above-mentioned conventional example, but it has two bit lines BL and XBL. The difference is that complementary data of high level and low level is written in one memory cell. For example, when writing "1" data to the memory cell 10, a high level is applied to the bit line BL and a low level is applied to the complementary bit line XBL, and then the word line WL and the cell plate line CP are set to the selected state. To do. At this time, the ferroelectric capacitors 16 and 17 are connected to the points S2 and S4 of FIG. 10, respectively.
Is set to the state of. This state is maintained even when the voltage application is stopped, as in the case of the 1T1C type memory cell. In order to read, 1T1 described above from this state
Select the word line BL as in the case of the C-type memory cell,
By setting the cell plate line CP to a high potential, the L1 level shown in FIG. 11 is output to the bit line BL and the L2 level is output to the complementary bit line XBL. Sense amplifier 11
Detects the level difference and reads the data.

In the above-described write / read operation, the polarization of the ferroelectric capacitor is reversed by applying a high potential pulse to the cell plate line after setting the bit line potential to a low potential. Similarly, it is also possible to set the bit line potential to a high potential and then apply a low potential pulse to the cell plate line to invert the polarization of the ferroelectric capacitor and write / read data.

In the circuits shown in FIGS. 9 and 12 of the above-mentioned conventional example, the pass transistor connecting the ferroelectric capacitor and the bit line is an N-channel type transistor as shown in FIG. 13A. There is. However, in FIG.
It is also possible to use a P-channel type transistor as shown in (b). Further, for the purpose of low voltage operation, as shown in FIG. 13C, a pass transistor can be formed by a CMOS transistor.

FIG. 15 is a timing chart showing an operation example of each signal when the memory cell configuration of FIG. 13 (c) is used. Here, XCE activates the memory cell
This is a memory cell selection signal for deactivating and is input from outside the memory cell. In this example, when the memory cell selection signal XCE is at the low potential level, the memory cells are selectively activated, and when the memory cell selection signal XCE is at the high potential level, the memory cells are deselected and deactivated, and the standby state is set. In this example, each signal line enters the standby state with the read or write operation completed. That is, in the standby state, the word line WL is in the low potential state,
Complementary word line XWL is in a high potential state, cell plate line CP
Is in a low potential state. The bit line pair BL, XBL is precharged to the ground potential.

[0016]

By the way, FIG.
In the DRAM memory cell including the ferroelectric capacitor C1 and the pass transistor T1 as shown in (a) to (c), when the memory cell is not selected and the pass transistor T1 is OFF, the pass transistor T1 The node NdA that connects the ferroelectric capacitor C1 to the ferroelectric capacitor C1 is in a floating state. Such a state occurs in an unselected memory cell during a normal write operation or read operation. It also occurs in a standby state (that is, a non-selected state) in which the memory cell is not in the active state.

The problem occurring at the node NdA at this time will be described below with reference to FIGS. 14 (a) to 14 (c). FIGS. 14A to 14C are the same as FIGS.
It is a figure which shows roughly the vertical cross-section structure of the transistor part corresponding to the circuit shown in (c). As shown in FIGS. 14A to 14C, the transistor T is formed in the well layer of the semiconductor substrate.
Two diffusion layers serving as a source / drain of 1 (T2) are formed, and a gate is provided on a semiconductor substrate located between the two diffusion layers. The word line WL is connected to the gate of the transistor T1 (T2), and the bit line B
L is connected to one diffusion layer of the transistor T1 (T2). Further, one electrode of the capacitor C1 (C2) is connected to the cell plate line CP, and the capacitor C1 (C2
The other electrode of 2) is connected to the transistor T via the node NdA.
1 (T2) is connected to the other diffusion layer.

Here, in FIGS. 14 (a) to 14 (c),
Since the node NdA is in contact with the diffusion layer of the transistor T1 (T2) formed in the well layer, when the transistor T1 (T2) is OFF, leakage occurs between the diffusion layer and the well layer over time. A current is generated, and the potential of this node NdA is charged until it becomes equal to the potential of the well layer.

Thus, the pass transistor T1 (T
When the OFF state of 2) continues and the potential of the cell plate line CP is different from the potential of the well layer, for example, the potential of the P well layer is generally V as shown in FIG.
It is the SS level. Therefore, when the cell plate line CP is set to the high potential state (power supply voltage level) in the non-selected state, the potential of the node NdA becomes the VSS level with the lapse of time, so that the ferroelectric capacitor A potential difference is generated between the electrodes on both sides, and there is a risk that the polarization of the ferroelectric substance may be reversed by mistake.

Similarly, in the case of the memory cell having the structure shown in FIG. 14B, since the N well layer is normally at a high potential (power supply voltage VCC), the potential of the cell plate line CP is low at the standby time. If it is (ground potential VSS), the polarization is erroneously inverted.

In the case of the memory cell having the structure shown in FIG. 14C, since the node NdA is connected to both the P well layer and the N well layer, the power supply voltage VCC and the ground potential VSS are Is charged in the middle of. Therefore, if a long time elapses in the non-selected state, there is a possibility that the polarization may be erroneously reversed regardless of whether the potential of the cell plate line CP is set to the high potential or the low potential.

As is apparent from the above description, the 2T2C type memory cell shown in FIG. 12 has a structure in which the memory cells shown in FIG.
Even in the 2C type memory cell, if the potential is set as described above, there is a possibility that the polarization may be erroneously inverted in the non-selected state.

The conventional cell plate line drive circuit for memory cells also has the following problems.
FIG. 16 shows a cell plate line drive circuit of a conventional memory. In the figure, RD is a decode selection signal for selecting a cell plate line, and is a signal for selecting a specific cell plate line from a plurality of arranged cell plate lines. CPO is the cell plate line CP
Is the source signal of. As shown in the figure, the cell plate line C
The cell plate line signal CP is generated by taking the logical product of the P source signal CPO and the decode signal RD. Therefore, when the memory cell is not selected, the decode signal RD becomes the low potential "L", and the logic of the cell plate line signal CP is "L" as shown in the truth table attached to FIG.
That is, the configuration of such a cell plate line drive circuit also causes a potential difference in the capacitor electrodes in the non-selected state, which may be one of the causes of erroneous polarization reversal.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory cell with a capacitor having a capacitance portion made of a material having a hysteresis characteristic with respect to a charge retention function such as a ferroelectric substance. An object of the present invention is to provide a semiconductor memory device capable of preventing erroneous reversal of polarization of a capacitor in a non-selected state for a long time.

[0025]

A first solution provided by the present invention to achieve the above object is to fix the potential of a storage node of a memory cell when the memory cell is not selected.

Specifically, the means taken by the invention of claim 1 is as follows.
A capacitor formed by sandwiching a capacitance portion having a hysteresis characteristic with respect to a charge holding function between first and second electrodes, and at least one pass transistor which is connected to the second electrode of the capacitor and can be turned on and off. It is premised on a semiconductor memory device provided with arranged memory cells. A cell plate line connected to the first electrode of the capacitor, a bit line connected to the second electrode of the capacitor through the at least one pass transistor, and an ON state of the at least one pass transistor.
A word line for supplying a signal for controlling OFF,
A potential fixing means for fixing the potential of the second electrode of the capacitor to a predetermined potential when the memory cell is not selected is provided.

The means taken by the invention of claim 2 is as follows:
In this semiconductor memory device, the memory cell is configured such that the pass transistor is turned off in the non-selected state. Further, the potential fixing means is connected to a wiring that connects a node between the second electrode of the capacitor and the pass transistor and the ground power supply, and is connected to the wiring when the pass transistor is turned off.
It is composed of an erroneous inversion prevention transistor which becomes N state.

The means taken by the invention of claim 3 is as follows:
In the semiconductor memory device, the memory cell includes an N-channel type transistor and a P-channel type transistor which are interposed in parallel with each other between the bit line and the second electrode of the capacitor and are turned on / off at the same timing. A transistor is provided, and each pass transistor is turned off in the non-selected state. Further, when the potential fixing means is connected between the node between the second electrode of the capacitor and each pass transistor and the ground power source, and the pass transistor interposed in the wiring is turned off. And an erroneous inversion prevention transistor that is turned on.

The means taken by the invention of claim 4 is as follows:
In the semiconductor memory device, the potential fixing unit precharges the bit line to a predetermined potential, and when the memory cell is in a non-selected state, the word line of the memory cell is selected and the memory cell is selected. The bit line to be connected and the second electrode of the capacitor are connected to each other, and the potential of the second electrode is controlled to be fixed to the bit line potential.

The second solution provided by the present invention is as follows.
The purpose is to suppress the potential difference between both electrodes of the capacitor within a range where polarization inversion does not occur when the memory cell is not selected.

Specifically, the means taken by the invention of claim 5 is a capacitor comprising a capacitance part having a hysteresis characteristic for a charge retention function, sandwiched between first and second electrodes, and the second electrode of the capacitor. It is premised on a semiconductor memory device including a memory cell having at least one pass transistor connected to the switch and capable of switching between ON and OFF states. A cell plate line connected to the first electrode of the capacitor, a bit line connected to the second electrode of the capacitor via the at least one pass transistor, and ON / OFF of the at least one pass transistor. A word line for supplying a signal for controlling the memory cell and the first line when the memory cell is in a non-selected state.
The potential difference eliminating means for making the potential difference between the electrode and the second electrode substantially equal is provided.

The means taken by the invention of claim 6 is as follows.
In the semiconductor memory device, the memory cell is configured such that the pass transistor is turned off in the non-selected state. Further, a wiring connecting the potential difference eliminating means between the node between the second electrode of the capacitor and each pass transistor and the cell plate line, and the path transistor interposed in the wiring, the pass transistor is OF
It is composed of an erroneous inversion prevention transistor which is turned on when it is in the F state.

The measures taken by the invention of claim 7 are as follows:
In the semiconductor memory device, an N-channel type transistor and a P-channel type transistor which are provided in the memory cell in parallel with each other between the bit line and the second electrode of the capacitor and are turned on and off at the same timing. And are provided so that each of the pass transistors is turned off in the non-selected state. Further, the potential difference eliminating means is connected to a line connecting the node between the second electrode of the capacitor and each pass transistor and the cell plate line, and the pass transistor interposed in the line is turned off. It is composed of a transistor for preventing erroneous inversion which is sometimes turned on.

The means taken by the invention of claim 8 is as follows.
Alternatively, in the semiconductor memory device of No. 7, the control signal line for controlling ON / OFF of the erroneous inversion prevention transistor has a channel opposite to the inversion prevention transistor of the N-channel type transistor and the P-channel type transistor. The structure is such that they are commonly connected to the word lines of transistors having a mold.

The measures taken by the invention of claim 9 are as follows:
In the semiconductor memory device, the N-channel type transistor formed in the P-type well layer and the P-channel type transistor formed in the N-type well layer are arranged in the memory cell. Further, the potential difference eliminating means is set to the same potential as the cell plate line when the memory cell is in a non-selected state and at least in the selected state of the P-type well layer and the N-type well layer. The potential of the cell plate is controlled to be changed to the same potential as the cell plate line.

According to a tenth aspect of the present invention, in the semiconductor memory device of the fifth aspect, the bit line of the memory cell is precharged to the ground level, and the cell plate line of the memory cell is in the non-selected state. A low potential is maintained and a pulse is applied to the power supply voltage during writing and reading. Further, in the potential difference eliminating means, the word line connected to the memory cell is always set to a selected state, and the potential of the second electrode of the capacitor is fixed to the bit line potential via the bit line. When the memory cell is selected and the memory is read and written, the word line of the non-selected memory cell is controlled to be inactivated.

Furthermore, a third solution is to bring both potentials of both electrodes of the capacitor into a floating state when the memory cell is in the non-selected state.

Specifically, the means taken by the invention of claim 11 is that a capacitor formed by sandwiching a capacitance part having a hysteresis characteristic with respect to a charge retention function between a first electrode and a second electrode, and the second electrode of the capacitor. It is premised on a memory cell in which at least one pass transistor which is connected and can be switched to an ON / OFF state is arranged. A cell plate line connected to the first electrode of the capacitor, a bit line connected to the second electrode of the capacitor via the at least one pass transistor, and ON / OFF of the at least one pass transistor. A word line for supplying a signal for controlling the memory cell, and a floating means for turning off the pass transistor when the memory cell is in a non-selected state and for bringing the cell plate line into a floating state. It is a thing.

[0039]

With the configuration of the semiconductor memory device described above, the following actions are achieved in the invention of each claim.

According to the first aspect of the present invention, when the memory cell is in a non-selected state, the potential fixing means causes the second capacitor
The potential of the electrode is fixed to a predetermined potential. Therefore, the potential of the second electrode of the capacitor does not change to the power source potential or the ground potential due to the leak current, and erroneous inversion of polarization does not occur.

According to the second aspect of the present invention, when the memory cell is in the non-selected state, the pass transistor is turned off and the second electrode of the capacitor and the bit line are turned off. At that time, since the transistor for preventing erroneous inversion is turned on, the second electrode of the capacitor is fixed to the potential of the ground power supply via the node. Therefore, the action of the invention of claim 1 is exhibited.

According to the invention of claim 3, the same operation as in claim 2 can be achieved even in the memory cell having the CMOS structure.

According to the invention of claim 4, when the memory cell is in a non-selected state, the potential fixing means controls the potential of the word line so that the memory cell is turned on. That is, since the second electrode of the capacitor is fixed to the potential of the bit line, the potential of the second electrode does not change due to the leak current, and the action of the invention of claim 1 is achieved.

According to the fifth aspect of the invention, when the memory cell is in the non-selected state, the potential difference eliminating means makes the potential difference between the first electrode and the second electrode of the capacitor substantially equal.
Therefore, a large potential relationship that inverts the memory holding state along the hysteresis characteristic line of the material forming the capacitor does not occur between both electrodes of the capacitor.

According to the sixth aspect of the invention, when the memory cell is in the non-selected state, the pass transistor is turned off and the second electrode of the capacitor and the bit line are cut off. At that time, the erroneous inversion prevention transistor is turned on, so that the potential of the second electrode of the capacitor becomes equal to the potential of the first electrode. Therefore, the action of the invention of claim 5 is achieved.

According to the invention of claim 7, the same operation as in claim 6 can be achieved even in a memory cell having a CMOS structure.

In the invention of claim 8, the above-mentioned claim 3 or 7
In the operation of the present invention, since the control signal line of the transistor for preventing erroneous inversion is shared with the signal line of one of the pair of pass transistors, the circuit configuration is simplified.

According to the ninth aspect of the invention, when the memory cell is in the selected state, the P-type well layer and the N-type well layer are controlled to have potentials which are mutually inverted, and the potential of the cell plate line is the same as that of one well layer. Controlled by. Then, when the memory cell is in the non-selected state, the cell plate line changes to a potential that is inverted from the selected state. At that time, the potential difference eliminating means changes the potential of the well layer, which was maintained at the same potential as the cell plate line in the selected state, to the same potential as the cell plate line, so that the potentials of both electrodes of the capacitor become equal, The operation of the invention of claim 5 is achieved.

In the tenth aspect of the invention, since the word line of the memory cell is always set to the selected state by the potential fixing means, the potential of the capacitor is fixed to the potential of the bit line. On the other hand, when the memory cell is selected, the word line of the non-selected memory cell is deactivated, so that writing / reading is possible in the selected memory cell. On the other hand, in the non-selected memory cell, the word line is deactivated, so that the pass transistor is turned off and the bit line and the second electrode are cut off. Therefore, both the cell plate line and the bit line have a low potential, and a large potential difference does not occur between both electrodes of the capacitor. Therefore, the action of the invention of claim 5 is achieved.

According to the eleventh aspect of the present invention, when the memory cell is in the non-selected state, the pass transistor is in the OFF state, so that the potential of the second electrode of the capacitor is separated from the bit line potential and becomes the floating state. On the other hand, when the memory cell is brought into the non-selected state by the potential difference eliminating means, the potential of the cell plate line also becomes in the floating state. Therefore, a large potential difference that causes reversal of polarization does not occur between both electrodes.

[0051]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

First, the configuration of the semiconductor memory device according to this embodiment will be described.

FIG. 1A is an electric circuit diagram showing a partial configuration of the semiconductor memory device of this embodiment. As shown in FIG. 1A, a CMOS transistor is formed in a memory cell for storing 1-bit data,
Two pass transistors T11 whose drains are connected
(N-channel type transistor), T12 (P-channel type transistor), and a ferroelectric capacitor C11 connected to the source / drain of each transistor via a node NdA (storage node) are arranged. Then, a bit line BL11 for reading and writing data,
A word line WL11 for applying a signal for selecting a memory cell to the gate of the N-channel type transistor T11;
A complementary word line XWL11 for applying a signal complementary to the word line WL11 to the gate of the P-channel type transistor T12, and a cell plate line CP11 connected to one electrode (first electrode) of the ferroelectric capacitor C11. It is connected to a memory cell. The ferroelectric capacitor C
The electrode connected to the node NdA of 11 is the second electrode.

As a feature of this embodiment, in the memory cell, a reset transistor T for fixing the potential of the node NdA between the node NdA and the ground power source.
13 (N-channel type transistor) is provided.
Here, the configuration of the memory cell shown in FIG. 1A shows a basic unit of the memory cell corresponding to FIG. 13C of the above-mentioned conventional example, in which one set of pass transistors and one strong transistor are provided. The dielectric capacitor is configured to store 1-bit data.

However, as shown in FIG.
Even if the reset transistor according to the present embodiment is provided in the 2T2C type memory cell configured to store 1-bit data, the circuit shown in FIG. The same effect as that of the example can be obtained.

Although not shown, the cross-sectional structure of the memory cell in this embodiment is the structure shown in FIG. 14 (c) to which a reset transistor T13 is added. That is, the node NdA is connected to each pass transistor T1.
The diffusion layers 1 and T12 are connected to the P-type well layer and the N-type well layer, respectively, and each well layer is connected to the ground power supply and the drive power supply, respectively. Further, the reset transistor T13 can be formed, for example, in the same P-type well layer as the pass transistor T11, and one diffusion layer is connected to the node NdA and the other diffusion layer is connected to the ground power supply.

Next, the operation of the semiconductor memory device shown in FIG. 1A will be described. To select this memory cell, the word line WL11 is set to high potential, for example, the power supply voltage VCC, the complementary word line XWL11 is set to low potential, for example, ground potential, and the gate control signal RST of the reset transistor T14 is set to low potential, for example, ground. Set to potential. As a result, the bit line BL11 and the ferroelectric capacitor C11 are electrically connected. At the time of reading, the bit line BL11 is precharged to the ground potential and a high-potential pulse signal is applied to the cell plate line CP, as in the description of FIG. 9 of the conventional example.

On the other hand, in order to deselect this memory cell, the word line WL11 is set to the ground potential and the complementary word line XW is set.
L11 is the power supply potential. At this time, each transistor T
11, T12 are in the OFF state. Then, when the gate signal RST of the reset transistor T13 which is an N-channel type transistor is set to a high potential, for example, a power source potential,
The reset transistor T13 is turned on, and the potential of the node NdA is fixed to the ground potential. That is, FIG.
The potential of the node NdA shown in (a) does not float even in the standby state, and does not change due to the leak current between the diffusion layer and the well layer. Therefore, even if the non-selected state continues for a long time, erroneous inversion of polarization of the ferroelectric capacitor does not occur.

Next, a modification of the first embodiment will be described. The RST signal described in FIG. 1A above is a signal that is controlled independently of the word line signal,
As shown in FIG. 1B, the reset transistor T13
It is possible to share the gate control signal with the signal of the complementary word line XWL. FIG. 1B is a diagram showing an example of a circuit having such a configuration.

To select the memory cell shown in FIG. 1B, the word line WL11 is set to a high voltage, for example, the power supply voltage, and the complementary word line XWL11 is selected, as in the case of FIG. 1A.
Is set to a low potential, for example, the ground potential. As a result, the bit line BL11 and the ferroelectric capacitor C11 are connected.
In reading, the bit line BL11 is precharged to the ground potential and a high-potential pulse signal is applied to the cell plate line CP11 in the same manner as in the conventional example shown in FIG.

To deselect this memory cell, the word line WL11 is set to the ground potential and the complementary word line XW is set.
L11 is the power supply potential. At this time, since a signal common to the complementary word line XWL11 is applied to the gate of the reset transistor T14, the reset transistor T13
Is turned on, and the node NdA is fixed to the ground potential. Therefore, the node NdA of the circuit shown in FIG.
Does not become floating even in the non-selected state, and the potential does not change due to the leak current between the diffusion layer and the well layer. That is, the configuration shown in FIG. 1B can also achieve the same effect as the circuit having the configuration shown in FIG.

In the first embodiment, the case where the present invention is applied to the conventional circuit shown in FIG. 13 (c) has been described, but it is shown in FIG. 13 (a), FIG. 13 (b) or FIG. It goes without saying that the present invention can be applied to a circuit. That is, a reset transistor is provided between the power supply of a constant voltage and the node NdA between the ferroelectric capacitor of the DRAM memory cell and the pass transistor, and the reset transistor is turned on when the corresponding memory cell is not selected.
With this configuration, the potential of the node NdA in the non-selected state can be fixed, so that the same effect as the first embodiment can be obtained.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. 2 (a) and 2 (b). In the circuit shown in FIG. 2A, two pass transistors T21 (N-channel type transistors) and T22 that form a CMOS transistor and have their sources and drains connected to each other.
A (P-channel type transistor) and a ferroelectric capacitor C21 connected to the source / drain of each transistor via a node NdA are arranged. Then, a bit line BL21 for reading and writing data, a word line WL21 for applying a signal for selecting a memory cell to the gate of the N-channel type transistor T21, and a signal complementary to the word line WL21 are P-channel type. Complementary word line XWL2 for applying to the gate of transistor T22
1 and a cell plate line CP21 connected to one electrode (first electrode) of the ferroelectric capacitor C21 are connected to the memory cell. The electrode connected to the node NdA of the ferroelectric capacitor C21 is the second electrode.

Here, as a feature of this embodiment, the node NdA and the cell plate line CP21 are connected by a wiring, and a short transistor T23 (N-channel type transistor) is provided in this wiring. In other words, when the short transistor T23 is in the ON state, the two electrodes of the ferroelectric capacitor C21 are in a conductive state, and the potentials of the two are short-circuited.

FIG. 2A shows an example in which the present invention is applied to the structure of the memory cell shown in FIG. 13C described in the above-mentioned conventional example. The present invention can also be applied to the structure of the memory cell shown in FIG.

Next, the operation of the semiconductor memory device of this embodiment will be described. In FIG. 2A, to select this memory cell, the word line WL21 is set to a high voltage such as a power supply voltage, and the complementary word line XWL21 is set to a low potential such as a ground potential. This brings the bit line BL21 and the ferroelectric capacitor C21 into conduction. And
At the time of reading, the bit line is precharged to the ground potential in the same manner as described with reference to FIG. 9 of the conventional example.
A pulse signal of the power supply voltage is applied to the cell plate line.

On the other hand, in order to deselect this memory cell, the word line WL21 is set to the ground potential and the complementary word line XW is set.
L21 is the power supply potential. At this time, the gate of the short transistor T23, which is an N-channel type transistor, receives a signal from the complementary word line XWL, so that the short transistor T23 is turned on and both electrodes of the ferroelectric capacitor C21 are short-circuited. Therefore, the second electrode connected to the node NdA of the ferroelectric capacitor C21 does not become floating even in the non-selected state, and therefore it is possible to effectively prevent erroneous polarization reversal in the non-selected state.

Next, a modification of the second embodiment will be described. In the above-described FIG. 2A, the transistor T21 is an N-channel type transistor, and
22 is a P-channel type transistor and the short transistor T23 is an N-channel type transistor. As shown in FIG. 2B, the transistors T21, T22 and T23 are shown in FIG. 2A, respectively. The transistor T22 and the short transistor T are composed of transistors having a channel type opposite to the channel type.
23 is connected to the word line WL21, and the transistor T21
The complementary word line XWL21 may be connected to. Even in this case, it goes without saying that the same effect as that of the circuit shown in FIG.

In the second embodiment, the case where the present invention is applied to the conventional circuit shown in FIG. 13 (c) has been described, but it is shown in FIG. 13 (a), FIG. 13 (b) or FIG. It goes without saying that the present invention can be applied to a circuit. That is, by arranging the short transistor between the node and the cell plate line and turning on the short transistor when the corresponding memory cell is not selected, the polarization of the ferroelectric capacitor in the unselected state is erroneous. Inversion can be prevented.

(Third Embodiment) Next, a third embodiment will be described with reference to FIGS. In this embodiment, the memory cell has the same structure as that shown in FIG.
It is configured as shown in FIG. In the selection / non-selection operation of the memory cell in the above conventional example, as shown in FIG.
Since each signal line enters the non-selected state while the read or write operation is completed, the word line WL is in the low potential state, the complementary word line XWL is in the high potential state, and the cell plate line CP is in the low state in the non-selected state. It is in a potential state. The bit line pair BL, XBL is precharged to the ground potential.

On the other hand, in the present embodiment, as shown in the timing chart of FIG. 3, when the memory cell selection signal XCE is in the high potential state, the memory cell is in the non-selected state, and the word line WL and the complementary word line XWL are separated from each other. Activated Figure 13
The two pass transistors shown in (c) are turned on. However, in the selected state, a pulse signal is applied to the bit line pair BL, XBL at the time of read / write operation,
Since the pulse signal is not applied to the bit line pair in the non-selected state, the read / write operation in the non-selected memory cell is not performed. As a result, the ferroelectric capacitor and the bit line BL are brought into conduction even in the non-selected state. Since the bit line pair BL, XBL is precharged to the predetermined potential in the non-selected state, the potential of the node connected to one electrode (second electrode) of the ferroelectric capacitor is fixed, and the node NdA. It is possible to effectively prevent erroneous inversion of polarization due to the potential of the floating state.

Next, a modification of this embodiment will be described with reference to the timing chart of FIG. Figure 3 above
In the example shown in FIG. 4, the signals of both the word line WL and the complementary word line XWL are activated during standby to fix the potential of the node of the capacitor of the memory cell, but in the timing chart shown in FIG. , Only the word line WL is activated and the complementary word line XWL is not activated. Also in this case, in the non-selected state, as shown in FIG.
Since the pass transistor of the N-channel type transistor in the circuit shown in (c) is turned on and the node NdA and the bit line BL are conducted, the potential of the ferroelectric capacitor is fixed and erroneous polarization reversal is effectively prevented. can do.

Next, another modification of this embodiment will be described with reference to the timing chart of FIG. In the example shown in FIG. 5, contrary to the example shown in FIG. 4, the word line WL is inactivated even in the non-selected state, and the complementary word line XW
By activating L, the P-channel type transistor of the memory cell is made conductive to fix the potential of the capacitor node. However, in this embodiment, the bit line is precharged to the power supply potential. In this example as well, similar to the method shown in FIGS. 3 and 4, it is possible to effectively prevent erroneous polarization reversal.

That is, as shown in FIGS.
The bit line potential is precharged to a predetermined potential, and in the non-selected state of the memory cell, the word line of the memory cell is selected and the pass transistor is turned on without applying a pulse signal to the bit line potential, By fixing the potential of the node to the potential of the bit line, it is possible to prevent erroneous inversion of polarization of the ferroelectric capacitor.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIGS. 6 (a) to 6 (c). Here, FIG. 6A is the same as FIG. 13C described in the conventional example.
Shows a vertical cross-sectional structure of a memory cell that almost corresponds to the circuit of
The structure of the memory cell in this embodiment is the same as that shown in FIG.
It is almost the same as the longitudinal sectional structure shown in (c). That is,
An N channel type transistor T11 is formed in the P type well layer, and a P channel type transistor T12 is formed in the N type well layer.
Is formed, one diffusion layer of each transistor is connected to the ferroelectric capacitor C11 via the common node NdA, and the other diffusion layer of each transistor T11, T12 is connected to the common bit line BL. However, the memory cell of this embodiment is different in that the potentials VPW and VNW of the P-type well layer and the N-type well layer are not fixed to the ground potential or the power supply potential. That is, the P-type well layer potential VPW,
Although not shown, the N-type well layer potential VNW is set to the ground potential or the power potential, respectively, during a normal write / read operation by a power supply circuit capable of switching the supply voltage. It is configured to be switched to.

Next, the operation of the semiconductor memory device of this embodiment will be described with reference to FIG. In the conventional CMOS circuit, the potentials VPW and VNW of the P-type well layer and the N-type well layer are usually fixed to the ground potential and the power supply potential for operation. On the other hand, in this embodiment, as shown in FIG.
As shown in the timing chart of (b), the potential of the bit line pair BL, XBL is precharged to the ground potential, and in the selected state, the potential VPW of the P-type well layer is set to the ground potential and the potential of the N-type well layer is set. The potential of VNW is set to the power supply potential, and the pulse signal is applied to the cell plate line CP. On the other hand, in the non-selected state, the cell plate line CP is set to the ground potential, and the potentials VPW and VNW of each well layer are set to the ground potential. That is, during a normal write / read operation, the P-type well layer and the N-type well layer are formed as in the conventional CMOS circuit.
The respective potentials VPW and VNW of the type well layer are set to the ground potential and the power source potential to operate, but in the non-selected state, the potential VNW of the N type well layer in which the P-channel type transistor is formed is grounded from the power source potential. Change to electric potential. That is, the potential of the well layer (N-type well layer) that is the same as the potential of the cell plate line CP during the operation in the selected state is set to be the same potential as the cell plate line CP even in the non-selected state. As a result, the potential of the electrode on the side facing the electrode fixed to the ground potential by the cell plate line CP of the ferroelectric capacitor C11, that is, the node NdA and the potential of the P-type well layer and the N-type well layer are the same ground. It becomes a potential, and there is no leak path with the power supply potential. Therefore, even if the pass transistors T11 and T12 of the memory cell are turned off, the potential of the node NdA rises to the power supply potential, and erroneous inversion of polarization can be effectively prevented.

Next, FIG. 6C, which is a modification of the present embodiment.
The method shown in will be described. In the timing chart shown in FIG. 6C, the bit line potential is precharged to the power supply potential, the potential of the cell plate line CP is set to the power supply potential in the non-selected state, and the pulse signal of the ground potential is set at the time of writing and reading. Apply. Further, as in the case of FIG. 6B described above, during the normal write / read operation, the potentials VPW and VNW of the P-type well layer and the N-type well layer are set to the ground potential and the power supply potential for operation. However, in the non-selected state, the potential VPW of the P-type well layer is changed from the ground potential to the power supply potential. As a result, the potential of the electrode opposite to the electrode fixed to the power supply potential by the cell plate line CP of the ferroelectric capacitor, that is, the node NdA and the potential of the P-type well layer and the N-type well layer become the same ground potential. , There is no leak path with the ground potential at the opposing electrodes,
Even if the pass transistor of the memory cell is turned off, there is no possibility that the potential drops to the ground potential and the polarization is inverted.
In this way, by changing the well potential in the non-selected state, no potential difference is generated between the electrodes of the ferroelectric capacitor, so that the polarization inversion in the state other than the original write / read operation does not occur. You can

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIG. In the write / read operation in the conventional example, as shown in FIG. 15, the word line WL connected to the N-type pass transistor of the selected memory cell is set to a high potential state, and the complementary word connected to the P-channel type pass transistor of the selected memory cell is set. A memory cell is selected by putting the line XWL into a low potential state. At this time,
Since the word line WL connected to the N-channel type pass transistor of the unselected memory cell is kept in the low potential state and the word line WL connected to the P-channel type pass transistor is kept in the high potential state, all the pass transistors are in the OFF state. Therefore, the electrodes of the ferroelectric capacitors connected to the respective pass transistors are in a floating state.

On the other hand, in this embodiment, the same FIG.
With respect to the memory cell having the structure shown in (c), the potential of the bit line BL is precharged to the ground potential, and the potential of the cell plate line CP is set to a low potential state when not selected, while the potential of the selected state is changed. A pulse signal of a power supply voltage is applied to the cell plate line CP during writing and reading.

That is, as shown in FIG. 7, the word lines WL connected to all the memory cells are always set to the selected state. In the memory having the ferroelectric capacitor, the data of the memory cell is not read unless the pulse signal is applied to the cell plate line CP even if the word line WL is selected. Therefore, the word line WL is always selected. However, the data in the memory cell is not destroyed. Then, when writing and reading are performed, all of the word lines WL and the complementary word lines XWL connected to the unselected memory cells are brought into a non-selected state, and only the word line WL to be written and read is kept in a selected state. Then, a high-potential pulse signal is applied through the cell plate line CP. When the signal on the word line WL is operated in this manner, the write / read operation in the selected memory cell is smoothly performed, while one of the electrodes of the ferroelectric capacitors of the memory cells in the non-selected state is at the ground potential. Since it is connected to the pair of bit lines BL and XBL set to, and the other is connected to the cell plate line CP at the ground potential, no potential difference is generated between the electrodes of the ferroelectric capacitor. As described above, by making the potentials of the electrodes of the ferroelectric capacitor substantially equal, it is possible to prevent the polarization of the ferroelectric capacitor from being inverted in a state other than the original write / read operation. That is, it is possible to effectively prevent erroneous inversion of polarization of the ferroelectric capacitor in the non-selected state. In this embodiment, the example in which both the word line WL and the complementary word line XWL are always selected is shown, but the word line WL and the complementary word line X are selected.
The same effect can be obtained by selecting only one of the WLs.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to FIGS. 8 (a) and 8 (b). None of the above-described embodiments is connected to the cell plate line for the purpose of preventing a potential difference that causes an erroneous inversion of polarization between the electrode of the ferroelectric capacitor connected to the cell plate line and the other electrode. The present invention relates to a method for setting the electrode potential to the same potential as the cell plate line potential. In order to prevent a potential difference from occurring between the electrodes of the ferroelectric capacitor when the electrode that is not connected to the cell plate line, that is, the node is in the floating state when the pass transistor is in the OFF state, the same applies to the electrode connected to the cell plate line. It is also possible to put it in a floating state. The method of making the cell plate line in a floating state will be described below.

FIG. 8A shows the structure of the cell plate line drive circuit according to this embodiment. The cell plate line drive circuit is arranged between the cell plate line drive buffer and the cell plate line CP. As shown in the figure, a NAND circuit and an inverter circuit are arranged in series, and further between the inverter and the cell plate line CP,
An N-channel type pass transistor T31 and a P-channel type transistor T32 are provided, and the decode signal RD is input to the gate of the pass transistor T31, while the NAND circuit controls the gate of the pass transistor T32 by its inverted signal. With this circuit configuration, the logic of the signal output to the cell plate line is as shown in the truth table attached to FIG. That is, when the memory cell is in the non-selected state, the decode signal RD is at the low potential “L”,
The signal on the cell plate line CP is in a floating state (Hi
gh-Z state). Therefore, in the non-selected state of the memory cell, one of the ferroelectric capacitors of the memory cell is
Both electrodes of the pair are in a floating state, and there is no large potential difference between both electrodes of the capacitor, which causes erroneous inversion of polarization.

Next, FIG. 8 shows a modification of this embodiment.
Description will be given with reference to (b). In this modification, four transistors T33, T34, T35 and T3 are used instead of the pass transistors T31 and T32 shown in FIG.
6 (transistor T34 is a P-channel type transistor, other than that is an N-channel type transistor) is connected in series between a driving power source and a ground power source to form a logic gate. Also in this modified example, FIG.
Similar to the circuit shown in (a), the logic of the signal output to the cell plate line CP is as shown in the truth table attached to the figure. Also in this circuit example, as described above, when the non-selected state of the memory cell continues, a large potential difference that causes erroneous inversion of polarization is not generated between the pair of electrodes of the ferroelectric capacitor. Absent.

[0084]

As described above, claims 1, 2, and
According to the invention of 3, 4, or 8, the potential of the second electrode connected to the pass transistor of the capacitor in the non-selected state of the semiconductor memory device is fixed to a predetermined potential, so that the non-selected state is for a long time. It is possible to effectively prevent the erroneous reversal of polarization even when it is continued, and thus it is possible to improve the storage characteristics of the semiconductor memory device.

According to the invention of claim 5, 6, 7, 8, 9 or 10, the potential difference between both electrodes of the capacitor in the non-selected state of the semiconductor memory device is suppressed to a predetermined value or less. Even when the selected state continues for a long time, erroneous polarization reversal can be effectively prevented, and thus the storage characteristics of the semiconductor memory device can be improved.

According to the eleventh aspect of the invention, when the memory cell is in the non-selected state, the potentials of both electrodes of the memory cell capacitor are set to the floating state.
Even when the non-selected state continues for a long time, it is possible to effectively prevent the occurrence of a large potential difference that causes erroneous inversion of polarization, and thus it is possible to improve the storage characteristics of the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing a configuration of a memory cell of a semiconductor memory device according to a first example and its modification.

FIG. 2 is an electric circuit diagram showing a configuration of a memory cell of a semiconductor memory device according to a second embodiment and its modification.

FIG. 3 is a timing chart showing control contents of a semiconductor memory device according to a third embodiment.

FIG. 4 is a timing chart showing the control contents of a semiconductor memory device in a modification of the third embodiment.

FIG. 5 is a timing chart showing the control contents of a semiconductor memory device in a modification of the third embodiment.

FIG. 6 is a cross-sectional view showing a configuration of a memory cell of a semiconductor memory device according to a fourth example and a timing chart showing control contents thereof.

FIG. 7 is a timing chart showing the control contents of the semiconductor memory device according to the fifth example.

FIG. 8 is an electric circuit diagram showing a partial configuration of a cell plate line drive circuit of a semiconductor memory device according to a sixth example.

FIG. 9 is an electric circuit diagram showing a partial configuration of a conventional DRAM type ferroelectric non-volatile memory cell array.

FIG. 10 is a characteristic diagram showing a hysteresis characteristic of self-polarization of a ferroelectric with respect to a voltage applied to a general ferroelectric.

FIG. 11 is a timing chart showing a basic read operation of a conventional DRAM type ferroelectric non-volatile memory.

FIG. 12 is an electric circuit diagram showing a configuration of a conventional 2T2C DRAM type ferroelectric non-volatile memory cell.

FIG. 13 is an electric circuit diagram showing the configuration of various conventional 1T1C DRAM type ferroelectric non-volatile memory cells.

FIG. 14 is a cross-sectional view showing the structure of various conventional 1T1C DRAM type ferroelectric non-volatile memory cells.

FIG. 15 is a timing chart showing control contents of a conventional DRAM type ferroelectric non-volatile memory in a selected state and a non-selected state.

FIG. 16 is an electric circuit diagram showing a configuration of a cell plate line drive circuit of a conventional DRAM type ferroelectric non-volatile memory.

[Explanation of symbols]

 BL bit line C capacitor WL word line T transistor CP cell plate line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/8242 (72) Inventor Joji Nakane 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (11)

[Claims] 1. A capacitor in which a capacitance portion having a hysteresis characteristic with respect to a charge holding function is sandwiched between first and second electrodes, and an ON capacitor connected to the second electrode of the capacitor.
A memory cell having at least one pass transistor switchable to an OFF state, a cell plate line connected to the first electrode of the capacitor, and the at least one pass transistor on the second electrode of the capacitor. ON / OFF of the bit line connected through the at least one pass transistor
A semiconductor memory comprising: a word line for supplying a signal for controlling the voltage; and a potential fixing means for fixing the potential of the second electrode of the capacitor to a predetermined potential when the memory cell is not selected. apparatus. 2. The semiconductor memory device according to claim 1, wherein the memory cell is configured such that the pass transistor is in an OFF state in a non-selected state, and the potential fixing means is the second capacitor of the capacitor. A wiring connecting a node between the electrode and the pass transistor and the ground power supply, and a transistor for preventing erroneous inversion which is interposed in the wiring and is turned on when the pass transistor is turned off. A semiconductor memory device characterized by being present. 3. The semiconductor memory device according to claim 1, wherein the memory cell is provided in parallel between the bit line and the second electrode of the capacitor, and is turned on / off at the same timing. The N-channel type transistor and the P-channel type transistor are arranged so that each of the pass transistors is in an OFF state in a non-selected state, and the potential fixing means is the second electrode of each of the capacitors Wiring that connects between the node between the pass transistors and the ground power supply, and the above-mentioned pass transistors that are interposed in the wiring and are turned off
A semiconductor memory device comprising: a transistor for preventing erroneous inversion which is turned on when the semiconductor memory device is turned on. 4. The semiconductor memory device according to claim 1, wherein the potential fixing means precharges the bit line to a predetermined potential, and when the memory cell is in a non-selected state, the word of the memory cell is selected. A semiconductor memory device is characterized in that a line is selected and the bit line connected to the memory cell is connected to the second electrode of the capacitor to control the potential of the second electrode to be fixed to the bit line potential. . 5. A capacitor formed by sandwiching a capacitance portion having a hysteresis characteristic with respect to a charge holding function between first and second electrodes, and an ON capacitor connected to the second electrode of the capacitor.
A memory cell having at least one pass transistor switchable to an OFF state, a cell plate line connected to the first electrode of the capacitor, and the at least one pass transistor on the second electrode of the capacitor. ON / OFF of the bit line connected through the at least one pass transistor
A word line for supplying a signal for controlling the voltage difference, and a potential difference eliminating means for substantially equalizing the potential difference between the first electrode and the second electrode when the memory cell is in a non-selected state. Semiconductor memory device. 6. The semiconductor memory device according to claim 5, wherein the memory cell is configured such that the pass transistor is in an OFF state in a non-selected state, and the potential difference eliminating means is the second capacitor of the capacitor. A wiring that connects a node between the electrode and each pass transistor and the cell plate line, and a transistor for erroneous inversion prevention that is interposed in the wiring and is turned on when the pass transistor is turned off. A semiconductor memory device characterized by being configured. 7. The semiconductor memory device according to claim 5, wherein the memory cell is provided in parallel with each other between the bit line and the second electrode of the capacitor, and is turned on / off at the same timing. The N-channel type transistor and the P-channel type transistor are arranged so that each of the pass transistors is in an OFF state in a non-selected state. Wiring that connects the node between the pass transistors and the cell plate line, and the above-mentioned pass transistors that are provided in the wiring are turned off.
A semiconductor memory device comprising: a transistor for preventing erroneous inversion which is turned on when the semiconductor memory device is turned on. 8. The semiconductor memory device according to claim 3, wherein the control signal line for controlling ON / OFF of the erroneous inversion prevention transistor is one of the N-channel transistor and the P-channel transistor. A semiconductor memory device, which is commonly connected to a word line of a transistor having a channel type opposite to that of an inversion prevention transistor. 9. The semiconductor memory device according to claim 5, wherein an N channel type transistor formed in a P type well layer and a P channel type transistor formed in an N type well layer are arranged in said memory cell. The potential difference eliminating means is set to the same potential as the cell plate line when at least the P-type well layer and the N-type well layer are in the selected state when the memory cell is in the non-selected state. A semiconductor memory device characterized in that the potential of the well layer is controlled to be changed to the same potential as the cell plate line. 10. The semiconductor memory device according to claim 5, wherein the bit line of the memory cell is precharged to a ground level, and the cell plate line of the memory cell is maintained at a low potential in a non-selected state. It is configured such that a pulse is applied to the power supply voltage at the time of writing / reading, and the potential difference eliminating means always sets the word line connected to the memory cell to a selected state and sets the capacitor of the capacitor via the bit line. A semiconductor characterized in that the potential of the second electrode is fixed to the bit line potential, and when the memory cell is selected to perform the memory read / write operation, the word line of the non-selected memory cell is controlled to be inactivated. Storage device. 11. A capacitor formed by sandwiching a capacitance portion having a hysteresis characteristic with respect to a charge holding function between first and second electrodes and an ON connected to the second electrode of the capacitor.
A memory cell having at least one pass transistor switchable to an OFF state, a cell plate line connected to the first electrode of the capacitor, and the at least one pass transistor on the second electrode of the capacitor ON / OFF of the bit line connected through the at least one pass transistor
A word line for supplying a signal for controlling the memory cell and a floating means for turning off the pass transistor when the memory cell is in a non-selected state and for bringing the cell plate line into a floating state. A characteristic semiconductor memory device.