JPH08138390A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To shorten the stress test time for a tunnel insulation film in a flash memory by selecting all memory cells on a chip and externally applying a voltage for charging or discharging the floating gate of a memory cell. CONSTITUTION: Each memory cell in a memory cell array forming a flash memory has a floating gate and the memory state is differentiated by charging or discharging the floating gate. All memory cells in the memory cell array are selected simultaneously by an external signal fed from a dedicated bonding pad ASP through control circuits X, Y. When a voltage according to the writing conditions and a voltage according to the erasing conditions are applied alternately under that state through test pads V1-V4, the floating gate can be charged or discharged simultaneously for all memory cells and the stress test time for the tunnel insulation film of flash memory can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reducing the test time of a semiconductor memory device.

[0002]

2. Description of the Related Art A conventional example will be described. In the following description, a symbol representing a terminal name also serves as a wiring name and a signal name, and also serves as a voltage value in the case of a power supply.

In a flash memory, a method of using a tunnel current for writing and erasing is performed. In FIG. 9, 1
994 Symposium on B.S.I.S. Circuits, pages 61 to 62 (1994 SYMPOSIUM ON VLSI C
A memory cell-related circuit according to the above method described in IRCUITS, pp. 61-62) is shown.

In such a memory, in order to investigate the initial failure of the tunnel insulating film, stress is applied to the tunnel insulating film by applying a flash-specific write and erase voltage. Therefore, like the normal write operation, for example, the sense latch circuits SL1 to SL4 hold 3V, the word line W00 is set to -9V, and ST1 is set to a high level to turn on the switch MOS connected thereto. Then, STS1 is set to a low level to turn off the switch MOS connected thereto, and the switches S01 to S01
Turn on 04. As a result, −9V is applied to the control gate of the memory cell, 3V is applied to the drain, and the source is in a floating state. At this time, the substrate is at 0V. This state is maintained for 1 millisecond, for example, to apply stress to the tunnel insulating film.

Next, the above voltage is applied to all memory cells while changing the memory cells to be applied. That is, if a voltage is applied simultaneously to, for example, 4 kilobits of memory cells at one time, in order to do this for all memory cells, it is about 16,000 times for 64 megabits and about 66,000 times for 256 megabits. Will be done. Next, while applying the erase voltage to the memory cells in small numbers in the same manner,
Do this for all memory cells. This is done once for all the memory cells, for example, 100,000 times as a test in order to guarantee the operation of 1 million times. Therefore, in the above example, the write and erase operations are performed 1.6 billion times with 64 megabits.

[0006]

In the conventional method, since the internally generated voltage is used for the test, it is difficult to increase the number of memory cells operating in parallel due to the limitation of the driving capability of the internal voltage generating circuit. Therefore, the shortening of the test time was limited. Further, there is no means for performing the voltage applied to the memory cells in the writing operation and the erasing operation peculiar to the flash memory at the same time for all the memory cells, and for alternately performing the writing condition and the erasing condition. Therefore, the shortening of the test time has been limited even in the method of applying the voltage from the outside.

[0007]

According to the present invention, a signal for simultaneously selecting all memory cells is provided, and a voltage necessary for writing and erasing conditions is externally applied to all memory cells. By providing means for applying at the same time, the above-mentioned problems of the prior art have been solved.

[0008]

According to the above means, all the memory cells can be selected at the same time, and the voltage of the condition for writing and the voltage of the condition for erasing can be alternately applied to all the memory cells at the same time.
Therefore, the test time can be significantly reduced.

[0009]

FIG. 1 is a diagram showing a first embodiment of the present invention. In the memory cell array on the chip, a specific memory cell can be selected by the word line W and the data line D, and its control circuit is X and Y. V1 to V4 are internal power supplies and pads peculiar to the present invention, and ASPs are signals and pads that simultaneously select all memory cells peculiar to the present invention. IN represents a plurality of control signals, and Ai represents a plurality of address signals.

V1 to V4 may be used during normal operation or may be used only during testing. Also, ASP
May be provided with a dedicated pad, or may be a signal generated by a combination of signals of other pads or a voltage relationship. In normal operation, a small number (for example, 2 to 3) is generally supplied to the chip by using the internal power supply generation circuit without using V1 to V4.
Is generated from the power source (Vcc, Vss).

A feature of the present invention is that all memory cells can be simultaneously selected by using V1 to V4 and ASP, a voltage required for the test can be applied from the outside, and this can be simultaneously applied to all the memory cells. This can significantly reduce the test time.

FIG. 2 is a diagram showing a second embodiment of the present invention. V1 to V5 are internal power supplies and pads unique to the present invention. A0 to An are representative of address signals of the normal operation signals and pads. DEC1 to DE
C3 is a circuit block for generating a signal for selecting a desired memory cell from these address signals. W0 to Wj are word lines, WD is word selection means, and GD1
˜GDk are global data lines. What is characteristic of this figure is that, in addition to the provision of V1 to V5 and the ASP, a means for simultaneously selecting all the memory cells by the ASP is provided.

That is, the output of DEC1 is input to the word selection means WD, and the ASP is input to this WD. The same applies to DEC2 and DEC3. Therefore, A
If SP is at high level, DEC1 to DEC3 operate normally, but if ASP is at low level, all memory cells are selected. With this, it is possible to directly apply a voltage from V1 to V5 to all the memory cells.
Therefore, there is a feature that the test voltage can be applied to all the memory cells at the same time. A buffer circuit may be added to the ASP and this output may be distributed.

The operation of the present invention will be described with reference to FIG. First, the ASP switches from high level to low level. As a result, as described above, a voltage can be directly applied to all the memory cells from V1 to V5. Below, all voltage values show one example.

First, in order to set the write voltage condition, V
1 to 3V, V2 to 0V, V3 to -9V, V4 to 0
V and V5 are set to 0V. As a result, each memory cell has V1 and V3 between the control gate and drain.
12V which is a voltage difference from Therefore, in each memory cell, the charge is extracted from the floating gate to the drain, and stress can be applied to the tunnel insulating film in this state. After continuing this state for 1 millisecond, for example, an erase voltage condition is applied. At this time, in order to change the external power supply for testing such as V1 to V5, and to set a desired terminal of the memory cell in a floating state, the MOS for the memory cell control switch is changed.
Turn off what you need. The provision of such means is an advantage of the present invention.

Under the erase voltage condition, V1 is 0V, V2 is 12V, V3 is 0V, V4 is -4V, and V5 is -4.
Set to V. As a result, 16V, which is the voltage difference between V2, V4 and V5, is applied to each memory cell between the control gate and the substrate. Therefore, in each memory cell, charges are injected from the substrate to the floating gate, and stress can be applied to the tunnel insulating film in this state. After continuing this state for 1 millisecond, for example, the write voltage condition is applied again.

In this way, the write voltage condition and the erase voltage condition are alternately applied to all the memory cells. After repeating the desired number of times, the threshold voltages of all the memory cells are verified. This is the same as the verification of the normal operation, and the deterioration of the memory cell can be checked by this. This verification also includes how the threshold voltage changes under constant write voltage conditions (time, voltage) before and after the test. The invention is not defined. If necessary, the power supply wiring for supplying the voltage applied from the outside to the inside of the chip may be thick in layout. Further, when switching the voltage applied from the outside, the rising time and the falling time may be set according to the layout thickness of the power supply wiring. Further, it is not necessary to make the write voltage condition and the erase voltage condition constant throughout the test, and the voltage applied to the tunnel insulating film may be increased initially and then decreased as the test progresses.

FIG. 4 is a diagram showing the effect of the present invention. Conventionally, as shown in (a), a so-called parallel test is performed in which a voltage is applied to a large number of memory cells at once rather than during normal operation. However, the degree of parallelism is limited, and it takes about 50 hours, for example, to write and erase 100,000 times in all memory cells. With this, a practically practical test cannot be performed. Here, the test of the flash memory is, in short, how to apply stress to the tunnel insulating film. Therefore, in the present invention, a means for simultaneously selecting all the memory cells is provided, and the voltage applied from the outside is switched to perform the test.

Therefore, according to the present invention, the test voltage can be collectively applied to all the memory cells as shown in (b). As a result, the test time can be shortened from about 50 hours in the case of (a) to about 2 hours in the case of (b).
Furthermore, if high temperature acceleration is also used as shown in (c),
Since the time for writing and erasing once can be shortened, the test time is about 2 hours in the case of (b),
In the case of (c), it can be shortened to about 10 minutes.

Since this method does not prescribe the format of the flash memory cell, FIGS. 5 to 8 show examples of voltage application at the time of testing in each memory cell. AND type memory cell,
NAND type memory cell, DINOR type memory cell, and NO
This is generally called an R-type memory cell, and can be found in the Nikkei Microdevice January 1993 issue (No. 91) No. 59.
Page-Page 63 and Nikkei Microelectronics 1994
It is widely known as described in pages 84 to 91 of the April 11, 2012 issue (No. 605). In the following figures, the word line voltage VW, the memory cell drain voltage VD, the memory cell source voltage VS and the substrate voltage VB are shown. It is a feature of the present invention that it has means for directly applying these voltages from the external power supply terminal and means for simultaneously applying a desired voltage to all the memory cells.

FIG. 5 shows the case of the AND type memory cell shown in FIG. In this memory cell, a small memory cell area can be realized by the contactless structure in which the drain and source of the memory cell are formed by the buried diffusion layer. In the write test, for example, the word line voltage VW is set to -9V, the drain voltage VD is set to 3V, the source VS is set to a floating state (indicated as Open in the figure, the same applies hereinafter), and the substrate voltage VB is set to 0V. In the erase test, for example, the word line voltage VW
Is 12 V, the drain VD is in a floating state, the source voltage VS is -4 V, and the substrate voltage VB is -4 V. By repeating this voltage relationship, it is possible to perform a test in which the write voltage condition and the erase voltage condition are alternately applied to all the memory cells to apply stress to the tunnel insulating film of the memory cells. The circuit method shown in FIG. 1 may be used for the full selection operation.

FIG. 6 shows the case of a NAND type memory cell. In this memory cell, a small memory cell area is realized by a contactless structure in which the memory cells are connected in series. In the write test, for example, the word line voltage V
W is 20V, drain voltage VD is 0V, source voltage VS
Is 0V and the substrate voltage VB is 0V. During the erase test,
For example, the word line voltage VW is 0V, the drain VD is in a floating state, the source VS is in a floating state, and the substrate voltage VB is 20V. By repeating this voltage relationship, it is possible to perform a test in which the write voltage condition and the erase voltage condition are alternately applied to all the memory cells to apply stress to the tunnel insulating film of the memory cells.

FIG. 7 shows the case of a DINOR type memory cell. In this memory cell, a common source is used to realize a small memory cell area and a low parasitic resistance at the time of reading. In the write test, for example, the word line voltage VW
Is −9 V, the drain voltage VD is 3 V, the source VS is in a floating state, and the substrate voltage VB is 0 V. In the erase test, for example, the word line voltage VW is 12V and the drain V is
D is in a floating state, the source voltage VS is -4V, and the substrate voltage VB is -4V. By repeating this voltage relationship, it is possible to perform a test in which the write voltage condition and the erase voltage condition are alternately applied to all the memory cells to apply stress to the tunnel insulating film of the memory cells.

FIG. 8 shows the case of a NOR type memory cell. In this memory cell, the writing is performed by hot electron injection, so that a low internal operating voltage and high-speed writing in a very small unit (the number of memory cells) are realized.
In the write test, for example, the word line voltage VW is 5V,
For example, the drain voltage VD is 5V and the source voltage VS is 0.
V and the substrate voltage VB are set to 0V, for example. In the erase test, for example, the word line voltage VW is 0V, the drain VD is in a floating state, the source voltage VS is 12V, and the substrate voltage VB is 0V. By repeating this voltage relationship, it is possible to perform a test in which the write voltage condition and the erase voltage condition are alternately applied to all the memory cells to apply stress to the insulating film of the memory cells.

Although the present invention has been described with respect to the flash memory, the present invention provides the signal for selecting all the memory cells at the same time, and the means for simultaneously applying the voltage required for the test from the outside to all the memory cells. Is a feature. Therefore, for example, in a so-called FRAM that stores data by utilizing polarization of a ferroelectric substance, it can be applied to a test for selecting an initial defect by applying stress to a ferroelectric film. Further, even in a normal dynamic random access memory (DRAM) or static random access memory (SRAM), it can be applied to a test for selecting an initial defect of an oxide film of a memory cell or a transistor.

[0026]

Since a signal for selecting all the memory cells at the same time is provided, and a means for externally applying a required voltage under the condition of writing and the condition of erasing and simultaneously applying this to all the memory cells is provided. It is possible to select all the memory cells at the same time, and to simultaneously apply the voltage of the condition for writing and the voltage of the condition for erasing to all these memory cells at the same time. Therefore, the test time can be significantly reduced.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a timing chart showing an operation example of the second embodiment.

FIG. 4 is an explanatory view showing the effect of the present invention.

FIG. 5 is an explanatory diagram showing an example of voltage application in the AND type memory cell of the present invention.

FIG. 6 is an explanatory diagram showing an example of voltage application in the NAND memory cell of the present invention.

FIG. 7 is an explanatory diagram showing an example of voltage application in the DINOR type memory cell of the present invention.

FIG. 8 is an explanatory diagram showing an example of voltage application in the NOR memory cell of the present invention.

FIG. 9 is an explanatory diagram showing a conventional example.

[Explanation of symbols]

W00, W0 to Wj ... Word line, GD01 to GD04,
GD1 to GDk ... Global data lines, C1 to C4 ... Memory cells, ST1, STS1 ... MOS control signals for memory cell selection switches, DEC1 to DEC3 ... Decoding circuit, VW ... Word line signal and voltage, VD ... Memory cell drain signal and Voltage, VS ... Memory cell source signal and voltage, VB ... Substrate signal and voltage.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shunichi Saeki 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. Hitachi, Ltd. Semiconductor Division (72) Inventor Katsutaka Kimura 1-280, Higashi Koigokubo, Kokubunji, Tokyo

Claims (8)

[Claims] 1. A semiconductor memory device comprising a floating gate, and a memory cell having a memory state which is changed by injecting or releasing charges to and from the floating gate,
Means for externally applying a voltage for injecting or releasing charges to the floating gate of the memory cell to the semiconductor memory device, and the externally applied voltage is applied to all the memory cells on a chip. And a means for selecting all the memory cells as described above. 2. A semiconductor memory device comprising a floating gate, and a memory cell having a memory state that changes a storage state by injecting or releasing charges into the floating gate,
A means for externally applying a voltage for injecting or releasing charges to the floating gate of the memory cell to the semiconductor memory device, and a voltage applied from the outside for all the memory cells on a chip are applied. And a means for alternately applying a voltage for injecting charges to the floating gates and a voltage for discharging the floating gates to all of the memory cells in succession. Semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein the voltage applied from the outside is applied to a bonding pad provided in parallel with the output of the internal voltage generating means. 4. The means for applying an externally applied voltage to all of the memory cells according to claim 1, 2 or 3, wherein a circuit for selecting a desired memory cell from an address signal is provided in the selection circuit. A semiconductor memory device in which an all-selection signal is added, and the all-selection signal is generated from a dedicated bonding pad or from a combination of voltages or phases of signals of other pads. 5. The memory cell according to claim 1, wherein a first voltage is applied to the control gate of the memory cell and a second voltage is applied to the drain of the memory cell.
The source of the memory cell is in a floating state, a third voltage is applied to the substrate of the memory cell, and the first and second
And a means for externally applying the third voltage, and means for simultaneously applying these voltages to a desired number of memory cells, and applying the first, second and third voltages to the memory cells. Then, a fourth voltage is applied to the control gate of the memory cell, the drain of the memory cell is made floating, and a fifth voltage is applied to the source of the memory cell,
Applying a sixth voltage to the substrate of the memory cell,
And means for applying the fifth and sixth voltages from the outside, and means for simultaneously applying these voltages to a desired number of memory cells, and the first, second and third voltages are desired. A semiconductor memory device in which the operation of simultaneously applying the same number of memory cells and the operation of simultaneously applying the fourth, fifth, and sixth voltages to a desired number of memory cells are alternately repeated. 6. A semiconductor memory device having a ferroelectric film, comprising a memory cell having a different memory state depending on a polarization direction of the ferroelectric film, wherein the ferroelectric film is polarized with respect to the semiconductor memory device. And a means for selecting all the memory cells so that the voltage applied from the outside is applied to all the memory cells on the chip. Semiconductor memory device. 7. The semiconductor memory device according to claim 6, wherein the voltage applied from the outside is applied to a bonding pad provided in parallel with the output of the internal voltage generating means. 8. The means for applying a voltage applied from the outside to a desired number of memory cells according to claim 6 or 7, wherein a circuit for selecting a desired memory cell from an address signal is provided in the selection circuit. A semiconductor memory device which is means for adding an all-selection signal and generating the all-selection signal from a dedicated bonding pad or from a combination of voltages or phases of signals of other pads.