JP3441154B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory having an array of memory cells in which a ferroelectric material is used as an insulating film of a capacitor for information storage. The present invention relates to a circuit for screening a body membrane).

[0002]

2. Description of the Related Art In a ferroelectric film, electric polarization once generated when an electric field is applied remains even if the electric field is no longer applied, and an electric field having a certain strength or more in a direction opposite to the electric field. Has a characteristic that the direction of polarization is reversed when is applied. Focusing on the polarization characteristics in which the direction of polarization of this dielectric is reversed, a technique has been developed to realize a nonvolatile ferroelectric memory cell by using a ferroelectric as an insulating film of a capacitor for information storage of the memory cell. There is.

FIG. 5 shows an equivalent circuit of a ferroelectric memory cell having a one-transistor / one-capacitor structure. Here, C is a capacitor for storing information (ferroelectric capacitor) using a ferroelectric having a perovskite structure as an interelectrode insulating film, Q is a MOS transistor for charge transfer connected in series to the capacitor, WL is a word line connected to the gate of the MOS transistor, BL is a bit line connected to one end of the MOS transistor, PL is a plate line connected to one end (plate) of the capacitor, and VPL is a plate. It is the line voltage.

FIGS. 6 (a) to 6 (c) and FIGS. 7 (a) to 7 (c) show a write operation of a ferroelectric memory cell having a two-transistor / two-capacitor structure using two memory cells of FIG. In order to explain the principle of read operation, the applied electric field and electric polarization state of the ferroelectric capacitor are shown.

This ferroelectric memory cell has a first transistor Q1 having a gate connected to a word line WL, respectively.
And a second transistor Q2, and a first capacitor C1 and a second capacitor C2 each having a plate line PL connected to a plate, and the first transistor Q1 and the first capacitor C1 are connected in series,
The second transistor Q2 and the second capacitor C2 are connected in series.

Then, one end of each of the first transistor Q1 and the second transistor Q2 is connected to the first bit line B.
It is connected to L1 and the second bit line BL2. The word line WL and the plate line PL are provided in parallel, and the word line WL is supplied with a word line signal from a row decoder (not shown) for the word line, and the plate line PL is supplied.
Is supplied with a plate line voltage VPL from a plate line row decoder (not shown).

In addition, the above-mentioned two bit lines BL1 and BL2
A sense amplifier (not shown) for bit line potential sense amplification, a write circuit (not shown), and a precharge circuit (not shown) are connected to the.

When writing or reading data to or from the ferroelectric memory cell, the potential of the plate line PL of the selected memory cell is changed from 0V → for example, 5V → 0V as shown in FIG. Control the orientation of.

That is, in the write operation, in the initial state, the plate line PL is set to the ground potential Vss (0V) and the two bit lines bit lines BL1 and BL2 are precharged to 0V respectively.

First, as shown in FIG. 6A, the second bit line BL2 is set to 5V, for example, and the word line WL is set to 5V.
When the two transistors Q1 and Q2 are turned on by applying a voltage, a potential difference is generated between both ends of the second capacitor C2 and, for example, downward polarization is generated in the figure, but between both ends of the first capacitor C1. Does not generate a potential difference, so no polarization occurs.

Next, as shown in FIG. 6B, when the plate line PL is set to 5 V, a potential difference is generated across the first capacitor C1 and an upward polarization occurs in the figure. Since there is no potential difference between both ends of the second capacitor C2, the polarization is not inverted. As a result, the two capacitors C1 and C2 are polarized in directions opposite to each other as shown in the figure, and this state corresponds to the write state of data "1" or "0".

Next, as shown in FIG. 6C, the plate line PL is set to 0V and the word line WL is set to 0V to turn off the two transistors Q1 and Q2. In the read operation, the plate line PL is set to 0V in the initial state.
Set to 0 and set each of the two bit lines BL1 and BL2 to 0.
Precharge to V. Here, it is assumed that data is written in the two capacitors C1 and C2 in a state where polarization occurs in the direction as shown in FIG. 7A, for example.

First, as shown in FIG. 7B, when the plate line PL is set to 5V and 5V is applied to the word line WL to turn on the two transistors Q1 and Q2, the second transistor Q1 is turned on. A potential difference is generated between both ends of the capacitor C2 and its polarization direction is reversed, but since no potential difference is generated between both ends of the first capacitor C1, the polarization direction is not reversed. The read potentials from the two capacitors C1 and C2 are sense-amplified by a sense amplifier, and the two bit lines BL1 and BL2 are correspondingly set to 0V and 5V by the output of the sense amplifier. The read data "1" or "0" is discriminated based on.

Next, as shown in FIG. 7C, when the plate line PL is set to 0 V, a potential difference is generated between both ends of the second capacitor C2 and the polarization direction is inverted, but the first Since there is no potential difference between both ends of the capacitor C1, the polarization direction is not reversed.

By the way, when manufacturing a ferroelectric memory having an array of memory cells using the above-mentioned ferroelectric capacitors, the insulating film of the ferroelectric capacitors is screened in a wafer state or a state after packaging. In this case, if the memory cells are accessed so as to be sequentially selected and the above-described write and read operations are repeated for each selected cell, the screening time becomes long and the screening cost becomes high.

[0016]

As described above, in the conventional ferroelectric memory, when the insulating film of the ferroelectric capacitor is screened, the screening time becomes long and the screening cost becomes high. was there.

The present invention has been made to solve the above-mentioned problems, and in the case of screening an insulating film of a ferroelectric capacitor, a semiconductor memory device capable of shortening the screening time and the screening cost. The purpose is to provide.

[0018]

According to the present invention, in a semiconductor memory device having a normal operation mode and a screening mode, a capacitor for information storage using a ferroelectric material for an interelectrode insulating film and a MOS transistor for charge transfer are provided. And a memory cell array in which memory cells connected in series are arranged in a matrix and memory cell MOs of the same row.
A plurality of word lines that are commonly connected to the gates of the S transistors, a plurality of plate lines that are commonly connected to the plates of the capacitors of the memory cells in the same row, and the MOS transistors of the memory cells in the same column. A plurality of bit lines commonly connected to one end, a word line selection circuit that selects a first number of word lines of the plurality of word lines based on an address signal in the normal operation mode, A plate line selection circuit that selects a first number of plate lines of the plurality of plate lines based on an address signal in the normal operation mode and controls the voltage of the plate line; and a normal operation mode in the screening mode. A large number of memory cells are selected at the same time as the memory cells that are selected at the same time, and there is a polarity between both ends of the ferroelectric capacitor insulating film. A pulse voltage mutually inverts and a screening circuit for applying any number of times, the subscription
During the screening mode, the learning circuit
From the first number of word lines out of several word lines
Screen that simultaneously selects a large number of second word lines
A word line selection circuit for a switching mode, and the screen
The first of the plurality of plate lines during
A second number of plate lines greater than the number of plate lines
A first pulse voltage that is selected at the same time and has a predetermined voltage amplitude.
A plate line voltage application circuit that applies pressure any number of times,
In the screening mode, the multiple bit lines are
Selected at a time and in a phase opposite to that of the first pulse voltage described above
A second pulse voltage having a pressure amplitude is applied any number of times
A bit line voltage applying circuit,
The word line selection circuit for the mode is the screening mode.
The first line to which the word line voltage is supplied at the
It is connected to the wiring of No. 1 and works in the screening mode.
One word line voltage application pad to which the word line voltage is applied
And the word line voltage application pad and the second number of wires.
For a plurality of first switches connected between the lead wire and
OS transistor group and the first switch MOS transistor
Second wiring commonly connected to each gate of the transistor group
Connected to this second wiring,
Mode, the first switching MOS transistor group is
One control voltage to which a control voltage for controlling the ON state is applied
A semiconductor memory device having a pressure applying pad .

[0019]

In the screening mode, the screening circuit simultaneously selects a larger number of memory cells than the memory cells selected in the normal mode, and applies a pulse voltage whose polarities are alternately inverted between both ends of the insulating film of the ferroelectric capacitor. Apply any number of times.

As a result, the ferroelectric insulating film of the capacitor can be polarization-inverted any number of times, the screening of the ferroelectric film can be efficiently performed, and the screening time and the screening cost can be reduced. It will be possible.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a part of a ferroelectric memory according to the first embodiment of the present invention. In this ferroelectric memory, MC is a ferroelectric capacitor C for information storage and MO for charge transfer, each of which uses a ferroelectric as an interelectrode insulating film.
These are a plurality of ferroelectric memory cells in which S transistors Q are connected in series, and the memory cells MC are arranged in a matrix to form a memory cell array 10.

WL0, WL1, WL2 ... Are a plurality of word lines P commonly connected to the gates of the transistors Q of the memory cells in the same row in the memory cell array 10.
L0, PL1, PL2 ... Are a plurality of plate lines commonly connected to the plates of the capacitors C of the memory cells of the same row in the memory cell array 10, and BL, / BL are memory cells of the same column in the memory cell array 10. A bit line commonly connected to one end of the transistor. Reference numeral 11 is a word line selection circuit and a plate line selection circuit.

The ferroelectric memory has a normal operation mode (hereinafter referred to as a normal mode) and a screening mode for the insulating film of the ferroelectric capacitor, and further, a memory selected in the screening mode and the normal mode. A screening circuit is provided in which a large number of memory cells (for example, all memory cells) are simultaneously selected from the cells and a pulse voltage whose polarity is alternately inverted is applied between the ends of the insulating film of the ferroelectric capacitor C an arbitrary number of times.

The word line selection circuit and the plate line selection circuit 11 are word line row decoders that select a first number of word lines from the plurality of word lines WL based on an address signal in the normal mode. , The plurality of plate lines PL based on the address signal in the normal mode
A plate line row decoder that selects the first number of plate lines of the selected line and controls the voltage of the plate line.

The screening circuit comprises a word line selection circuit 21 for the screening mode, a plate line voltage application circuit 22 and a bit line voltage application circuit 23. In the screening mode, the plurality of lines (for example, all the lines) are selected. A predetermined voltage level is alternately inverted between the second number of plate lines PL, which is larger than the first number of plate lines PL, and a plurality (for example, all the number) of bit lines BL. The potential difference is applied any number of times.

The word line selection circuit 21 for the screening mode is for simultaneously selecting a second number of word lines, which is larger than the first number of word lines, of the plurality of word lines in the screening mode. is there.

In the present embodiment, the word line selection circuit 21 is connected to the first wiring 211 to which the word line voltage VSTW is supplied in the screening mode and the first wiring 211, and is connected to the first wiring 211 in the screening mode. One word line voltage application pad 212 applied from outside the memory chip, and a plurality of first switch MOSs connected between the word line voltage application pad and the second number of word lines. A transistor 213 group, a second wiring 214 commonly connected to each gate of the first switching MOS transistor group, and a second wiring 214 connected to the second wiring, and the first switching M in the screening mode.
A control voltage application pad 215 to which a control voltage for controlling the OS transistor group to be turned on is applied from the outside of the memory chip.

The plate line voltage application circuit 22 simultaneously selects a second number of plate lines, which is larger than the first number of plate lines, of the plurality of plate lines in the screening mode, and sets a predetermined voltage amplitude. The first pulse voltage having is applied any number of times.

In this embodiment, the plate line voltage applying circuit 22 includes a plurality of second switches connected between the second number of plate lines and the supply node N1 of the first pulse voltage VSTP. Control MOS transistor 221 group and the gates of the second switching MOS transistor 221 group are commonly connected, and a control voltage VGTP for controlling the second switching MOS transistor 221 group to be turned on in the screening mode is supplied. Third wiring 2
And 22.

The bit line voltage application circuit 23 selects the plurality of bit lines at the same time in the screening mode, and arbitrarily selects a second pulse voltage having a predetermined voltage amplitude in a phase opposite to the first pulse voltage. Is a circuit for applying the number of times.

In this embodiment, the bit line voltage application circuit 23 includes a plurality of third switching MOS transistor groups connected between all bit lines and the supply node N2 of the second pulse voltage VSTB. 231 and a gate of the third switching MOS transistor 231 group are connected in common, and a control voltage VGTB for controlling the third switching MOS transistor group to be turned on in the screening mode is supplied. The wiring 232 is provided.

In the screening mode, the third
There is provided one control voltage application pad 24 to which the control voltage VGTP for supplying to the wiring 222 is applied from the outside of the memory chip. Further, in this example, the control voltage VGTP is also used as the control voltage VGTB to be supplied to the fourth wiring 232.

In the screening mode, the first
Of the pulse voltages VSTP and VSTB of opposite phases to the pulse voltage supply node N1 and the second pulse voltage supply node N2 of
For supplying the pulse voltage VSTS from the outside of the memory chip in the screening mode, and is connected between the pulse voltage application pad 25 and the first pulse voltage supply node N1. One inverter circuit 26 and two inverter circuits 271, 272 connected between the pulse voltage application pad 25 and the second pulse voltage supply node are provided.

A sense amplifier 28 for bit line potential sense amplification is connected to the bit lines BL and / BL. FIG. 2 shows an example of the voltage waveform of each part in the screening mode of the ferroelectric memory of FIG.

That is, in the word line selection circuit 21 for the screening mode, the word line voltage VSTW is supplied to the first wiring 211 via the word line voltage application pad 212 and the control voltage application pad is supplied to the second wiring 214. 215
The control voltage VGTW is supplied via the
The group of S transistors 213 is turned on. As a result, the second number of word lines are simultaneously selected, and more memory cells than the memory cells selected in the normal mode are selected.

In the plate line voltage application circuit 22, the control voltage VGTP is supplied to the third wiring 222 through the control voltage application pad 24, so that the switching MOS transistor 221 group is turned on. A second number of plate lines is selected at the same time.

Further, in the bit line voltage applying circuit 23, the control voltage VGTB (= VGTP) is supplied to the fourth wiring 232, so that the group of switching MOS transistors 232 is turned on and all the bit lines are turned on. Are selected at the same time.

Further, the pulse voltage VSTS is applied to the pulse voltage application pad 25, and the first voltage is applied from the inverter circuit 26.
Pulse voltage VSTP of the first pulse voltage supply node N1
The second pulse voltage VSTB having a phase opposite to that of the first pulse voltage is supplied from the inverter circuit 272 to the second pulse voltage supply node N2.

As a result, in the screening mode, a predetermined potential difference at which the voltage level relationship is alternately inverted between the plate lines having a number larger than the number selected in the normal mode and all the bit lines is set to an arbitrary number of times. A ferroelectric capacitor C that is applied, that is, is connected between the plate line and the bit line via a MOS transistor Q.
It is possible to apply a pulse voltage whose polarity is alternately inverted between both ends of the insulating film of 2.

Therefore, the ferroelectric insulating film of the capacitor C can be polarization-inverted any number of times, the ferroelectric film can be efficiently screened, and the screening time and the screening cost can be reduced. Can be planned.

By setting the control voltages VGTP and VGTB above the power supply voltage level, it becomes possible to apply a severer voltage stress to the ferroelectric insulating film than in the normal mode.

FIG. 3 shows a part of the ferroelectric memory according to the second embodiment of the present invention. This ferroelectric memory is
Compared with the ferroelectric memory of FIG. 1, the screening circuit is different, and the other parts are the same, and are therefore assigned the same reference numerals.

In the screening circuit, the word line selection circuit 21 for the screening mode and the first pulse voltage that changes between the predetermined voltage and the ground potential are arbitrarily applied to the second number of plate lines in the screening mode. Of the plate line voltage applying circuit 32 and a second pulse voltage that changes between a predetermined voltage and the ground potential to the plurality of bit lines in the screening mode, and has a phase opposite to that of the first pulse voltage. And a bit line voltage application circuit 33 that applies an arbitrary number of times at a timing having the relationship of.

That is, the plate line voltage applying circuit 32
Is a fifth wiring 321 to which the control voltage VSTP is supplied in the screening mode, and a plurality of second wirings connected between the fifth wiring and the second number of plate lines.
Group of switching MOS transistors 322, and the second
Of the switching MOS transistor group are commonly connected to each other, and switch control of the second switching MOS transistor group is performed in the screening mode.
A sixth wiring 323 to which the pulse voltage VGTP of
The plurality of third switching MOS transistor 324 groups connected between the second number of plate lines and the ground potential Vss and the gates of the third switching MOS transistor group 324 are commonly connected. And a seventh wiring 325 to which a second pulse voltage VGTPS for complementary complementary switching control of the third switching MOS transistor 324 group to the second switching MOS transistor 322 group in the screening mode is supplied. To have.

Further, the bit line voltage applying circuit 33 is
An eighth wiring 331 to which the control voltage VSTB is supplied in the screening mode, a plurality of fourth switching MOS transistor 332 groups connected between the eighth wiring and all bit lines, and A second pulse voltage VGTB which is commonly connected to the respective gates of the fourth switching MOS transistor group and which controls the switching of the fourth switching MOS transistor group in the screening mode.
Wiring 333 to which is supplied, a plurality of fifth switching MOS transistor 334 groups connected between all the bit lines and the ground potential Vss, and this fifth switching MOS transistor group. Are commonly connected to the respective gates of the fifth switch M in the screening mode.
And a tenth wiring 335 to which a first pulse voltage VGTBS is supplied to switch the OS transistor 334 group complementarily to the fourth switching MOS transistor 332 group.

In the screening mode, the fifth
The control voltage VSTP on the wiring 321 of the eighth wiring 3
31 is provided with one control voltage application pad 24 for commonly supplying the control voltage VSTB.

In the screening mode, the sixth
For example, the first pulse voltage VGTP is supplied to the wiring 323, the first pulse voltage VGTBS is supplied to the tenth wiring 335, and the second pulse voltage VGTPS is supplied to the seventh wiring 325. In order to supply the second pulse voltage VGTB to the wiring 333 of the above, one pulse voltage application pad 25 to which the pulse voltage VSTS is applied in the screening mode, the pulse voltage application pad 25 and the sixth voltage
One inverter circuit 26 connected between the wiring 323 and the tenth wiring 335, the pulse voltage application pad 25, the seventh wiring 325, and the ninth wiring 3
Two-stage inverter circuit 271 connected between 33 and
And 272 are provided.

FIG. 4 shows an example of the voltage waveform of each part in the screening mode of the ferroelectric memory of FIG. That is, in the word line selection circuit 21 for the screening mode, as in the first embodiment, the second number of word lines are simultaneously selected, and more memory cells than the memory cells selected in the normal mode are selected. To be done.

In the plate line voltage applying circuit 32, the control voltage SGTP is supplied to the fifth wiring 321 via the control voltage applying pad 24, and in the plate line voltage applying circuit 33, the eighth wiring 331 is supplied. Control voltage VSTB
(= VSTP) is supplied.

Further, the pulse voltage VSTS is applied to the pulse voltage application pad 25, and the inverter circuit 26 outputs the first pulse voltage VSTS.
Of the pulse voltage VGTP (= VGTBS) is supplied to the sixth wiring 323 and the tenth wiring 335, and the inverter circuit 2
The second pulse voltage VGTPS (= VGTB) is supplied from 71 to the seventh wiring 325 and the ninth wiring 333.

As a result, in the screening mode, the number of plate lines larger than the number selected in the normal mode is selected, the predetermined voltage VSTP is applied, and at the same time all bit lines are set to the ground potential. A larger number of plate lines than the number selected in the mode are selected and set to the ground potential, and at the same time, a state in which the predetermined voltage VSTB is applied to all bit lines is alternately repeated. That is, a pulse voltage whose polarity is alternately inverted can be applied any number of times across the insulating film of the ferroelectric capacitor C connected between the plate line and the bit line via the MOS transistor Q. It will be possible.

Therefore, as in the first embodiment, the ferroelectric insulating film of the capacitor C can be polarization-inverted any number of times, the ferroelectric film can be efficiently screened, and the screening time can be increased. And the screening cost can be reduced.

Further, by setting the control voltages VSTP and VSTB above the power supply voltage level, it becomes possible to apply a severer voltage stress to the ferroelectric insulating film than in the normal mode.

In the above embodiment, instead of the word line selection circuit 21 for the screening mode, the row decoder input or the row decoder input for the word line selects the second number of word lines in the screening mode. A control circuit for controlling the output of the row decoder and a pad for applying a control signal for controlling the control circuit may be provided.

In the above embodiment, one transistor
Although an array of ferroelectric memory cells having a one-capacitor structure is shown, the present invention is also applicable to a ferroelectric memory having an array of ferroelectric memory cells having a two-transistor / two-capacitor structure as shown in FIGS. It goes without saying that the invention can be applied.

[0056]

As described above, according to the present invention, it is possible to realize a semiconductor memory device capable of shortening the screening time and the screening cost when the insulating film of the ferroelectric capacitor is screened. You can

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a ferroelectric memory according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing an example of voltage waveforms of respective parts in a screening mode of the ferroelectric memory of FIG.

FIG. 3 is a circuit diagram showing a part of a ferroelectric memory according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram showing an example of voltage waveforms of respective parts in a screening mode of the ferroelectric memory of FIG.

FIG. 5 is a diagram showing an equivalent circuit of a ferroelectric memory cell having a one-transistor / one-capacitor configuration.

6A and 6B show states of an applied electric field and electric polarization of the ferroelectric capacitor for explaining the principle of the write operation of the ferroelectric memory cell having the two-transistor / two-capacitor structure using the two memory cells of FIG. Fig.

FIG. 7 shows a state of an applied electric field and electric polarization of a ferroelectric capacitor for explaining a principle of a read operation of a ferroelectric memory cell having a two-transistor / two-capacitor structure using two memory cells of FIG. Fig.

8 is a waveform chart showing an example of voltage waveforms applied to the plate line PL in the write operation shown in FIG. 6 and the read operation shown in FIG. 7.

[Explanation of symbols]

MC ... Ferroelectric memory cell, C ... Ferroelectric capacitor,
Q ... MOS transistor, WL0, WL1, WL2 ... Word line, PL0, PL1, PL2 ... Plate line, BL,
/ BL ... Bit line, 10 ... Memory cell array, 11 ... Word line selection circuit and plate line selection circuit, 21 ... Screening mode word line selection circuit, 211 ... First
, 212 ... Word line voltage application pad, 213 ... First switch MOS transistor, 214 ... Second wire, 215 ... Control voltage application pad, 22 ... Plate line voltage application circuit, 221 ... For second switch MOS transistor, 222 ... Third wiring, 23 ... Bit line voltage application circuit, 231 ... Third switch MOS transistor, 2
32 ... Fourth wiring, 24 ... Control voltage application pad, 25 ...
Pulse voltage application pads, 26, 271, 272 ... Inverter circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/105 H01L 27/10 444Z (56) References JP-A-2-177194 (JP, A) JP-A-5-75137 ( JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 29/00 G11C 11/22

Claims (6)

(57) [Claims] 1. A semiconductor memory device having a normal operation mode and a screening mode, in which an information storage capacitor using a ferroelectric for an interelectrode insulating film and a charge transfer MOS transistor are connected in series. A memory cell array in which cells are arranged in a matrix, a plurality of word lines that are commonly connected to the gates of the MOS transistors of the memory cells in the same row, and a word line that is commonly connected to the capacitor plates of the memory cells in the same row. The plurality of plate lines, the plurality of bit lines commonly connected to one ends of the MOS transistors of the memory cells in the same column, and the plurality of word lines of the plurality of word lines based on an address signal in the normal operation mode. A word line selection circuit for selecting the first number of word lines, and an address in the normal operation mode. A plate line selection circuit that selects a first number of plate lines from the plurality of plate lines based on a scan signal and controls the voltage of the plate lines; and a plate line selection circuit that is selected in the normal operation mode in the screening mode. simultaneously selecting a plurality of memory cells from the memory cell, comprising a screening circuit for polarity applies any number of times a pulse voltage alternately reversed across the insulating film of the ferroelectric capacitor, said screening circuit, Of the plurality of word lines in the screening mode
A second number of word lines, which is larger than the first number of word lines
Screen mode mode that selects word lines simultaneously
And a plurality of plate lines in the screening mode.
A second book of more than the first number of plate lines of the
Select a number of plate lines at the same time and have a predetermined voltage swing
A plate line electrode that applies a first pulse voltage for any number of times
A voltage applying circuit and the plurality of bit lines in the screening mode.
They are selected at the same time and have a predetermined phase opposite to the first pulse voltage.
Apply a second pulse voltage with voltage amplitude any number of times
And a appropriate bit line voltage application circuit, a word line selection circuit for the screening mode, the word line voltage is supplied to the screening mode
Connected to the first wiring and the screening mode described above.
One word line voltage applied, sometimes word line voltage applied
Pad, the word line voltage application pad, and the second number of words
A plurality of first switching MOSs connected to the line
Transistor group and each gate of the first switching MOS transistor group
A second wiring commonly connected to the second wiring and the second wiring connected to the second wiring.
Sometimes the first switch MOS transistor group is turned on.
One control voltage mark to which a control voltage for controlling the state is applied
A semiconductor memory device having an additional pad . 2. The semiconductor memory device according to claim 1, wherein the screening circuit has a second number of plate lines that is greater than the first number of plate lines of the plurality of plate lines in the screening mode. And a plurality of bit lines, a semiconductor memory device characterized in that a predetermined potential difference at which the voltage level relationship is alternately inverted is applied an arbitrary number of times. 3. The semiconductor memory device according to claim 1 , wherein the plate line voltage application circuit includes a plurality of first line voltage supply circuits connected between the second number of plate lines and a first pulse voltage supply node. MO for 2 switches
A third control transistor, which is commonly connected to the S transistor group and each gate of the second switch MOS transistor group and is supplied with a control voltage for controlling the second switch MOS transistor group to be in an ON state in the screening mode. And a wiring of the semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein the bit line voltage application circuit is for a plurality of second switches connected between all bit lines and a second pulse voltage supply node. The gates of the MOS transistor group and the gates of the second switching MOS transistor group are commonly connected, and are connected to each other in the screening mode.
And a third wiring to which a control voltage for controlling the second switching MOS transistor group to be turned on is supplied. 5. The semiconductor memory device according to claim 1 , wherein the plate line voltage application circuit includes a third wiring to which a control voltage is supplied in the screening mode, the third wiring and the second number. A plurality of second switch MOS transistor groups connected between the second switch MOS transistor group and the second switch MOS transistor group in common in the screening mode. A fourth wiring to which a pulse voltage for controlling the switching MOS transistor group is supplied, and a plurality of third switching MOS transistor groups connected between the second number of plate lines and the ground potential , The third switch MOS transistor group is commonly connected to the respective gates of the third switch MOS transistor group and is used in the screening mode. The semiconductor memory device characterized by pulse voltage complementarily switch control transistor group against MOS transistor groups for the second switch and a fifth wiring which is supplied. 6. The semiconductor memory device according to claim 1 , wherein the bit line voltage application circuit includes a third wiring to which a control voltage is supplied in the screening mode, the third wiring and all the bit lines. A plurality of second switch MOS transistor groups connected between the second switch MOS transistor group and the second switch MOS transistor group, and the second switch MOS transistor groups are commonly connected to the gates of the second switch MOS transistor group. A fourth wiring to which a pulse voltage for switching control of the group is supplied, a plurality of third switching MOS transistor groups connected between all the bit lines and the ground potential, and the third switch Of the third switching MOS transistor group connected in common to each gate of the third switching MOS transistor group in the screening mode. Serial semiconductor memory device, wherein a pulse voltage complementary switch control; and a fifth wiring which is supplied to the second switching MOS transistor group.