JP3397452B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory cell capacitor in a ferroelectric memory having an array of ferroelectric memory cells using a ferroelectric material as an insulating film of a capacitor for information storage. It relates to a circuit for screening for.

[0002]

2. Description of the Related Art In a ferroelectric substance, for example, as shown in the characteristic diagram of FIG. 9, the electric polarization P once generated when an electric field E is applied remains even if the electric field is not applied. It has a hysteresis characteristic that the direction of polarization is reversed when an electric field having a certain level of strength is applied in the opposite direction.

Focusing on the polarization characteristic in which the direction of polarization of the ferroelectric substance is inverted, a technique for realizing a nonvolatile ferroelectric memory cell by using a ferroelectric substance as an insulating film of a capacitor for storing information of the memory cell Is being developed.

FIG. 10 shows an equivalent circuit of a ferroelectric memory cell having a one-transistor / one-capacitor structure. Here, C is a capacitor for storing information (ferroelectric capacitor) using a ferroelectric having a perovskite structure as an interelectrode insulating film, Q is a MOS transistor for charge transfer connected in series to the capacitor, WL is the above MOS
The word line connected to the gate of the transistor, BL
Is a bit line connected to one end of the MOS transistor, PL is a plate line connected to one end (plate) of the capacitor, and VPL is a plate line voltage.

FIG. 11 shows an equivalent circuit of a part of a memory cell array in a ferroelectric memory having the array of ferroelectric memory cells of FIG. BL and / BL indicate a pair of a plurality of bit lines, one end of each transistor Q of a plurality of memory cells MC and one reference cell RMC for generating a read reference potential.
Is connected to one end of the transistor Q. The reference cell has the same circuit configuration as the memory cell,
The capacity of the capacitor is set larger than the capacity of the capacitor of the memory cell.

The word lines WL0, WL1 ... Are commonly connected to the gates of the transistors of the memory cells in the same row, and the RWL0, RWL1 are commonly connected to the gates of the transistors of the reference cells in the same row. It is a reference word line. PL is a plate line commonly connected to the plates of the capacitors of the memory cells in the same row, and RPL is a reference plate line commonly connected to the plates of the capacitors of the reference cells in the same row.

The word lines WL0, WL1 ... And the plate line PL are provided in parallel, and the reference word lines RWL0, RWL1 and the reference plate line RPL are provided in parallel.

The word lines WL0, WL1 ... And the reference word lines RWL0, RWL1 are supplied with a word line signal from a word line selection circuit (not shown), and the plate line PL and the reference plate line RPL are plate line selection circuits. A plate line voltage VPL is supplied from (not shown).

Further, the bit line pair BL, / BL is
A sense amplifier SA for bit line potential sense amplification, a write potential setting circuit (not shown) and a precharge circuit (not shown) are connected.

In writing data in the above ferroelectric memory, the potential of the plate line of the selected memory cell is changed from "L" level to "H" level to "L" level as shown in FIG. , The direction of the dielectric polarization of the capacitor C is controlled according to "1" and "0" of the write data.

When reading data, the potential of the plate line of the selected memory cell MC is changed from "L" level to "H" level to "L" level as shown in FIG. MC data “1”,
Inversion / non-inversion of polarization is controlled according to "0". At the same time, the other bit line / BL paired with the one bit line BL to which the selected memory cell MC is connected.
As shown in FIG. 12, the potential of the reference plate line RPL of the reference cell RMC connected to is changed to “L” level → “H” level → “L” level. In the capacitor of the reference cell RMC, the read logic level of the data of the reference cell is “H” and “L” of the read logic level of the data of the memory cell MC.
The capacity is set so that it is almost halfway between and. In other words, the capacitor of the reference cell RMC has ΔP (change amount of electric polarizability) at the time of polarization reversal and polarization non-reversal in order to distinguish between the polarization reversal / non-reversal of the capacitor of the memory cell MC. The capacitance is set so as to have a ΔP approximately in the middle of the ΔP at the time.

However, in the conventional ferroelectric memory having the array of memory cells using the ferroelectric capacitors as described above, the capacitor insulating film is screened at the time of manufacturing, in a wafer state or a state after packaging. At this time, it is difficult to measure the margin of the read operation of the memory cell and the change amount ΔP of the electric polarizability at the time of polarization reversal of the capacitor.

[0013]

As described above, in the conventional ferroelectric memory, it is possible to measure the margin of the read operation of the ferroelectric memory cell and the change amount ΔP of the electric polarizability during the polarization reversal of the capacitor. There was a problem that it was difficult.

The present invention has been made to solve the above problems, and it provides a margin of a read operation of a ferroelectric memory cell and an amount of change ΔP in electric polarizability at the time of polarization reversal of a capacitor.
It is an object of the present invention to provide a semiconductor memory device capable of easily measuring

[0015]

SUMMARY OF THE INVENTION The present invention is directed to charge transfer.
One MOS transistor and one ferroelectric for information storage
Memory cell and a body capacitor connected in series
And the same circuit configuration as the above memory cell
Generation of read reference potential with large capacitor capacitance
Memory cells in which reference cells for cells are arranged in a matrix
The same as the array in the above memory cell array
A plurality of memory cells in a column
One end of each MOS transistor of several reference cells
And a plurality of bit lines commonly connected to
MOS of memory cells in the same row in a memory cell array
Multiple wires commonly connected to each gate of the transistor
And the same in the memory cell array
For each plate of the ferroelectric capacitors of the row memory cells
Multiple plate wires connected to each other and
M of the reference cells in the same row in the memory cell array
Plural lines commonly connected to each gate of OS transistors
Reference word lines and the above memory cells
Ferroelectric keys of reference cells in the same row in the array
Capacitor plates commonly connected to the plate
The license plate line and the word line depending on the address signal.
Part of the reference line and part of the reference word line
Line selection circuit for supplying a word line signal
And a part of the plate line depending on the address signal.
And select part of the reference plate line to play
A plate line selection circuit for supplying a line voltage,
Sense that amplifies the potential read to the bit line pair
Precharge the amplifier and the bit line pair at a predetermined timing.
A precharge circuit for charging the word line
The selection circuit operates during the read operation in the normal operation mode.
Is a plurality of word lines based on the address signal.
Select some of the word lines to supply the word line selection signal
And at the same time, selected by the selected word line
Memory cell is paired with the connected bit line
Of multiple reference cells connected to the bit line
A certain number of referrals to select a certain number of
Supply word line selection signal
However, during the read operation in the test mode, the address
A part of the plurality of word lines based on the
Select the word line and supply the word line selection signal.
At the same time, the note selected by the word line selected above
To the bit line paired with the bit line to which the resell is connected
Any of the connected reference cells
You can select as many reference wires as you like.
Select a word line to supply a word line selection signal,
The gate line selection circuit is used for the read operation in the normal operation mode.
At the time of operation, the word line selection circuit is selected based on the address signal.
Select the plate line paired with the word line selected by the
Supply the plate line voltage, and at the same time, select the above.
The selected memory cell is connected by the selected word line.
Connected to the bit line paired with the bit line
Select a specific number of reference cells
Select a certain number of reference plate lines
Supply the plate line voltage and read in the test mode.
During the read operation, the word is written based on the address signal.
Play paired with the word line selected by the line selection circuit
Select the source line to supply the plate line voltage and simultaneously
The memory cell selected by the word line selected above.
Connected to the bit line paired with the bit line to which the
Any of the reference cells
Play any number of references as you choose
It is characterized in that the line voltage is selected and the plate line voltage is supplied .

[0016]

The word line selection circuit and the plate line selection circuit arbitrarily control the selected number of reference cells during the read operation in the test mode, or the selected number of capacitors connected to one reference cell. The reference cell capacity variable control function allows the capacity of the reference cell to be arbitrarily changed by controlling the above. As a result, it becomes possible to easily measure the read operation margin of the ferroelectric memory cell and the change amount ΔP of the electric polarizability at the time of polarization reversal of the capacitor.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an equivalent circuit of a part of the memory cell array in the ferroelectric memory according to the first embodiment of the present invention.

In this ferroelectric memory, the ferroelectric memory cells (memory cell MC and reference cell R
MC) are arranged in a matrix to form a memory cell array.

Each of the memory cell MC and the reference cell RMC has a ferroelectric capacitor C for information storage and a MO for charge transfer, each of which uses a ferroelectric material as an interelectrode insulating film.
This is a ferroelectric memory cell in which an S transistor Q is connected in series. In this case, the reference cell RM
Although each C has the same circuit configuration as the memory cell MC, the capacitance of the capacitor C is different from the capacitance of the capacitor C of the memory cell MC as described later.

BL and / BL are transistors Q of the ferroelectric memory cells MC of the same column in the memory cell array.
Is a bit line commonly connected to one end of the pair, and only one pair is representatively shown. Each bit line pair BL, / BL has one end of each transistor Q of a plurality of memory cells MC and a plurality (3 in this example) for generating a read reference potential.
One end of the transistor Q of each reference cell RMC is connected.

WL0, WL1 ... Are word lines commonly connected to the gates of the transistors of the memory cells in the same row in the memory cell array. RWLa, R
WLb ... Are reference word lines commonly connected to the gates of the transistors Q of the reference cells RMC in the same row in the memory cell array.

PL is a plate line commonly connected to the plates of the capacitors C of the memory cells MC in the same row in the memory cell array, and is commonly used in two adjacent rows in this example.

Reference numerals RPL1, RPL2 ... Are reference plate lines commonly connected to the plates of the capacitors C of the reference cells RMC in the same row in the memory cell array, and are commonly used in two adjacent rows in this example. ing.

The word lines WL0, WL1 ... And the plate lines PL are provided in parallel, and the reference word lines RWLa, RWLb ... And the reference plate lines RPL1, RPL2 ... Are provided in parallel.

Reference numeral 11 is a part of the word lines WL0, WL1 ... And reference word lines RWLa, RWLb.
Is a word line selection circuit for selecting a part of the plate line PL and a part of the reference plate lines RPL1, RPL2 ... A plate line selection circuit for supplying VPL.

The bit line pair BL, / BL is
A sense amplifier SA for bit line potential sense amplification, a write potential setting circuit (not shown) and a precharge circuit (not shown) are connected.

The ferroelectric memory has a normal operation mode and a test mode for the insulating film of the ferroelectric capacitor, and the word line selection circuit 11 and the plate line selection circuit 12 have a read operation in the test mode. A reference cell selection number control function capable of arbitrarily controlling the selection number of reference cells RMC is added.

That is, during the read operation in the normal operation mode, the word line selection circuit 11 selects a part of the plurality of word lines based on an address signal to select a word line selection signal. At the same time, the specific number of the plurality of reference cells connected to the bit line paired with the bit line to which the memory cell selected by the selected word line is connected, A specific number of reference word lines are selected so as to supply a word line selection signal, and at the time of a read operation in the test mode, a part of the plurality of word lines is selected based on an address signal. A word line is selected and a word line selection signal is supplied, and at the same time, it is paired with the bit line to which the memory cell selected by the selected word line is connected. A circuit is configured to select an arbitrary number of reference word lines and supply a word line selection signal so as to select an arbitrary number of reference cells connected to the bit line. There is.

In the read operation in the normal operation mode, the plate line selection circuit 12 selects a plate line paired with the word line selected by the word line selection circuit on the basis of an address signal to select a plate line voltage. VPL is supplied, and at the same time, a specific number of a plurality of reference cells connected to the bit line paired with the bit line to which the memory cell selected by the selected word line is connected. Select a specific number of reference plate lines to select the plate line voltage VPL
Is supplied, during the read operation in the test mode,
A plate line paired with the word line selected by the word line selection circuit is selected based on an address signal to supply a plate line voltage VPL, and at the same time, a memory cell selected by the selected word line. The plate line voltage VPL is selected by selecting an arbitrary number of reference plate lines so as to select an arbitrary number of the plurality of reference cells connected to the bit line paired with The circuit is configured to supply

In the above ferroelectric memory, the capacitance of each reference cell RMC is equal to the memory cell M.
It is set to have a value larger than the capacitor capacity of C when the polarization is not inverted and a value that is a multiple (not limited to an integral multiple) of ΔP when the polarization of the memory cell MC is not inverted.

Then, the word line selection circuit 11 and the plate line selection circuit 12 have a variable reference cell capacity control function that makes the capacity of the reference cell RMC different between the read operation in the normal operation mode and the read operation in the test mode. And a reference cell capacity variable control function capable of arbitrarily changing the capacity of the reference cell by arbitrarily controlling the selected number of reference cells during the read operation in the test mode. In this case, in order to change the capacity of the reference cells, control is performed so as to change the selected number of the reference cells RMC, and one specific example thereof is
The non-selected reference cell word line RWLi may be fixed to 0 V (Vss) using a detection signal from a detection circuit (not shown) for detecting that the test mode has been entered.

FIG. 2 shows the polarizability change amount ΔP obtained when the number of selected reference cells is changed and the polarizability change amount ΔP obtained when the data of the selected memory cell is “1” or “0”. It is a characteristic view which shows an example of a magnitude relationship.

From the characteristic diagram of FIG. 2, if two reference cells are selected, the read logic level of the data of the reference cell is approximately halfway between "H" and "L" of the read logic level of the data of the memory cell. It turns out that it can be set to. That is, if two reference cells are selected as described above, the overall capacitor capacitance of the selected reference cell is approximately equal to ΔP of both capacitors at the time of polarization inversion / non-inversion of the capacitors of the selected memory cell. It can be seen that it can be set so as to have an intermediate (not necessarily almost in the middle) ΔP, and it is possible to distinguish between the polarization inversion and the polarization non-inversion of the capacitor of the selected memory cell. However, as described above, when the two reference cells are selected, the total capacitance of the capacitors is the same as that of the polarization inversion of the capacitors of the selected memory cells.
It is not necessary to set it so that ΔP of both when polarization is not reversed is almost in the middle.

On the other hand, when one reference cell is selected, the capacitance of the capacitor of the selected reference cell is set so that the data read logic level of the reference cell is closer to the “L” level than the intermediate level. You can see that it can be set to. Further, it is understood that when three reference cells are selected, the capacitor capacitance of the selected reference cells can be set so that the read logic level of the reference cell data is closer to the “H” level than the intermediate level.

Therefore, during the read operation in the normal operation mode, a specific number (two in this example) of reference cells are selected as described above, and during the read operation in the test mode, the selected number of reference cells is arbitrary. It is possible to arbitrarily change the capacitance of the reference cell by controlling the above.

This makes it possible to easily measure the margin of the read operation of the ferroelectric memory cell and the change amount ΔP of the electric polarizability at the time of polarization reversal of the capacitor. Here, the operation of writing data to the selected memory cell in the ferroelectric memory will be described with reference to FIG.
Description will be made with reference to FIGS. 4A to 4C and FIGS.

When writing data, the potential of the plate line of the selected memory cell is changed from "L" level (0V) to "H" level (for example, 5V power supply potential) to "L" as shown in FIG. The direction of the dielectric polarization is controlled by changing the level.

FIGS. 3A to 3C show the applied electric field and the electric polarization state of the capacitor of the selected memory cell in order to explain the writing of data "1". That is, in the initial state, the plate line PL is set to 0V and the bit line B
Precharge L and / BL to 0V respectively. Next, as shown in FIG. 3A, the selected bit line BL is set to 5V, for example, and 5V is applied to the selected word line WL to turn on the transistor. As a result, a potential difference is generated between both ends of the capacitor C, and, for example, downward polarization in the figure is generated, and the remnant polarization point of the memory cell is the point C in the hysteresis characteristic.

Next, as shown in FIG. 3 (b), when the plate line PL is set to 5V, no potential difference is generated between both ends of the capacitor C, so that the polarization does not reverse and the residual in the hysteresis characteristic remains. The polarization point moves from point C to point D.

Next, as shown in FIG. 3C, the plate line PL is set to 0V and the word line WL is set to 0V to turn off the transistor (return to the initial state). This state corresponds to the write state of data "1".

FIGS. 4A to 4C show the applied electric field of the capacitor of the selected memory cell and the state of electric polarization in order to explain the principle of the data "0" write operation. That is, in the initial state, the plate line PL is set to 0V and the bit lines BL and / BL are precharged to 0V. Next, as shown in FIG. 4A, the selected bit line BL is left at 0V and the selected word line WL is set to 5V.
V is applied to turn on the transistor. This time,
Since there is no potential difference between both ends of the capacitor C, no polarization occurs.

Next, as shown in FIG. 4 (b), when the plate line PL is set to 5V, a potential difference is generated between both ends of the capacitor C, which is upward in the figure contrary to the time of writing "1". Polarization occurs, and the remnant polarization point of the memory cell is the point A in the hysteresis characteristic.

Next, as shown in FIG. 4C, the plate line PL is set to 0V and the word line WL is set to 0V to turn off the transistor (return to the initial state). Since there is no potential difference between them, the remanent polarization point in the hysteresis characteristic moves from point A to point B without reversing the polarization. This state is data “0”
It corresponds to the writing state of.

Next, the data read operation in the normal operation mode will be described with reference to FIGS. 5A to 5C and FIG.
A description will be given with reference to (a) to (c). When reading data, the potential VPL of the plate line of the selected memory cell and the potential VPL of the plate line of the reference cell
PL is changed from "L" level to "H" level to "L" level as shown in FIG.

FIGS. 5A to 5C show the memory when the data "1" is written (the state of the remanent polarization point D in the hysteresis characteristic) is selected and the data "1" is read. The electric field applied and electric polarization of the cell capacitor and the reference cell capacitor are shown.

In the initial state, as shown in FIG.
The potential VPL of the plate line and the potential VPL of the reference plate line are set to 0V, and the bit lines BL and / BL are precharged to 0V respectively.

Next, as shown in FIG. 5B, the potential VPL of the selected plate line and the potential VPL of the reference plate line are set to 5 V, respectively, and the selected word line and the reference word line are set. 5 for each
V is applied to turn on each transistor of the selected memory cell and reference cell.

As a result, an electric field in the direction opposite to the polarization direction is applied across the capacitor C of the selected memory cell, the polarization direction of the memory cell is reversed, and the polarization point becomes the hysteresis characteristic. The remnant polarization point D moves to point A. On the other hand, since an electric field in the same direction as the polarization direction is applied across the capacitor C of the reference cell, the polarization of the reference cell is not inverted.

In this case, currents flow in the memory cell and the reference cell, respectively, and potential changes occur in the corresponding bit lines BL, / BL, but the polarization of the capacitor C of the memory cell is inverted as described above, so the memory The current flowing through the cell is larger than the current flowing through the reference cell, the potential change ΔVBL (1) of the bit line BL is larger than the potential change ΔV / BL of the bit line / BL, and a small amount is present between the bit line pair BL, / BL. A potential difference occurs. The minute potential difference is sense-amplified by the sense amplifier SA, and the output (read data "1") of the sense amplifier SA sets the bit lines BL and / BL to 5V and 0V correspondingly.

As a result, no electric field is applied across the capacitor C of the memory cell, and the polarization point of the memory cell moves from the point A in the hysteresis characteristic to the remnant polarization point B.

Next, as shown in FIG. 5C, when the potential VPL of the plate line and the potential VPL of the plate line of the reference cell are set to 0V, the capacitor C of the memory cell is set.
An electric field in the direction opposite to the direction of polarization of the memory cell is applied across both ends of the memory cell, the direction of polarization of the memory cell is reversed, and the polarization point moves from the residual polarization point B to the point C in the hysteresis characteristic. .

Then, again, as shown in FIG.
When the bit lines BL and / BL are precharged to 0 V, no electric field is applied across the capacitor C of the memory cell, and the polarization point of the memory cell changes from point C in the hysteresis characteristic to remnant polarization point D. Moving.

After that, the word line and the reference word line are set to 0 V to turn off the memory cell transistor and the reference cell transistor to return to the initial state.

Contrary to the read operation of the data "1" described above, the "" when the selected memory cell is in the state of the remanent polarization point B in the hysteresis characteristic (write state of data "0"). The 0 "read operation will be described.

FIGS. 6A to 6C show the memory when the data "0" is written (the remnant polarization point B in the hysteresis characteristic) is selected and the data "0" is read. The electric field applied and electric polarization of the cell capacitor and the reference cell capacitor are shown.

In the initial state, as shown in FIG.
The potential VPL of the plate line and the potential VPL of the reference plate line are set to 0V, and the bit lines BL and / BL are precharged to 0V respectively.

Next, as shown in FIG. 6B, the potential VPL of the selected plate line and the potential VPL of the reference plate line are set to 5V, respectively, and the selected word line and the reference word line are set. 5 for each
V is applied to turn on each transistor of the selected memory cell and reference cell.

As a result, an electric field in the same direction as the polarization direction of the memory cell is applied across the capacitor C of the selected memory cell, so that the polarization of the memory cell is not inverted and the polarization point thereof is not reversed. Moves from the remanent polarization point B to the point A in the hysteresis characteristic. Similarly, since the electric field in the same direction as the polarization of the memory cell is applied across the capacitor C of the reference cell, the polarization of the reference cell is not inverted.

In this case, currents flow in the memory cell and the reference cell, respectively, and potential changes occur in the corresponding bit lines BL and / BL. However, as described above, the capacitance of the reference cell is greater than that of the memory cell. Since the current flowing in the reference cell is larger than the current flowing in the memory cell, the potential change ΔVBL (0) of the bit line BL is smaller than the potential change ΔV / BL of the bit line / BL, Pair B
A minute potential difference is generated between L and / BL. The minute potential difference is sense-amplified by the sense amplifier SA, and the output (read data "0") of the sense amplifier SA sets the bit lines BL, / BL to 0V, 5V correspondingly.

As a result, an electric field in the same direction as the polarization direction is applied across the capacitor C of the memory cell, and the polarization point of the memory cell remains the point A in the hysteresis characteristic.

Then, as shown in FIG. 6C, the potential VPL of the plate line and the potential VPL of the reference plate line.
When PL is set to 0 V, no electric field is applied across the capacitor C of the memory cell, and the polarization point of the memory cell moves from point A in the hysteresis characteristic to remnant polarization point B.

Then, again, as shown in FIG.
When the bit lines BL and / BL are precharged to 0 V, no electric field is applied across the capacitor C of the memory cell, and the polarization point of the memory cell remains the remnant polarization point B in the hysteresis characteristic.

After that, the word line and the reference word line are set to 0 V to turn off the memory cell transistor and the reference cell transistor to return to the initial state.

FIG. 7 shows a part of the ferroelectric memory according to the second embodiment of the present invention. This ferroelectric memory is
Compared to the ferroelectric memory of FIG. 1, the number of reference cells connected and the circuit configuration, the connection of reference word lines and reference plate lines to this reference cell, and part of the function of the plate line selection circuit are different, and others are Since they are the same, the same reference numerals are given.

That is, in the reference cell, one end of each of a plurality (three in this example) of ferroelectric capacitors C is provided at the other end of one MOS transistor Q whose one end is connected to the bit line BL or / BL. Are connected in common and are connected to the bit lines BL and / BL one by one. The reference word line RWLa is connected to the gate of the MOS transistor of the reference cell connected to the bit line BL, and the reference word line is connected to the gate of the MOS transistor of the reference cell connected to the bit line / BL. RWLb is connected, and the reference plate lines RPL1 to RPL3 are connected to the other ends of the three ferroelectric capacitors.

In this case, the reference word line R
WLa and RWLb are commonly connected to the gates of the MOS transistors of the reference cells in the same row in the memory cell array. The reference plate lines RPL1 to RPL3 are commonly connected to the plates of the plurality of ferroelectric capacitors of the reference cells in the same row in the memory cell array.

The capacitance of each capacitor of the reference cell is larger than the capacitance of the memory cell when polarization is not inverted, and Δ when the polarization of the memory cell is not inverted.
It is set to have a value that is a multiple of P (not limited to an integer multiple).

The word line selection circuit 71 and the plate line selection circuit 72 have a reference cell capacity variable control function that makes the capacity of the reference cell different between the read operation in the normal operation mode and the read operation in the test mode. , Read operation in test mode,
It has a reference cell capacity variable control function that enables the capacity of the reference cell to be arbitrarily changed by arbitrarily controlling the number of selected reference cells. In this case, in order to change the capacitance of the reference cell, the number of selected capacitors of the reference cell is controlled so as to be changed, so that the characteristics shown in FIG. 2 are obtained.

That is, the plate line selection circuit 71 is connected to the memory cell selected by the word line and the plate line selected based on the address signal during the read operation in the normal operation mode of the ferroelectric memory. A reference word line connected to a bit line paired with a corresponding bit line, and a reference word line is selected so that a plurality of ferroelectric capacitors of the one reference cell are selected. A specific number of reference plate lines are selected from the plurality of reference plate lines RPL1 to RPL3 connected to, and the voltage of the reference plate lines is controlled.

The plate line selection circuit 72 is connected to the word line selected based on the address signal and the memory cell selected by the plate line during the read operation in the test mode of the ferroelectric memory. The reference word line is selected so that one reference cell connected to the bit line paired with the existing bit line is selected, and a plurality of ferroelectric capacitors of the one reference cell are selected. Select an arbitrary number of reference plate lines from the plurality of connected reference plate lines RPL1 to RPL3,
The voltage of this reference plate line is controlled.

The operation of the ferroelectric memory of the second embodiment is similar to the operation of the ferroelectric memory of the first embodiment described above, and the reference cell capacitance is read in the normal operation mode and in the test mode. By having a reference cell capacitance variable control function that is different depending on the read operation in, and by arbitrarily controlling the selected number of capacitors connected to one reference cell during the read operation in the test mode, It has a reference cell capacity variable control function that allows the capacity of the reference cell to be changed arbitrarily.

Therefore, as in the first embodiment, it is possible to easily measure the margin of the read operation of the ferroelectric memory cell and the change amount ΔP of the electric polarizability at the time of polarization reversal of the capacitor.

FIG. 8 shows a plate line selection circuit 72 shown in FIG.
3 is a circuit diagram showing a specific example of a capacitor selection number control circuit for controlling the selection number of capacitors connected to one reference cell in FIG.

This capacitor selection number control circuit has a two-input NAND circuit 81i (i = 1) in the same number as the number of capacitors connected to one reference cell (three in this example).
~ 3) are provided.

Each of the NAND circuits 81i receives a pulse signal a having a phase opposite to that of the plate line voltage VPL as a first input, and a control signal bi (i = i = i) for designating whether to select a capacitor as a second input. 1 to 3) (“1” level when selectable, “0” level when not selectable) correspondingly input, and the output signal corresponds to the reference plate line RPLi (i = 1 to 3) Is supplied to.

In the above-mentioned capacitor selection number control circuit, since the NAND circuit 81i corresponding to the capacitor to be selected during the read operation is given the "1" level as the control signal bi, the output signal obtained by inverting the pulse signal a is output. The plate line voltage VPL is supplied to the corresponding reference plate line RPLi.

On the other hand, the NAND circuit 81i corresponding to the capacitor which is not selected in the read operation is
Since the "0" level is given as the control signal bi,
The "1" level (Vcc) is output and supplied to the corresponding reference plate line RPLi so that the polarization of the capacitor not selected is not inverted.

In the above embodiment, one transistor
Although an array of ferroelectric memory cells having a one-capacitor structure is shown, it goes without saying that the present invention can be applied to a ferroelectric memory having an array of ferroelectric memory cells having a two-transistor / two-capacitor structure.

[0079]

As described above, according to the semiconductor memory device of the present invention, when the insulating film of the ferroelectric capacitor is screened, the margin of the read operation of the ferroelectric memory cell and the polarization reversal of the capacitor. It is possible to easily measure the change amount ΔP of the electric polarizability at the time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a ferroelectric memory according to a first embodiment of the present invention.

FIG. 2 shows polarizability change amount ΔP and data of selected memory cells of “1” and “0” obtained when the number of selected reference cells is changed during the read operation in the test mode of the ferroelectric memory of FIG. The characteristic view showing an example of the magnitude relationship with the polarizability change amount ΔP obtained in the case of “”.

FIG. 3 is a diagram showing a state of an applied electric field and electric polarization of a ferroelectric capacitor for explaining a principle of writing data “1” to a selected memory cell in FIG. 1.

FIG. 4 is a diagram showing an applied electric field and a state of electric polarization of a ferroelectric capacitor for explaining a principle of a data “0” write operation to a selected memory cell in FIG. 1.

5 is a diagram showing a state of an applied electric field and electric polarization of a ferroelectric capacitor in order to explain a principle of a read operation of data "1" with respect to a selected memory cell in FIG.

FIG. 6 is a diagram showing a state of an applied electric field and electric polarization of a ferroelectric capacitor for explaining a principle of a data “0” read operation for a selected memory cell in FIG. 1.

FIG. 7 is a circuit diagram showing a part of a ferroelectric memory according to a second embodiment of the present invention.

8 is a circuit diagram showing a specific example of a capacitor selection number control circuit provided in the plate line selection circuit in FIG.

FIG. 9 is a characteristic diagram showing a relationship between an electric field E applied to a ferroelectric film and an electric polarization P.

FIG. 10 is an equivalent circuit diagram showing a ferroelectric memory cell having a one-transistor / one-capacitor configuration.

11 is an equivalent circuit diagram showing a part of a memory cell array in a conventional ferroelectric memory having an array of ferroelectric memory cells of FIG.

FIG. 12 is a plan view of the plate line PL in the write operation and the read operation for the selected memory cell in FIG.
FIG. 3 is a waveform chart showing an example of a voltage waveform applied to the circuit.

[Explanation of symbols]

MC ... Memory cell, RMC ... Reference cell, C ... Ferroelectric capacitor, Q ... MOS transistor, WL0,
WL1 ... Word line, RWLa to RWLf ... Reference word line, PL ... Plate line, RPL1 to RPL3 ...
Reference plate line, BL, / BL ... bit line,
11, 71 ... Word line selection circuit, 12, 72 ... Plate line selection circuit.

Front page continuation (72) Inventor Mitsuru Shimizu 25-1 Ekimae Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Stock Association In-house (72) Toshio Tanaka Komukai-shishiba, Saiwai-ku, Kawasaki-shi, Kanagawa 1st Co., Ltd. Toshiba Research and Development Center (56) References JP-A 63-201998 (JP, A) JP-A 59-198594 (JP, A) JP-A 4-90189 (JP, A) (58) Fields investigated ( Int.Cl. ⁷ , DB name) G11C 11/22 G11C 11/40-11/4099 G11C 29/00

Claims (2)

(57) [Claims] 1. A semiconductor memory device having a normal operation mode and a test mode, wherein a memory cell in which one MOS transistor for charge transfer and one ferroelectric capacitor for information storage are connected in series, and A memory cell array in which reference cells for generating a read reference potential having the same circuit configuration as the memory cell and having a larger capacitance than the memory cell are arranged in a matrix, and a plurality of memory cells in the same column in the memory cell array, respectively. Of the MOS transistors and the MOS transistors of the plurality of reference cells, which are commonly connected to the respective ends, and the gates of the MOS transistors of the memory cells of the same row in the memory cell array. Multiple word lines and the above A plurality of plate lines commonly connected to the respective plates of the ferroelectric capacitors of the memory cells of the same row in the re-cell array and the gates of the MOS transistors of the reference cells of the same row of the memory cell array, respectively. A plurality of reference word lines, a plurality of reference plate lines that are commonly connected to the plates of the ferroelectric capacitors of the reference cells in the same row in the memory cell array, and the word lines of the word lines according to an address signal. A word line selection circuit for selecting a part and a part of a reference word line to supply a word line signal, and a part of the plate line and a part of the reference plate line according to the address signal. To select the plate line voltage to supply the plate line voltage. If, comprising a sense amplifier for sensing amplifies the potential read out to the bit line pair, and a precharge circuit for precharging the bit line pair at a predetermined timing, said word line selection circuit, the normal operation Address during read operation in mode
Based on a signal, some word lines of the plurality of word lines are
Supplying word line selection signal by selecting the lead wire, the as this
Sometimes the memory selected by the above selected word line
Connect to the bit line paired with the bit line to which the cell is connected.
A specific one of the reference cells
A specific number of reference work
Select a read line to supply a word line select signal , and read the address signal during the read operation in the test mode.
Of some of the word lines based on the
At the same time as supplying the word line selection signal
The memory cell selected by the word line selected above.
Connected to the bit line paired with the bit line to which the
Any of the reference cells
Any number of reference words to select the number
A line is selected and a word line selection signal is supplied, and the plate line selection circuit selects an address during a read operation in the normal operation mode.
Selected by the word line selection circuit based on a signal
Select the plate line paired with the word line to select the plate line
Supply pressure to the selected word line at the same time.
With the bit line to which the selected memory cell is connected
Multiple references connected to a pair of bit lines
A specific number of cells to select a specific number of cells
Select the reference plate line for the plate line voltage
The address signal is supplied during read operation in the test mode.
Signal selected by the word line selection circuit based on the
Select the plate line paired with the
Of the selected word line at the same time.
The bit line to which the selected memory cell is connected.
References connected to the bit lines that make up
Any number of cells can be selected to select any number of cells.
Select the reference plate line and set the plate line voltage
A semiconductor memory device characterized by being supplied . 2. In a semiconductor memory device having a normal operation mode and a test mode, a memory cell and a charge in which one MOS transistor for charge transfer and one ferroelectric capacitor for information storage are connected in series. A memory cell array in which reference cells for generating a read reference potential, in which one end of each of a plurality of ferroelectric capacitors for information storage are connected to one transfer MOS transistor, are arranged in a matrix, and the memory cell array, respectively. , A plurality of bit lines commonly connected to one end of a plurality of memory cell MOS transistors and one reference cell MOS transistor in the same column, and MOS transistors of memory cells in the same row in the memory cell array, respectively. A plurality of word lines commonly connected to each gate of A plurality of plate lines that are commonly connected to the respective plates of the ferroelectric capacitors of the memory cells in the same row in the memory cell array, and the gates of the MOS transistors of the reference cells in the same row in the memory cell array, respectively. A plurality of reference word lines connected to each other, and a plurality of reference plate lines commonly connected to each plate of the plurality of ferroelectric capacitors of the reference cells in the same row in the memory cell array. A word line selection circuit for supplying a word line signal by selecting a part of the word line and a part of the reference word line according to an address signal, and one of the plate lines according to the address signal. And part of the reference plate line to select the plate line voltage. Comprising a plate line selection circuit for supplying, a sense amplifier for amplifying a sense the potential read out to the bit line pair, and a precharge circuit for precharging the bit line pair at a predetermined timing, the word The line selection circuit operates during the read operation in the normal operation mode and the test operation.
Based on the address signal during a read operation in
Select some of the word lines from the above
To supply the word line selection signal, and at the same time, select the above.
The selected memory cell is connected by the selected word line.
Connected to the bit line paired with the bit line
Use one reference word line to select one
The selected word line selection signal is supplied to the plate line selection circuit, and the plate line selection circuit selects the address during the read operation in the normal operation mode.
Selected by the word line selection circuit based on a signal
Select the plate line paired with the word line to select the plate line
Supply pressure to the selected word line at the same time.
With the bit line to which the selected memory cell is connected
One reference connected to a pair of bit lines
The cells are connected to correspond to multiple ferroelectric capacitors.
Out of multiple reference plate lines
Select the number of reference plate lines and plate
Supply the line voltage and read the address signal during the read operation in the test mode.
Signal selected by the word line selection circuit based on the
Select the plate line paired with the
Of the selected word line at the same time.
The bit line to which the selected memory cell is connected.
One reference cell connected to the bit line
Corresponding to multiple ferroelectric capacitors
Any of the multiple reference plate lines
Select the number of reference plate lines and select the plate line
A semiconductor memory device characterized by supplying a voltage .