JPH0660650A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the region for forming a column gate driver and to reduce area loss thus utilizing the surface of chip effectively in a semiconductor storage device where the pairs of data bus line shared by a plurality of pairs of bit lines connected with storage cells are separated into pairs of read data buse line and write data bus line being multiplexed. CONSTITUTION:Vth of nMOS transistors 61, 63, 65, 67 in read column gates 58, 59 is set at 0.1V, whereas Vth of nMOS transistors 91-94 in write column gate is set at 1.5V=1/2VCC. At the time of read operation, column selection signal is set at 1.5V whereas it is set at 3V = VCC at the time of write operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention separates a data bus line pair shared by a plurality of bit line pairs to which memory cells are connected into a read data bus line pair and a write data bus line pair. The present invention relates to a semiconductor memory device in which these are multiplexed.

[0002]

2. Description of the Related Art Conventionally, a data bus line pair shared by a plurality of bit line pairs to which memory cells are connected is separated into a read data bus line pair and a write data bus line pair, and each of these is separated. A dual semiconductor memory device, such as a DRAM (dynamic random access memory)
As y), there is known one whose main part is shown in FIG.

In the figure, 1 is a memory cell array section,
A, 1B, 1C and 1D are memory cells, WL1 and WLn are word lines, and BL1, / BL1, BL2 and / BL2 are bit lines.

Further, 2 is a sense amplifier provided corresponding to the bit line pair BL1, / BL1 and 3 is a bit line pair BL.
2, sense amplifiers provided corresponding to / BL2, 4 to 7 are pMOS transistors, and 8 to 11 are nMO.
The S transistor, PSA, and NSA are sense amplifier activation signal lines.

In addition, RDB1, / RDB1 and RDB
2 and / RDB2 are paired read data bus lines, WDB1, / WDB1 and WDB2, / WDB, respectively.
Reference numerals 2 are write data bus lines that make a pair, respectively.

Further, 12 is a bit line pair BL1, / BL1
Corresponding to the read column gate, 13 is a read column gate provided corresponding to the bit line pair BL2, / BL2, 14 to 21 are nMOS transistors, and 22 is a grounded wiring. .

Reference numeral 23 is a bit line pair BL1, / BL1
Column gates for writing provided corresponding to the bit lines, 24 is a column gate for writing provided corresponding to the bit line pair BL2, / BL2, and 25 to 28 are nMOS transistors.

A column decoder 29 decodes a column address signal to select a column.
0, /CA0.../CA9 are column address signals, 3
Reference numeral 0 is a NAND circuit for selecting the read column gates 12 and 13 and the write column gates 23 and 24.

Further, 31 is a read column selection signal RC
A read column gate driver that outputs L to drive the read column gates 12 and 13, and a write column gate driver 32 that outputs a write column selection signal WCL to drive the write column gates 23 and 24. 33 and 34 are pMOS transistors and 3
Reference numerals 5 and 36 are nMOS transistors.

RCD is a read column selection signal R.
A signal supplied to the source of the pMOS transistor forming the read column gate driver to generate CL, and WCD a pMOS forming the write column gate driver to generate the write column selection signal WCL. This signal is supplied to the source of the transistor.

In the conventional DRAM configured as described above, the stored information of the memory cell connected to the word line selected by the row decoder (not shown) for decoding the row address signal is read to the bit line at the time of reading. Transmitted.

Thereafter, the sense amplifier activation signal line PSA is set to the power supply voltage VCC by the sense amplifier activation circuit (not shown), and the sense amplifier activation signal line NS is set.
A is set to the ground voltage, all sense amplifiers connected to the sense amplifier activation circuit are activated, and the stored information transmitted to the bit line is amplified.

Here, for example, the read column gate 1
When 2 and 13 are selected, the column decoder 29 is supplied with column address signals CA0, / CA0 ... / CA9 for selecting the read column gates 12 and 13, and the output of the NAND circuit 30 is "L". It is said that

As a result, the pMOS transistor 33 of the column gate driver 31 is ON, the nMOS transistor 35 is OFF, and the pMO of the column gate driver 32 is pMO.
S transistor 34 = ON, nMOS transistor 36
= OFF.

Further, in this case, the signal RCD = “H”, the signal WCD = “L”, and the read column selection signal RC.
L = “H”, write column selection signal WCL = “L”.

Here, the read column gates 12 and 13 are provided.
NMOS transistors 15, 17, 19, 21 = 0
N, nMOS transistors 25, 26, 27, 28 of write column gates 23, 24 are turned off.

As a result, in the read column gate 12, the information of the bit line pair BL1 and / BL1 is combined with the nMOS transistors 14 and 16 connected in series with the nMOS transistors 15 and 17 to read data bus line pair R.
It is transmitted to DB1 and / RDB1 and is read via a read amplifier (not shown).

In the read column gate 13, n
NM connected in series with MOS transistors 19 and 21
Bit line pair BL coupled with OS transistors 18 and 20
2, information of / BL2 is read data bus line pair RDB
2, / RDB2, which is read out via a read amplifier (not shown).

On the other hand, at the time of writing, two input data are written as complementary signals by the write amplifier (not shown), and the write data bus line pair WDB1, / WDB1, /
WDB1 and write data bus line pair WDB2, / WD
It is transmitted to B2.

Here, for example, the write column gate 2
When 3, 24 are selected, column address signals CA0, / CA0 ... / CA9 for selecting the write column gates 23, 24 are supplied to the column decoder 29, and the output of the NAND circuit 30 is "L". It is said that

As a result, the pMOS transistor 33 of the column gate driver 31 is ON, the nMOS transistor 35 is OFF, and the pMO of the column gate driver 32 is pMO.
S transistor 34 = ON, nMOS transistor 36
= OFF.

In this case, the signal RCD = “L”, the signal WCD = “H”, and the read column selection signal RC.
L = “L” and the write column selection signal WCL = “H”.

Here, the read column gates 12 and 13 are provided.
NMOS transistors 15, 17, 19, 21 = OF
F, and the nMOS of the write column gates 23 and 24
The transistors 25, 26, 27, 28 are turned on.

As a result, bit lines BL1, / BL1, B
L2 and / BL2 are nMOS transistors 25 and
Write data bus line WDB via 26, 27 and 28
1, / WDB1, WDB2, / WDB2 are connected to write data to the selected memory cell.

In this DRAM, since the data bus line pair is separated into the read data bus line pair and the write data bus line pair, the write column selection signal WCL is set to "H" in the write mode. In this case, even if the read column selection signal RCL is "H", accurate writing can be performed, and the speed can be increased.

By the way, in the DRAM in which the data bus line pair is divided into the read data bus line pair and the write data bus line pair as in this example, it is assumed that the read data bus line pair and the write data are temporarily stored. If the bus line pair is not duplicated, it is necessary to provide one read column gate driver and one write column gate driver within the width of one column (within the formation width of each sense amplifier).
In this case, the arrangement pitch of the sense amplifiers has to be increased, and high integration cannot be achieved.

In this regard, in the DRAM shown in FIG. 18, since the read data bus line pair and the write data bus line pair are duplicated, one read column gate driver is provided within one column width. Or, it is sufficient to provide only one column gate driver for writing.

That is, for example, it is sufficient to provide the read column gate driver 31 within the formation width of the sense amplifier 2 and the write column gate driver 32 within the formation width of the sense amplifier 3.

Therefore, the DRAM shown in FIG. 18 can be highly integrated as compared with the DRAM in which the read data bus line pair and the write data bus line pair are not duplicated.

[0030]

As described above, in the DRAM shown in FIG. 18, the read data bus line pair and the write data bus line pair are duplicated to achieve high integration. However, one column gate driver is used here, for example, read column gates 12 and 13 and write column gates 23 and 24.
Area 37 provided for forming a column gate driver if it can be driven.
Can be made smaller, the area loss can be reduced, and the chip surface can be effectively used.

Furthermore, for example, the NAND circuit 30
Therefore, if the two read column gates 12 and 13 and the write column gates 23 and 24 can be driven, the column gate drivers 31 and 32 are unnecessary and the column gate driver is formed. It is possible to eliminate the area 37 provided on the chip, further reduce the area loss, and use the chip surface more effectively.

In view of the above point, the present invention reduces the area for forming the column gate driver, reduces the area loss, and enables the chip surface to be effectively utilized, and It is an object of the present invention to provide a semiconductor memory device in which a region for forming a column gate driver is eliminated, an area loss is further reduced, and a chip surface can be used more effectively.

[0033]

FIG. 1 is a circuit diagram showing the principle of the first invention in the present invention. In FIG. 1, 38 ₁ , 38 ₂ , ...
.. 38 _{mn + n} are bit line pairs formed by connecting memory cells, 39 ₁ , 39 ₂ ... 39 _n are read data bus line pairs, 40 ₁ , 40 ₂ ... 40 _n are write data It is a pair of bus lines.

41 ₁ , 41 ₂ ... 41 _{mn + n} are read column gates, 42 ₁ , 42 ₂ ... 42 _{mn + n} are write column gates, 43 ₁ , 43 ₂ ... 43 _{m + 1} is a column gate driver.

That is, in the first invention, the bit line pair 3
8 ₁ , 38 ₂ ... 38 _{mn + n} (n = integer of 2 or more, m = 0
For the above integers), read data bus line pair 3
9 ₁ , 39 ₂ ... 39 _n and write data bus line pair 4
0 ₁ , 40 ₂ ... 40 _n are provided.

The bit line pairs 38 ₁ , 38 _2, ... 38
Corresponding to _{mn + n} , read column gates 41 ₁ and 41 ₂
... 41 _{mn + n} and write column gates 42 ₁ and 42 ₂
... 42 _{mn + n} are provided.

In addition, the read column gate 41₁, 41₂
... 41_nAnd column gate 42 for light₁, 42₂・
・ ・ 42_nGroup consisting of 4 column gates for leads
1_{n + 1}, 41_{n + 2}... 41_{n + n}And column games for lights
To 42_{n + 1}, 42_{n + 2}... 42 _{n + n}A group of
..., read column gate 41_{mn + 1}, 41_{mn + 2}・ ・
・ 41_{mn + n}And column gate 42 for light_{mn + 1}, 42
_{mn + 2}... 42_{mn + n}1 group each consisting of
As a column gate dry
Ba 43₁, 43₂... 43_{m + 1}Is provided.

Here, FIG. 2 shows the read column gate 41 _pn provided corresponding to the bit line pair 38 _{pn + i} (where p = 0 to an integer of m and i = 1 to an integer of n). FIG. 44 is a circuit diagram showing _{+ i} and a write column gate 42 _{pn + i} ,
_{pn + i} , 45 _{pn + i} , 46 _{pn + i} , 47 _{pn + i} , 48 _{pn + i} , 49
_{pn + i} is a MOS transistor.

That is, the read column gate 41_{pn + i}Is
MOS transistor 44_{pn + i}, 45 _{pn + i}, 46_{pn + i}Four
7_{pn + i}The MOS transistor 4
Four_{pn + i}, 45_{pn + i}Wiring 50 and data bus line pair for read
39_iOne read data bus line / RDB_iBetween
MOS transistor 44 connected in series in order_{pn + i}The game
Bit line pair 38_{pn + i}One bit line BL_{pn + i}Contact
It continues.

Further, the MOS transistors 46 _{pn + i} , 47
_{pn + i} is sequentially connected in series between the wiring 50 and the other read data bus line RDB _i of the read data bus line pair 39 _i , and the gate of the MOS transistor 46 _{pn + i} is connected to the bit line pair 38 _{pn +. i} of the other bit line / BL is connected to the _{pn + i.}

When the power loss is not taken into consideration, the wiring 50 is grounded and used for reading the column selected from the precharged read data bus line pair not only at the time of reading but also at the time of writing. A current flows to the ground via the column gate and the wiring 50.

On the other hand, in consideration of power loss, the wiring 50 is grounded at the time of reading, but at the time of writing, the lead of the column selected from the precharged read data bus line pair. Wiring through the column gate for
The voltage is set so that the current flowing to 0 can be suppressed.

In addition, the write column gate 42_{pn + i}Is
MOS transistor 45_{pn + i}, 47 _{pn + i}Than thresh
High-voltage MOS transistor 48_{pn + i}, 49
_{pn + i}It is composed of.

Here, the MOS transistor 48 _{pn + i} is
It is connected between one bit line BL _{pn + i of the} bit line pair 38 _{pn + i} and one data bus line WDB _i of the write data bus line pair 40 _i .

Further, MOS transistors 49 _{pn + i} is the bit line pair 38 _{pn + i} of the other bit line / BL _{pn + i} and the write data bus line pairs 40 _i other write data bus line / WDB _i Is connected between and.

In the first aspect of the invention, the column selection signals CL ₁ , CL ₂ ... CL output from the column gate drivers 43 ₁ , 43 ₂ ... 43 _{m + 1 are} output.
_{m + 1} is the read column gates 41 ₁ and 41 ₂ , respectively.
... 41 _n and write column gates 42 ₁ and 42 ₂
.... MOS transistors 45 _{pn + i} forming 42 _n , 4
7 _{pn + i} , 48 _{pn + i} , 49 _{pn + i} gates (where p =
0), read column gates 41 _{n + 1} , 41 _{n + 2} ... 4
1 _{n + n} and write column gates 42 _{n + 1} , 42 _{n + 2} ...
・ MOS transistors 45 _{pn + i} , which form 42 _{n + n} , 4
7 _{pn + i} , 48 _{pn + i} , 49 _{pn + i} gates (where p =
1), ..., Read column gates 41 _{mn + 1} , 41
_{mn + 2}・ ・ ・ 41 _{mn + n} and write column gate 4
2 _{mn + 1} , 42 _{mn + 2} ... to the gates of the MOS transistors 45 _{pn + i} , 47 _{pn + i} , 48 _{pn + i} , 49 _{pn + i} (provided that p = m) that form 42 _{mn + n} Supplied.

However, these column selection signals CL ₁ , CL ₂
... CL _{m + 1} is the MOS transistor 4 when reading
5 _{pn + i} , 47 _{pn + i} conductive, MOS transistor 48
_{pn + i} and 49 _{pn + i} are non-conducting, and when writing, MO
S transistor 45 _{pn + i} , 47 _{pn + i} , 48 _{pn + i} , 49
It is a signal of a level that makes _{pn + i} conductive.

FIG. 3 is a circuit diagram showing the principle of the second invention in the present invention. In the second invention, logic gates 51 ₁ and 51 ₂ for selecting a column in a column decoder are shown.
... 51 _{m + 1} to the above-described column selection signals CL ₁ and CL ₂
... CL _{m + 1} is output, and the column gate drivers 43 ₁ , 43 ₂ ... 43 _{m + 1} are not necessary, and other configurations are the same as those of the first invention. It is a thing.

[0049]

In the first aspect of the invention, the read column gates 41 ₁ , 41 ₂ ... 41 _n and the write column gate 4 are provided.
Group consisting of 2 ₁ , 42 ₂ ... 42 _n , read column gates 41 _{n + 1} , 41 _{n + 2} ... 41 _{n + n} and write column gates 42 _{n + 1} , 42 _{n + 2} ...・ Group consisting of 42 _{n + n} , ..., Read column gate 41 _{mn +1}
41 _{mn + 2} ... 41 _{mn + n} and write column gate 42
_{mn + 1} , 42 _{mn + 2} ... 42 _{mn + n} corresponding to a group of column gate drivers 43 ₁ , 43 ₂ ... 43
_{Since m + 1} is provided, it is not necessary to provide a column gate driver for each column.
The area forming the driver is reduced, the area loss is reduced,
The chip surface can be effectively used.

In the second invention, the column selection signals CL ₁ , CL ₂ ... CL _{m + 1} are output from the logic gates 51 ₁ , 51 _2, ... 51 _{m + 1 for} selecting columns. Column gate drivers 43 ₁ , 43 ₂
・ ・ ・ 43 _{m + 1} is not required, so column gate
The area for forming the driver can be eliminated, the area loss can be reduced more than in the first invention, and the chip surface can be effectively used more than in the first invention.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 5 to 17, a DRAM in which a read data bus line pair and a write data bus line pair are respectively duplicated in the first to third embodiments of the present invention. The case where the present invention is applied to will be described as an example.

First Embodiment ... FIG. 5 to FIG. 13 FIG. 5 is a circuit diagram showing a main part of an embodiment of the present invention. A memory cell array part 1 in which memory cells are arranged, bit lines BL1, / BL1, BL2, / BL2, sense amplifiers 2, 3, read data bus lines RDB1, / RDB
1, RDB2, / RDB2, write data bus line WD
For B1, / WDB1, WDB2, / WDB2,
The circuit diagram is similar to that of the conventional DRAM shown in FIG.

Here, 51 is a sense amplifier activation circuit for activating a group of sense amplifiers including the sense amplifiers 2 and 3. This sense amplifier activation circuit 51
Is configured as shown in FIG. 6, for example.

In the figure, 52 and 53 are pMOS transistors, 54 and 55 are nMOS transistors, 56 and 57 are inverters, and VCC is a power supply voltage, for example, 3 [V], V.
PR is a precharge voltage, for example, 1/2 VCC = 1.
5 [V] and / RS are reset signals, LE is a latch enable signal, and PSA and NSA are sense amplifier activation signal lines.

In the sense amplifier activation circuit 51, when the reset signal / RS = "L" and the latch enable signal LE = "L", the pMOS transistor 5 is used.
3 = ON, nMOS transistor 54 = ON, pMOS
Transistor 52 = OFF, nMOS transistor 55
= OFF, the sense amplifier activation signal lines PSA, N
SA is precharged to the precharge voltage VPR.

From this reset state, reset signal / R
When S = “H” and latch enable signal LE = “H”, pMOS transistor 53 = OFF, nMOS transistor 54 = OFF, pMOS transistor 52 =
ON, the nMOS transistor 55 = ON, the sense amplifier activating signal line PSA is set to the power supply voltage VCC, the sense amplifier activating signal line NSA is set to the ground voltage, and all the sense amplifier activating circuits 51 are connected. Sense amplifiers, eg, 1024 sense amplifiers, are activated.

Further, in FIG. 5, 58 is a bit line pair B.
Read column gates provided corresponding to L1 and / BL1, 59 are read column gates provided corresponding to the bit line pair BL2 and / BL2, and 60 to 67 are n.
It is a MOS transistor. The threshold voltage of the nMOS transistors 61, 63, 65, 67 is, for example, 0.1 [V].

Further, 68 is a wiring, and 69 is a VSS * generator (VSS * Gen.) For generating the voltage VSS *. The VSS * generator 69 is constructed as shown in FIG. 7, for example.

In the figure, WE is a write enable signal, 7
Reference numerals 0, 71, and 72 are inverters, 73 is a pMOS transistor, and 74 is an nMOS transistor. Also, 75 and 76 are nMOS transistors.

In the VSS * generator 69, when the write enable signal WE = “L”, the inverter 70
Output = “H”, output of inverter 72 = “L”, n
When the MOS transistor 75 is turned off and the output of the inverter 71 is “H”, the nMOS transistor 7
6 = ON, the wiring 68 is connected to the nMOS transistor 7
It is grounded via 6 and VSS * = 0 [V].

On the other hand, the write enable signal WE
= “H”, the output of the inverter 70 = “L”, the output of the inverter 72 = VPR, the output of the inverter 71 = “L”, and the nMOS transistor 76 = O.
FF, and the voltage Vss * of the wiring 68 is VPR = VPR
-VTH (threshold voltage of nMOS transistor) = 1/2 VCC-VTH.

In FIG. 5, reference numeral 77 is a read amplifier provided corresponding to the read data bus line pair RDB1, / RDB1, and 78 is a read data bus line pair RDB.
2, a read amplifier provided corresponding to / RDB2.

Here, the read amplifier 77 is constructed, for example, as shown in FIG. The same applies to the read amplifier 78. In the figure, 79 is a precharge circuit unit,
Reference numeral 82 is an nMOS transistor, VRR is a precharge voltage, for example, 1.0 [V], and RR is a reset signal.

Reference numeral 83 is a differential amplifier section, and 84,
85 is a pMOS transistor, 86 to 88 are nMOS transistors, SBE is a read amplifier enable signal,
OUT and / OUT are outputs.

In this read amplifier 77, the reset signal RR = “H”, the read amplifier enable signal S
When BE = “L”, the nMOS transistor 80
.About.82 = ON, the nMOS transistor 88 = OFF, and the read data buses RDB1 and / RDB1 are precharged to the precharge voltage VRR.

From this reset state, the reset signal RR
= “L”, read amplifier enable signal SBE =
When set to “H”, the nMOS transistors 80 to 82 =
When the nMOS transistor 88 is turned off, the nMOS transistor 88 is turned on, the differential amplifier 83 is activated, and reading is enabled.

Further, in FIG. 5, 89 is a bit line pair B.
Write column gates provided corresponding to L1 and / BL1, 90 are write column gates provided corresponding to bit line pair BL2 and / BL2, and 91 to 94 are n.
It is a MOS transistor. The threshold voltages of the nMOS transistors 91 to 94 are, for example,
1/2 VCC = 1.5 [V].

Further, 95 is a write data bus line pair WD
A write amplifier provided corresponding to B1 and / WDB1,
A write amplifier 96 is provided corresponding to the write data bus line pair WDB2, / WDB2.

Here, the write amplifier 95 is constructed, for example, as shown in FIG. The same applies to the write amplifier 96. In the figure, 97 is a precharge circuit unit,
100 is an nMOS transistor, VWW is a precharge voltage, for example, 3.0 [V], and WW is a reset signal.

Further, 101 and 102 are pMOS transistors, 103 and 104 are nMOS transistors, and 105.
˜109 are inverters, 110 and 111 are NAND circuits, and DIN1 is input data to be written.

In the write amplifier 95, the reset signal WW = “H” and the write enable signal WE =
When set to “L”, nMOS transistors 98 to 10
0 = ON and the NAND circuits 110 and 111
Output = “H”, output of inverters 107 and 108 =
“L”, the outputs of the inverters 105 and 106 = “H”, and the pMOS transistors 101 and 102 = OFF, n
The MOS transistors 103 and 104 are turned off, and the write data bus line pair WDB1 and / WDB1 is precharged to the precharge voltage VWW.

From this reset state, the reset signal WW
= “L” and the write enable signal WE = “H”, the nMOS transistors 98 to 100 are turned off, and the outputs of the NAND circuits 110 and 111 depend on the input data DIN1. Is possible.

In FIG. 5, 112 is a column decoder, and 113 is read column gates 58 and 59.
And NA for selecting the write column gates 89 and 90
It is an ND circuit.

Further, 114 outputs a column selection signal CL of two kinds of levels, which will be described later, to read column gate 5
8, a column gate driver for driving the write column gates 89, 90;
The S transistor and 116 are nMOS transistors.

Further, 117 is a column gate driver 1
A group of column gate driver pMOSs including 14
VQQ for generating signal VQQ to be supplied to transistor
A generator (VQQ · Gen.), 118 is a VQQ line.

The VQQ generator 117 is constructed, for example, as shown in FIG. In the figure, reference numeral 119 is a voltage dividing circuit for dividing the power supply voltage VCC to obtain 1/2 VCC, 120 and 121 are resistors having the same resistance value, and 122 is a MOS capacitor. That is, the node 123 is made to obtain 1/2 VCC.

Reference numeral 124 is a high speed 1 / 2VCC reset circuit for performing the high speed operation when the VQQ line 118 is reset from VCC to 1 / 2VCC.
Is a pMOS transistor, 126 is an nMOS transistor, 127 and 128 are resistors having a resistance value smaller than that of the resistors 120 and 121 and having the same resistance value.

Reference numeral 129 is a one-shot pulse generating circuit for generating a one-shot pulse for driving the high speed 1 / 2VCC reset circuit 124, and 13
0 ₁ , 130 ₂ ... 130 _{2n + 1} is an inverter forming a delay circuit, 131 is a NOR circuit, and 132 is a NOR circuit 1
It is an inverter that inverts the output of 31.

Further, 133 is a pMOS transistor for charging up the VQQ line 118 to VCC, and 13
Reference numeral 4 is an nMOS transistor for disconnecting the voltage dividing circuit 119 from the VQQ line 118, and 135 is an inverter.

FIG. 11 is a waveform diagram showing the operation of the VQQ generator 117 shown in FIG. 10. FIG. 11A is a write enable signal WE, FIG. 11B is the output of the inverter 135, and FIG. 11C is the output of the inverter 130 _{2n + 1} . FIG. 11D
Is the output of the NOR circuit 131, and FIG. 11E is the inverter 13
2 outputs, FIG. 11F shows the signal VQQ.

That is, the VQQ generator 1 shown in FIG.
In FIG. 17, at the time of reading and at the time of reset, the write enable signal WE = “L”, the output of the inverter 135 = “H”, the nMOS transistor 134 = ON,
The pMOS transistor 133 is turned off.

In this case, the output of the inverter 130 _{2n + 1} = “H”, the output of the NOR circuit 131 = “L”, the output of the inverter 132 = “H”, the nMOS transistor 126 = OFF, the pMOS transistor 125 = OFF
It is said that As a result, VQQ = 1 / 2VCC.

From this state, the write enable signal WE
= “H”, and during the write period, the inverter 1
35 output = “L”, nMOS transistor 134 = 0
The FF and pMOS transistor 133 are turned on, and the voltage dividing circuit 119 is disconnected from the VQQ line 118.

In this case, the output of the inverter 130 _{2n + 1} = “H”, the output of the NOR circuit 131 = “L”, the inverter 132 = “H”, and the nMOS transistor 126 = OFF and the pMOS transistor 125 = OFF.
To maintain. As a result, VQQ is charged up to VCC by the pMOS transistor 133.

After that, when the write period ends, the write enable signal WE is set to "L", and the inverter 135
Output = “H”, and nMOS transistor 134 =
It is turned on and the pMOS transistor 133 is turned off, and the voltage dividing circuit 119 and the VQQ line 118 are connected.

In this case, the output of the inverter 130 _{2n + 1} = “L”, the output of the NOR circuit 131 = “H”, the output of the inverter 132 = “L”, the nMOS transistor 126 = ON, the pMOS transistor 125 = The signal VQQ is turned ON at high speed through the resistors 127 and 128.
Reset to / 2VCC.

FIG. 12 is a waveform diagram showing the read operation of the first embodiment thus constructed. That is, in the first embodiment, first, the reset signal RS =
“H”, that is, in FIG. 6, reset signal / RS =
“L” and the latch enable signal LE = “L”.

As a result, in the sense amplifier activation circuit 51 shown in FIG. 6, the pMOS transistor 53 = 0.
N, nMOS transistor 54 = ON, pMOS transistor 52 = OFF, nMOS transistor 55 = OF
F, the sense amplifier activation signal lines PSA and NSA are precharged to the precharge voltage VPR.

After that, the reset signal RS = “L”, that is, the reset signal / RS = “H” is set, the pMOS transistor 53 = OFF, the nMOS transistor 54 = O.
FF. At this stage, the latch enable signal LE = “L”, the pMOS transistor = OFF,
The nMOS transistor 55 is kept OFF.

Thereafter, the word line WL selected by the row decoder (not shown) is set to "H", the storage information of the memory cell connected to this word line WL is transmitted to the bit line, and the bit line pair is transmitted. There is a slight voltage difference between the one bit line BL and the other bit line / BL.

After that, the latch enable signal LE =
It is set to "H", and as a result, the sense amplifier activation circuit 51
, PMOS transistor 52 = ON, nMO
The S transistor 55 is turned on.

As a result, the sense amplifier activation signal line PS
A is set to the power supply voltage VCC, the sense amplifier activation signal line NSA is set to the ground voltage, and all sense amplifiers connected to the sense amplifier activation circuit 51, for example, 1
024 sense amplifiers are activated and bit lines BL,
The voltage difference between / BL is amplified.

At this stage, in FIG. 8, the reset signal RR = “H”, the read amplifier enable signal SBE = “L”, and the nMOS transistors 80 to 82 =
ON, the nMOS transistor 88 = OFF, and the read data bus lines RDB1 and / RDB1 are precharged to the precharge voltage VRR. The read data bus lines RDB2, / RDB2 are similarly precharged to the precharge voltage VRR.

From this reset state, first, the reset signal RR = “L” is set, and in the read amplifier 77,
The nMOS transistors 80 to 82 are turned off, and the read data bus lines RDB1 and / RDB1 are maintained at the precharge voltage VRR. Read data bus line RDB
The same applies to 2 and / RDB2.

In this case, the column gate is selected, but before the column gate is selected, in FIG. 5, for example, the output of the NAND circuit 113 =
At “H”, the pMOS transistor 115 of the column gate driver 114 = OFF, the nMOS transistor 11
6 = ON and the column selection signal CL = “L”.

As a result, the read column gates 58, 5
9 nMOS transistors 61, 63, 65, 67 = O
The nMOS transistors 91, 92, 93 and 94 of the FF and the write column gates 89 and 90 are turned off. The same applies to the other read column gates and write column gates.

Here, for example, the read column gate 5
8 and 59 and write column gates 89 and 90 are selected, column address signals CA0 and / CA0 for selecting the read column gates 58 and 59 and the write column gates 89 and 90 to the column decoder 112.
./CA9 is supplied and the output of the NAND circuit 113 =
“L”, pMO of column gate driver 114
S transistor 115 = ON, nMOS transistor 1
16 = OFF.

At the time of reading, as shown in FIG.
Write enable signal WE = “L”, VQQ = 1/2
Since it is set to VCC, the column selection signal CL = 1/2 VCC in FIG.

As a result, the threshold voltage is reduced to 0.1
Read column gate 5 with [V] <1/2 VCC
8, 59 nMOS transistors 61, 63, 65, 6
7 = ON, threshold voltage is 1.5 [V] =
NMOS transistors 91, 92, 93, 94 of write column gates 89, 90 for 1/2 VCC = substantially OF
It becomes F.

Here, nMOS transistors 61 and 63
Information of the bit line pair BL1, / BL1 is transmitted to the read data bus line pair RDB1, / RDB1 together with the nMOS transistors 60, 62 connected in series with the read data bus line RDB1, / RDB1. Occurs.

Information of the bit line pair BL2, / BL2 is transmitted to the read data bus line pair RDB2, / RDB2 together with the nMOS transistors 64, 66 connected in series with the nMOS transistors 65, 67, and read data is read. A voltage difference occurs between the bus lines RDB2 and / RDB2.

Then, in FIG. 8, the read amplifier enable signal SBE is set to "H", and the read amplifier 77 is turned on.
In the differential amplifier section 83 of the
T and / OUT are output.

Then, reset signal RR = “L”, column selection signal CL = “L”, word line WL = “L”, latch enable signal LE = “L”, reset signal RS =
It is set to "H", and the read operation is completed.

FIG. 13 is a waveform diagram showing the write operation of the first embodiment. That is, in the first embodiment, first, the reset signal RS = “L”, that is, the reset signal / RS = “H” in FIG. 6, the word line WL to be selected = “H”, and the latch enable signal LE. =
It is set to "H".

As a result, as in the case of reading, the storage information of the memory cell connected to the selected word line WL is transmitted to the bit line, and the bit line BL on one side and the bit line / BL on the other side are transmitted. There is a slight voltage difference between them, which is amplified.

At this stage, in FIG. 9, the reset signal WW = “H” and the write enable signal WE = “L”.
In the write amplifier 95, nMOS transistors 98 to 100 = ON, pMOS transistor 101,
102 = OFF, nMOS transistors 103 and 104
= OFF, and write data buses WDB1 and / WD
B1 is precharged to the precharge voltage VWW.
Regarding the write data buses WDB2 and / WDB2,
It is the same.

From this reset state, first, the reset signal WW is set to "L", and in the write amplifier 95,
The nMOS transistors 98 to 100 are turned off, and the write data buses WDB1 and / WDB1 are maintained at the precharge voltage VWW. Write data bus WDB
The same applies to 2 and / WDB2.

After that, the input data DIN1 is input,
Then, the write enable signal WE is set to "H", and N
The outputs of the AND circuits 110 and 111 are the input data DIN
1 depends on the write data bus WDB
1, a potential difference occurs between / WDB1. The same applies to the write data buses WDB2 and / WDB2.

Here, again, the write enable signal WE
= “H”, the VSS * generator 69 shown in FIG. 7 causes the voltage VSS * = VPR−VTH = 1 of the wiring 68.
/ 2VCC-VTH.

After that, the column gate is selected. Before the column gate is selected, in FIG.
For example, when the output of the NAND circuit 113 is “H”, the pMOS transistor 115 of the column gate driver 114 is
= OFF, the nMOS transistor 116 = ON, and the column selection signal CL = “L”.

As a result, the read column gates 58, 5
9 nMOS transistors 61, 63, 65, 67 = O
The nMOS transistors 91, 92, 93 and 94 of the FF and the write column gates 89 and 90 are turned off. The same applies to the other read column gates and write column gates.

Here, for example, the read column gate 5
8 and 59 and the write column gates 89 and 90 are selected, the column address signals CA0 and / CA0 for selecting the read column gates 58 and 59 and the write column gates 89 and 90 to the column decoder 112.
./CA9 is supplied and the output of the NAND circuit 113 =
“L”, pMO of column gate driver 114
S transistor 115 = ON, nMOS transistor 1
16 = OFF.

At the time of writing, the write enable signal WE is "H" in FIG. 10 and the VQQ generator 117 shown in FIG. 10 sets VQQ = VCC, so the column selection signal CL = VCC.

As a result, in FIG. 5, the nMOS transistors 61 and 6 of the read column gates 58 and 59 having the threshold voltage of 0.1 [V] <1/2 VCC.
3,65,67 = ON, threshold voltage 1.5
Write column gate 8 with [V] = 1/2 VCC
9, 90 nMOS transistors 91, 92, 93, 9
4 = ON.

In the write column gate 89, the bit lines BL1 and / BL1 and the write data bus line RDB1 are connected via the nMOS transistors 91 and 92.
/ RDB1 is connected to generate a voltage difference between the bit lines BL1 and / BL1.

In the write column gate 90, the bit lines BL2 and / BL2 and the write data bus lines RDB2 and / via the nMOS transistors 93 and 94.
RDB2 is connected, a voltage difference is generated between the bit lines BL2 and / BL2, and writing is performed.

In this case, since the wiring 68 is set to 1 / 2VCC-VTH by the VSS * generator 69, the current flowing from the read data bus line pair RDB1, / RDB1 to the wiring 68 via the read column gate 58. Also, the current flowing from the read data bus line pair RDB2, / RDB2 to the wiring 68 via the read column gate 59 can be sufficiently suppressed, and the power consumption can be reduced.

After that, the column selection signal CL = “L”, the write enable signal WE = “L”, the reset signal WW =
"H", VQQ = 1/2 VCC, word line WL =
The write operation is completed by setting “L”, the latch enable signal LE = “L”, and the reset signal RS = “H”.

Thus, in this first embodiment,
The column gate driver 114 drives the read column gates 58 and 59 and the write column gates 89 and 90 by one column gate driver,
Two read column gates and two write column gates can be driven.

Therefore, according to the first embodiment, 2
Since it suffices to form one column gate driver within the width of the column (within the formation width of two sense amplifiers), the region 136 provided for forming the column gate driver is narrowed to reduce the area. The loss can be reduced and the chip surface can be effectively used.

In the first embodiment, VQQ
Has described the case where two types of voltage values of 1/2 VCC and VCC are set, this VQQ is
It is not uniquely determined to take a seed voltage.

If the voltage value to be taken at the time of reading is VQQR and the voltage value to be taken at the time of writing is VQQW, first, for example, the nMOS transistor 91 is turned on.
In order to become N, the precharge voltage of the bit line must be VB
L _P , write data bus line precharge voltage to VW
DB _P , read data bus line precharge voltage to R
If the threshold voltage of WDB _P and the nMOS transistor 91 is expressed as VTH (H), if the bit line pair is not amplified at all in the worst case and one and the other bit line of the bit line pair are at the precharge voltage, VQQ
It is necessary to set W as shown in Equation 1.

[0123]

[Equation 1]

Considering the write efficiency, VB
In some cases, L _P <VWDB _P = about VCC, and
In recent years, a method of setting VBL _P of a DRAM to about 1/2 VCC is often used, and when this is adopted, equation 1 becomes equation 2.

[0125]

[Equation 2]

As can be seen from these equations 1 and 2, VQ
It is appropriate that QW has a voltage as high as possible, and it is appropriate to set VQQW = VCC or VQQW = VCC + α · VTH (H). However, α> 1. At this time, the gate overdrive of the nMOS transistor 91 at the time of writing is
Equation 3 is obtained, which is sufficient for turning on the nMOS transistor 91.

[0127]

[Equation 3]

Similarly, considering VQQR at the time of reading, in order to sufficiently turn on the series path of the nMOS transistors 60 and 61, in consideration of the worst case, it is necessary to set VQQR as shown in Formula 4. is there. However,
VTH (L) is the threshold voltage of the nMOS transistor 61.

[0129]

[Equation 4]

On the other hand, it is ideal that the nMOS transistor 91 is turned off at the level of VQQR.
Even if it is ON, it must be in a state where the overdrive is very small in the vicinity of VTH (H). Therefore, considering the worst case, it is desirable to set VQQR as in equation 5 or equation 6. However, k is a sufficiently small value of 1/10>k> 0.

[0131]

[Equation 5]

[0132]

[Equation 6]

Here, as can be seen from Equation 4, VQQR
It is desirable that VTH (L) and VRDB _p are low in order to bring the level of V to the intermediate level between VCC and VSS. Also, as can be seen from Equations 5 and 6, VQQR is V
It is desirable that it is approximately equal to TH (H).

Now, when VQQW ≧ VCC,
VQQR is VQQR = about VTH (H) = 1/2 VCC
VTH (L) = 0.1-0.1.
As small as 2 [V], VRDB _P is VRDB _P = 1 / 2V
Set to about CC-0.5 [V].

By doing so, the column selection line can be shared during both reading and writing. Therefore, for example, as in the case of the first embodiment, VQQW =
3.0 [V], VQQR = 1.5 [V], VTH (H) =
1.5 [V], VTH (L) = 0.1 [V], VRDB _P
= 1.5 [V] and VWDB _P = 3.0 [V], the desired operation can be achieved.

Second Embodiment ... FIG. 14, FIG. 15 In the second embodiment of the present invention, as the VQQ generator, the VQQ generator shown in FIG. 14 is incorporated instead of the VQQ generator shown in FIG. The configuration is similar to that of the DRAM shown in FIG.

The VQQ generator shown in FIG.
By removing the pMOS transistor 133 from the VQQ generator shown in FIG. 10, the inverters 137, 138, nM are removed.
OS transistors 139 and 140, MOS capacitor 1
41 and 142 are added. Note that VPP is
A voltage higher than the power supply voltage VCC, for example, VCC
The voltage is + VTH or VCC + 2VTH.

In this VQQ generator, the write enable signal WE = "L" at the time of reading and at the time of resetting.
Then, the output of the inverter 135 = “H”, the nMOS transistor 134 = ON, and the voltage dividing circuit 119 is connected to the VQQ line 118.

The output of the inverter 137 = “L”,
When the node 143 = “L”, the nMOS transistor 140
= OFF, the voltage VPP is not transmitted to the VQQ line 118.

In this case, the output of the inverter 130 _{2n + 1} = “H”, the output of the NOR circuit 131 = “L”, the output of the inverter 132 = “H”, the nMOS transistor 126 = OFF, the pMOS transistor 125 = OFF
It is said that Further, the output of the inverter 138 = “L”.

Therefore, at the time of reading and at the time of resetting, VQQ = 1 / 2VCC, which is VQQ line 11
PMOS of the column gate driver 114 via
PM of column gate driver such as transistor 115
It is supplied to the OS transistor.

From this state, the write enable signal WE
= “H”, and during the write period, the inverter 1
35 output = “L”, nMOS transistor 134 = 0
FF, the voltage dividing circuit 119 is disconnected from the VQQ line 118, and the output of the inverter 137 = “H” and the node 143 = “H”.

On the other hand, in this case, the output of the inverter 130 _{2n + 1} = “H”, the output of the NOR circuit 131 = “L”, the output of the inverter 132 = “H”, and the nMOS transistor 126 = OFF and the pMOS transistor 125. =
Keep OFF.

Thereafter, the output of the inverter 130 _{2n + 1} =
It becomes “L”, but in this case, the inverter 138 = “H”
Then, the node 143 is charged up via the MOS capacitor 141 and rises, the nMOS transistor 140 turns ON, and the source voltage of the nMOS transistor 140 rises.

Then, the voltage of node 143 further rises to exceed VPP via MOS capacitor 142, and voltage VPP is transmitted to VQQ line 118 and VQQ line 118 is transmitted.
Q = VPP, which is transmitted via the VQQ line 118 to the pMOS transistor 1 of the column gate driver 114.
15, etc., to the pMOS transistor of the column gate driver. In this case, nMOS transistor 126 = OFF, pMOS transistor 125 = OF
We are maintaining F.

Thereafter, when the write period ends, the write enable signal WE = “L”, the output of the inverter 135 = “H”, and the nMOS transistor 134 = ON.
The voltage dividing circuit 119 and the VQQ line 118 are connected, and the output of the inverter 137 = “L”, node 14
3 = “L”, and nMOS transistor 140 = OF
It is assumed to be F.

On the other hand, in this case, the output of the inverter 130 _{2n + 1} = “L”, the output of the NOR circuit 131 = “H”, the output of the inverter 132 = “L”, the nMOS transistor 126 = ON, the pMOS transistor 125 = It turns ON, and VQQ becomes 1/2 at high speed through the resistors 127 and 128.
Reset to VCC.

FIG. 15 is a waveform diagram showing the operation at the time of writing of the second embodiment equipped with this VQQ generator. VQQ has a low voltage side of 1/2 VCC and a high voltage side of VPP. Except for the points, the operation is the same as the write operation in the first embodiment shown in FIG.

According to the second embodiment, the same effect as that of the first embodiment can be obtained, and the voltage of the column selection line CL for driving the write column gate is set to VPP> VCC. Therefore, the switching operation of the nMOS transistor forming the write column gate can be speeded up, and the data of the write data bus can be stably transmitted to the bit line.

Third Embodiment ... FIGS. 16 and 17 FIG. 16 is a circuit diagram showing an essential part of a third embodiment of the present invention. This third embodiment is a column decoder 1 of the first embodiment.
The configuration is the same as that of the first embodiment shown in FIG. 5 except that a column decoder 144 having a configuration different from that of No. 12 is mounted.

Here, the column decoder 144 uses a NAND circuit using the voltage VQQ as a power supply voltage as a NAND circuit for selecting a column and eliminates the column gate driver.

That is, referring to FIG. 16, a NAND circuit for selecting the read column gates 58 and 59 and the write column gates 89 and 90 is used as the voltage VQQ.
The NAND gate 145 having the power supply voltage of 5 is used, and the column gate driver 114 shown in FIG. 5 is deleted.

This NAND circuit 145 is, for example, as shown in FIG.
It is configured as shown in FIG. In the figure, 146 ₀ , 146 ₁
.... 146 ₉ are pMOS transistors 147 ₀ , 147
₁ ... 147 ₉ are nMOS transistors.

As described above, according to the third embodiment, the NAND circuit for selecting columns outputs the column selection signals CL ₁ , CL _2, ... CL _{m + 1} similar to those in the first case. Since the column gate driver is unnecessary, the area for forming the column gate driver is eliminated,
The area loss can be reduced more than that of the first embodiment, and the chip surface can be effectively used more than that of the first embodiment.

[0155]

According to the first aspect of the present invention, it suffices to provide one column gate driver for every two or more columns, and one column gate driver for each column. Therefore, the area for forming the column gate driver can be reduced, the area loss can be reduced, and the chip surface can be effectively used.

Further, according to the second invention, since the column gate driver is unnecessary, the region for forming the column gate driver is eliminated, the area loss is reduced more than in the first invention, and the chip surface is reduced to the first surface. The invention can be used more effectively than the above invention.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a principle of a first invention in the present invention.

FIG. 2 is a circuit diagram showing configurations of a read column gate and a write column gate.

FIG. 3 is a circuit diagram showing a principle of a second invention in the present invention.

FIG. 4 is a circuit diagram showing another configuration example of a read column gate.

FIG. 5 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a sense amplifier activating circuit which constitutes a first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a VSS * generator that constitutes the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a read amplifier which constitutes a first embodiment of the present invention.

FIG. 9 is a circuit diagram showing a write amplifier which constitutes a first embodiment of the present invention.

FIG. 10 is a circuit diagram showing a VQQ generator that constitutes the first embodiment of the present invention.

11 is a waveform diagram showing an operation of the VQQ generator shown in FIG.

FIG. 12 is a waveform chart showing an operation during reading according to the first embodiment of the present invention.

FIG. 13 is a waveform diagram showing an operation at the time of writing according to the first embodiment of the present invention.

FIG. 14 is a circuit diagram showing a VQQ generator incorporated in a second embodiment of the present invention.

FIG. 15 is a waveform chart showing an operation at the time of writing according to the second embodiment of the present invention.

FIG. 16 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 17 is a circuit diagram showing a NAND circuit of a column decoder which constitutes a third embodiment of the present invention.

FIG. 18 is a circuit diagram showing a main part of an example of a conventional DRAM.

[Explanation of symbols]

38 ₁ , 38 ₂ ... 38 _{mn + n} bit line pair 39 ₁ , 39 ₂ ... 39 _n read data bus line pair 40 ₁ , 40 ₂ ... 40 _n write data bus line pair 41 ₁ , 41 ₂ ... 41 _{mn + n} read column gates 42 ₁ , 42 ₂ ... 42 _{mn + n} write column gates 43 ₁ , 43 ₂ ... 43 _{m + 1} column gate driver CL ₁ , CL ₂ ... CL _{m + 1} column selection signal

Claims (10)

[Claims] 1. First, second ... mn + n (where n =
Bit line pair (38, integer of 2 or more, m = 0 or more)
₁, 38₂... 38_{mn + n}) To the first, second ...
n read data bus line pair (39₁, 39₂... 39
_n) And a write data bus line pair (40₁, 40₂...
40_n) Is provided and the first, second ... mnth
+ N bit line pair (38₁, 38₂... 38_{mn + n}) To
The first, second ... mn + n lead columns.
Gate (41₁, 41₂... 41_{mn + n}) And light
Ramgate (42₁, 42₂... 42_{mn + n}), The first
pn + i (provided that p = 0 to m is an integer, i = 1 to n is an integer
The number of read column gates is 1st, 2nd, 3rd, 3rd,
4 MOS transistor (44_{pn + i}, 45_{pn + i}, 46
_{pn + i}, 47_{pn + i}), And the first and second MO
S transistor (44_{pn + i}, 45_{pn + i}) The predetermined wiring
(50) and the i-th read data bus line pair (39_i)of
One read data bus line (/ RDB_i) And order
Connected in series with the first MOS transistor (44
_{pn + i}) With the gate of pn + i bit line pair (38_{pn + i})
One bit line (BL_{pn + i}) And the above
Third and fourth MOS transistors (46_{pn + i}Four
7_{pn + i}) Is the predetermined wiring (50) and the i-th lead
Data bus line pair (39_i) The other read data
Line (RDB_i) And in series in order,
MOS transistor (46_{pn + i}) Gate to the p-th
n + i bit line pair (38_{pn + i}) Other bit line (/
BL_{pn + i}), And the pn + i write column game for writing
To (42_{pn + i}) Is the second and fourth MOS transistors
(45_{pn + i}, 47_{pn + i}) Than the threshold voltage
High fifth and sixth MOS transistors (48_{pn + i}, 49
_{pn + i}), And the fifth MOS transistor
(48_{pn + i}) Is the pn + i-th bit line pair (3
8_{pn + i}) One bit line (BL_{pn + i}) And the i-th light
Data bus line pair (40_i) One write data buffer
Line (WDB_i) And the sixth
MOS transistor (49_{pn + i}) Is the pn + i-th
Line pair (38_{pn + i}) Other bit line (/ BL_{pn + i})
And the i-th write data bus line pair (40_i) The other
Write data bus line (/ WDB_i) And connect
, The first, second ... mn + n lead columns
Gate (41₁, 41₂... 41_{mn + n}) And light
Ramgate (42₁, 42₂... 42_{mn + n}) Is the first,
Second ... nth read column gate (41₁, 41₂
... 41_n) And a column gate for light (42₁, 42
₂... 42_n) Group consisting of n + 1 and n + 2
... The (n + n) th read column gate (41_{n + 1}Four
1_{n + 2}... 41_n+_n) And column gate for light (4
Two_{n + 1}, 42_{n + 2}... 42_{n + n}Group consisting of
.., mn + 1, mn + 2 ... mn + n Lee
Column gate (41_{mn + 1}, 41_{mn +2}... 4
1_{mn + n}) And a column gate for light (42_{mn + 1}, 42
_{mn + 2}... 42 _{mn + n}) Each group
The first, second ... m + 1th colla respectively
Mugate driver (43₁, 43₂... 43_{m + 1}) To
From the second, fourth, fifth and sixth MOS transistors
(45_{pn + i}, 47_{pn + i}, 48_{pn + i}, 49_{pn + i}) Game
On the other hand, when reading, the second and fourth MOS transistors
Register (45_{pn + i}, 47_{pn + i}) The conducting state, the first
5, 6th MOS transistor (48_{pn + i}, 49_{pn + i})
Is non-conducting, and at the time of writing, the second, fourth, and
5, 6th MOS transistor (45_{pn + i}, 47_{pn + i},
48_{pn + i}, 49_{pn + i}) Level column that makes the
Selection signal (CL₁, CL₂... CL_{m + 1}) Is supplied
Semiconductor memory device characterized by being configured as follows.
Place 2. The first, second ... mn + n (where n =
Bit line pair (38, integer of 2 or more, m = 0 or more)
₁, 38₂... 38_{mn + n}) To the first, second ...
n read data bus line pair (39₁, 39₂... 39
_n) And a write data bus line pair (40₁, 40₂...
40_n) Is provided and the first, second ... mnth
+ N bit line pair (38₁, 38₂... 38_{mn + n}) To
The first, second ... mn + n lead columns.
Gate (41₁, 41₂... 41_{mn + n}) And light
Ramgate (42₁, 42₂... 42_{mn + n}), The first
pn + i (provided that p = 0 to m is an integer, i = 1 to n is an integer
The number of read column gates is 1st, 2nd, 3rd, 3rd,
4 MOS transistor (44_{pn + i}, 45_{pn + i}, 46
_{pn + i}, 47_{pn + i}), And the first and second MO
S transistor (44_{pn + i}, 45_{pn + i}) Lead to i
Data bus line pair (39_i) One read data
Line (/ RDB_i) And the predetermined wiring (50) in order
Connected in series, the first MOS transistor (44
_{pn + i}) With the gate of pn + i bit line pair (38_{pn + i})
One bit line (BL_{pn + i}) And the above
Third and fourth MOS transistors (46_{pn + i}Four
7_{pn + i}) Is the i-th read data bus line pair (3
9_i) Other read data bus line (RDB)_i) And the above
Connect in series with a predetermined wiring (50) in order,
3 MOS transistor (46_{pn + i}) Gate to the above
pn + i bit line pair (38_{pn + i}) The other bit line
(/ BL_{pn + i}), And the pn + i write column
Gate (42_{pn + i}) Is the second and fourth MOS transistors
Dista (45_{pn + i}, 47_{pn + i}) Than threshold electric
The fifth and sixth transistors (48_{pn + i}, 49
_{pn + i}), And the fifth MOS transistor
(48_{pn + i}) Is the pn + i-th bit line pair (3
8_{pn + i}) One bit line (BL_{pn + i}) And the i-th light
Data bus line pair (40_i) One write data buffer
Line (WDB_i) And the sixth
MOS transistor (49_{pn + i}) Is the pn + i-th
Line pair (38_{pn + i}) Other bit line (/ BL_{pn + i})
And the i-th write data bus line pair (40_i) The other
Write data bus line (WDB_i) And
The first, second ... mn + n read column games
To (41₁, 41₂... 41_{mn + n}) And light column
Gate (42₁, 42₂... 42_{mn + n}) Is the first and second
... Nth read column gate (41₁, 41₂・ ・
・ 41_n) And a column gate for light (42₁, 42 ₂・
・ ・ 42_n), A group consisting of n + 1, n + 2.
..Column gates for the (n + n) th read (41_{n + 1}, 41
_{n + 2}... 41_n+_n) And a column gate for light (42
_{n + 1}, 42_{n + 2}... 42_{n + n}Group consisting of ...
.., mn + 1, mn + 2 ... mn + n lead
Column gate (41_{mn + 1}, 41_{mn + 2}... 41_{mn + n})
And column gate for light (42_{mn + 1}, 42_{mn + 2}...
42_{mn + n}), Each as a unit,
1st, 2nd ... m + 1th column gate
Driver (43₁, 43₂... 43_{m + 1})
The second, fourth, fifth and sixth MOS transistors (45
_{pn + i}, 47_{pn + i}, 48_{pn + i}, 49_{pn + i}) For the gate
When reading, the second and fourth MOS transistors are used.
(45_{pn + i}, 47_{pn + i}) Is in a conductive state, and the fifth and sixth
MOS transistor (48_{pn + i}, 49_{pn + i}) Is non-conducting
The second, the fourth, the fifth, and the sixth M are in the write state.
OS transistor (45_{pn + i}, 47_{pn + i}, 48_{pn + i}Four
9_{pn + i}Column selection signal (C
L₁, CL₂... CL_{m + 1}) Is configured to be supplied
A semiconductor memory device characterized by being provided. 3. The first, second ... mn + n (where n =
Bit line pair (38, integer of 2 or more, m = 0 or more)
₁, 38₂... 38_{mn + n}) To the first, second ...
n read data bus line pair (39₁, 39₂... 39
_n) And a write data bus line pair (40₁, 40₂...
40_n) Is provided and the first, second ... mnth
+ N bit line pair (38₁, 38₂... 38_{mn + n}) To
The first, second ... mn + n lead columns.
Gate (41₁, 41₂... 41_{mn + n}) And light
Ramgate (42₁, 42₂... 42_{mn + n}), The first
pn + i (provided that p = 0 to m is an integer, i = 1 to n is an integer
The number of read column gates is 1st, 2nd, 3rd, 3rd,
4 MOS transistor (44_{pn + i}, 45_{pn + i}, 46
_{pn + i}, 47_{pn + i}), And the first and second MO
S transistor (44_{pn + i}, 45_{pn + i}) The predetermined wiring
(50) and the i-th read data bus line pair (39_i)of
One read data bus line (/ RDB_i) And order
Connected in series with the first MOS transistor (44
_{pn + i}) With the gate of pn + i bit line pair (38_{pn + i})
One bit line (BL_{pn + i}) And the above
Third and fourth MOS transistors (46_{pn + i}Four
7_{pn + i}) Is the predetermined wiring (50) and the i-th lead
Data bus line pair (39_i) The other read data
Line (RDB_i) And in series in order,
MOS transistor (46_{pn + i}) Gate to the p-th
n + i bit line pair (38_{pn + i}) Other bit line (/
BL_{pn + i}), And the pn + i write column game for writing
To (42_{pn + i}) Is the second and fourth MOS transistors
(45_{pn + i}, 47_{pn + i}) Than the threshold voltage
High fifth and sixth MOS transistors (48_{pn + i}, 49
_{pn + i}), And the fifth MOS transistor
(48_{pn + i}) Is the pn + i-th bit line pair (3
8_{pn + i}) One bit line (BL_{pn + i}) And the i-th light
Data bus line pair (40_i) One write data buffer
Line (WDB_i) And the sixth
MOS transistor (49_{pn + i}) Is the pn + i-th
Line pair (38_{pn + i}) Other bit line (/ BL_{pn + i})
And the i-th write data bus line pair (40_i) The other
Write data bus line (WDB_i) And
The first, second ... mn + n read column games
To (41₁, 41₂... 41_{mn + n}) And light column
Gate (42₁, 42₂... 42_{mn + n}) Is the first and second
... Nth read column gate (41₁, 41₂・ ・
・ 41_n) And a column gate for light (42₁, 42₂・
・ ・ 42_n) Karunaru group, n + 1, n + 2.
..Column gates for the (n + n) th read (41_{n + 1}, 41
_{n + 2}... 41_n+_n) And a column gate for light (42
_{n + 1}, 42_{n + 2}... 42_{n + n}Group consisting of ...
.., mn + 1, mn + 2 ... mn + n lead
Column gate (41_{mn + 1}, 41_{mn + 2}... 41_{mn + n})
And column gate for light (42_{mn + 1}, 42_{mn + 2}...
42_{mn + n}), Each as a unit,
The first, second, ...
m + 1 logic gate (43₁, 43₂... 43_{m + 1}) To
From the second, fourth, fifth and sixth MOS transistors
(45_{pn + i}, 47_{pn + i}, 48_{pn + i}, 49_{pn + i}) Game
On the other hand, when reading, the second and fourth MOS transistors
Register (45_{pn + i}, 47_{pn + i}) The conducting state, the first
5, 6th MOS transistor (48_{pn + i}, 49_{pn + i})
Is non-conducting, and at the time of writing, the second, fourth, and
5, 6th MOS transistor (45_{pn + i}, 47_{pn + i},
48_{pn + i}, 49 _{pn + i}) Level column that makes the
Selection signal (CL₁, CL₂... CL_{m + 1}) Is supplied
Semiconductor memory device characterized by being configured as follows.
Place 4. First, second ... mn + n (where n =
Bit line pair (38, integer of 2 or more, m = 0 or more)
₁, 38₂... 38_{mn + n}) To the first, second ...
n read data bus line pair (39₁, 39₂... 39
_n) And a write data bus line pair (40₁, 40₂...
40_n) Is provided and the first, second ... mnth
+ N bit line pair (38₁, 38₂... 38_{mn + n}) To
The first, second ... mn + n lead columns.
Gate (41₁, 41₂... 41_{mn + n}) And light
Ramgate (42₁, 42₂... 42_{mn + n}), The first
pn + i (provided that p = 0 to m is an integer, i = 1 to n is an integer
The number of read column gates is 1st, 2nd, 3rd, 3rd,
4 MOS transistor (44_{pn + i}, 45_{pn + i}, 46
_{pn + i}, 47_{pn + i}), And the first and second MO
S transistor (44_{pn + i}, 45_{pn + i}) Lead to i
Data bus line pair (39_i) One read data
Line (/ RDB_i) And the predetermined wiring (50) in order
Connected in series, the first MOS transistor (44
_{pn + i}) With the gate of pn + i bit line pair (38_{pn + i})
One bit line (BL_{pn + i}) And the above
Third and fourth MOS transistors (46_{pn + i}Four
7_{pn + i}) Is the i-th read data bus line pair (3
9_i) Other read data bus line (RDB)_i) And the above
Connect in series with a predetermined wiring (50) in order,
3 MOS transistor (46_{pn + i}) Gate to the above
pn + i bit line pair (38_{pn + i}) The other bit line
(/ BL_{pn + i}), And the pn + i write column
Gate (42_{pn + i}) Is the second and fourth MOS transistors
Dista (45_{pn + i}, 47_{pn + i}) Than threshold electric
The fifth and sixth transistors (48_{pn + i}, 49
_{pn + i}), And the fifth MOS transistor
(48_{pn + i}) Is the pn + i-th bit line pair (3
8_{pn + i}) One bit line (BL_{pn + i}) And the i-th light
Data bus line pair (40_i) One write data buffer
Line (WDB_i) And the sixth
MOS transistor (49_{pn + i}) Is the pn + i-th
Line pair (38_{pn + i}) Other bit line (/ BL_{pn + i})
And the i-th write data bus line pair (40_i) The other
Write data bus line (WDB_i) And
The first, second ... mn + n read column games
To (41₁, 41₂... 41_{mn + n}) And light column
Gate (42₁, 42₂... 42_{mn + n}) Is the first and second
... Nth read column gate (41₁, 41₂・ ・
・ 41_n) And a column gate for light (42₁, 42 ₂・
・ ・ 42_n), A group consisting of n + 1, n + 2.
..Column gates for the (n + n) th read (41_{n + 1}, 41
_{n + 2}... 41_n+_n) And a column gate for light (42
_{n + 1}, 42_{n + 2}... 42_{n + n}Group consisting of ...
.., mn + 1, mn + 2 ... mn + n lead
Column gate (41_{mn + 1}, 41_{mn + 2}... 41_{mn + n})
And column gate for light (42_{mn + 1}, 42_{mn + 2}...
42_{mn + n}), Each as a unit,
The first, second, ...
M + 1th logic gate (43₁, 43₂... 43_{m + 1})
The second, fourth, fifth and sixth MOS transistors
Star (45_{pn + i}, 47_{pn + i}, 48_{pn + i}, 49_{pn + i})
When reading, the second and fourth MOS transistors
Langista (45_{pn + i}, 47_{pn + i}) The conducting state, the first
5, 6th MOS transistor (48_{pn + i}, 49_{pn + i})
Is non-conducting, and at the time of writing, the second, fourth, and
5, 6th MOS transistor (45_{pn + i}, 47_{pn + i},
48_{pn + i}, 49_{pn + i}) Level column that makes the
Selection signal (CL₁, CL₂... CL_{m + 1}) Is supplied
Semiconductor memory device characterized by being configured as follows.
Place 5. The predetermined wiring (50) is grounded at the time of reading, and at the time of writing, the predetermined wiring is connected via a read column gate of a column selected from a precharged read data bus line pair. 5. The semiconductor memory device according to claim 1, wherein the voltage is set to a value that can suppress the current flowing through the wiring (50). 6. The column selection signals (CL ₁ , CL ₂ ...
The level at the time of reading CL _{m + 1} ) is the bit line pair (3
8. The semiconductor memory device according to claim 1, wherein the precharge voltage is close to 8 ₁ , 38 ₂ ... 38 _{mn + n} ). 7. The column selection signals (CL ₁ , CL ₂ ...
7. The semiconductor memory device according to claim 1, wherein the level when CL _{m + 1} ) is read is higher than the power supply voltage. 8. A column selection signal (CL
₁ , CL ₂ ... CL _{m + 1} ) outputs a voltage at the same level as the level at the time of reading, and at the time of writing, at the time of writing the column selection signals (CL ₁ , CL ₂ ... CL _{m + 1} ). A voltage generation circuit that outputs a voltage of the same level as the above-mentioned level, and generates the column selection signals (CL ₁ , CL _2, ... CL _{m + 1} ) based on the voltage output from the voltage generation circuit. 8. The semiconductor memory device according to claim 1, 2, 3, 4, 5, 6 or 7. 9. A first voltage generating circuit which outputs a voltage of the same level as the level at the time of reading the column selection signals (CL ₁ , CL ₂ ... CL _{m + 1} ), A second voltage generating circuit that outputs a voltage at the same level as the column selection signals (CL ₁ , CL _2, ... CL _{m + 1} ) at the time of writing, and the first voltage generating circuit at the time of reading The second voltage generation circuit is inactivated while being connected to the output end, and the connection between the first voltage generation circuit and the output end is disconnected and the second voltage generation circuit is activated at the time of writing. And a voltage generation control circuit for controlling the voltage at the output terminal from the voltage at the same level as the column selection signal (CL ₁ , CL ₂ ... CL _{m + 1} ) at the time of writing when the write period ends. The column selection signal (C
L ₁ , CL ₂ ... CL _{m + 1} ) and a reset circuit for forcibly resetting to a voltage at the same level as the read level.
The semiconductor memory device described in 3, 4, 5, 6, 7 or 8. 10. A first voltage generating circuit which outputs a first voltage, a second voltage generating circuit which outputs a second voltage higher than the second voltage, and in a first mode. , The first voltage generating circuit is connected to the output terminal, the second voltage generating circuit is inactivated, and in the second mode,
A voltage generation control circuit that disconnects the connection between the first voltage generating circuit and the output terminal and activates the second voltage generating circuit, and the output terminal when the second mode period ends. And a reset circuit for forcibly resetting the voltage of 2 from the second voltage to the first voltage.