JPH1040683A - Multi-bank memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the setup time margin of a bank address by minimizing the load effect of a bank information line and to provide a stable action by reliably blocking the failure generation of data access. SOLUTION: When the first terminal of an NMOS transistor M2 is applied with a voltage level VDD, the self boosting node N is precharged from 0V to the voltage VDD minus Vtn. After that, when the voltage of the global column selection line GCSL is changed from 0V to the voltage VDD, the self- boosting node N is self-boosted at a sufficient level. And when the self-boosting node N is self-boosted to more than the voltage plus Vtn, the CMOS level of the global selection line is transmitted to the local column selection line LCSL. After the row address strobe signal changes to the active state of low level, the level of the voltage VPP of the bank information is kept constant every time the bank address changes during the long active period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-bank memory device having a self-voltage boosting function for supplementing a decrease in a column selection line driving voltage due to line loading when a bank address is specified.

[0002]

2. Description of the Related Art In recent years, a memory device often employs a multi-bank structure in which banks are assembled in order to realize high speed and high integration. In this multi-bank structure, a large number of cell arrays are composed of a large number of blocks, and the blocks are arranged in a column direction and a row direction to form one bank. Research is being conducted to reduce the load effect generated by combining a large number of banks and to access data stably. That is, research for improving the stability of the operation of the memory device is in progress.

FIG. 4 is an overall block diagram of a conventional semiconductor memory device having a multi-bank structure. In FIG. 4, in this multi-bank structure, a plurality of bank dummies and a plurality of bank dummies are provided side by side, and data input D
It has a plurality of column decoders CD0 to CDn provided independently for each of Q1 to DQn. Further, in this multi-bank structure, a global column selection line a is provided for a large number of banks to use output signals of a plurality of row decoders BD0 to BDn and column decoders CD0 to CDn provided for each bank.

FIG. 5 is a detailed circuit diagram for explaining a conventional multi-bank memory device. In FIG. 5, the multi-bank memory device includes a first bank and a second bank in which left and right same-shaped partial circuits are assembled.
The partial circuit 100 is connected between the global column selection line a and the source voltage source, and is transmitted through the first and second bank selection lines b composed of two lines.
It has a local column selection line drive circuit 110 that generates a column selection control signal in response to the negative bank information Bank0 and BankOB. Here, the positive bank information switches at the level of the voltage VPP, and the negative bank information switches at the CMOS level.

The multi-bank memory device is connected to a plurality of local input / output (LOCAL I / O) lines c and bit lines of the bank memory, respectively.
A column selection unit 120 including a plurality of NMOS transistors M3 to M6 driven simultaneously in response to a column selection control signal, and connected to each of a plurality of local input / output lines c, Multiple global input / output (GLOVAL I / O) including a sense amplifier (not shown) that amplifies the bit signal transmitted from the output line
And a line d.

FIG. 6 is a detailed circuit diagram of the conventional local column selection line driving circuit 110 shown in FIG. FIG.
In this, the local column selection line driving circuit 11
0 indicates that the first terminal has the global column selection line G (GLOVA
L) The NMO connected to the CSL, the second terminal connected to the local column selection line L (LOCAL) CSL, and the third terminal connected to the first bank selection line L1
It has an S transistor M1. Further, the first terminal is connected to the local column selection line LCSL, and
The second terminal is grounded and the second bank selection line L
2 has an NMOS transistor M2 connected to a third terminal.

Next, a general operation of the multi-bank memory device configured as described above will be described. 4 to 6, first, the column decoders CD0 to CDn
Designates a global column selection line GCSL, and the positive bank information Ban is transmitted through the bank selection line.
When k0 is input, the voltage VDD is applied to the first terminal of the NMOS transistor M1 in the local column selection line driving circuit 110, the voltage VPP is applied to the third terminal, and the NMOS transistor M1 is turned on. At this time, since the NMOS transistor M2 is turned off, the local column selection line driving circuit 110 is pulled up to the level of the voltage VDD.

A plurality of NMOs are provided by this pull-up voltage.
The S transistors M1 to M4 are turned on at the same time, and the bit signal of the bank is loaded to the global input / output line d via the local input / output line c shown in FIG. Thereafter, the signal is amplified and output by a sense amplifier (not shown).

FIG. 7 is a timing chart of the operation of the conventional multi-bank memory device. In FIG. 7, after the row address strobe signal RASB changes to an active state of a low level, the voltage VPP level of the bank information ADD, BANK1 is kept at a constant level every time the bank address (column address) CASB changes during a long active period. Reduce. That is, it is reduced to a level at which data access failure occurs.

As described above, the charge of the bank information switching at the voltage VPP level disappears due to the loading of the bank selection line, and the level of the voltage VPP decreases by a fixed amount every time the bank address changes. Therefore, the voltage level of the bank information is reduced at the time of reading the cell data, and a data access failure occurs. In other words, the low voltage margin deteriorates.

Also, the voltage VPP generator cannot compensate for the charge of the voltage VPP consumed when the bank address keeps changing during the active period of the long row address strobe, thereby causing a data access failure.

In order to configure a bank information voltage VPP generator controlled by a column address strobe in an active period of a long row address strobe, a cycle time for performing pumping of a pumping capacitance of the VPP generator and a precharge operation. Needs to be reduced sufficiently.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the prior art, and has a self-voltage boosting function capable of supplementing a decrease in a column selection line drive voltage due to line loading at the time of bank address designation. To improve the setup time margin of the bank address by minimizing the load effect of the bank information line, and to prevent the failure of the data access without fail, thereby achieving a stable operation of the multi-bank memory device. It is intended to be provided.

[0014]

To achieve the above object, the present invention provides a local column selection line driving circuit, a local column selection line for transmitting a local column selection signal, and a global column for transmitting a global column selection signal. A multi-bank memory device including a selection line and first and second bank selection lines transmitting first and second bank selection signals having CMOS levels, wherein a local column selection line driving circuit includes a local column selection line and a ground. And a pull-down means for pulling down the local column selection line in response to the second bank selection signal transmitted through the second bank selection line. Furthermore, it is connected between the first bank selection line and the self-boosting node, and precharges the self-boosting node to a voltage lower than the power supply voltage level of the CMOS level in response to the active leading edge of the first bank selection signal. The precharge means is connected between the global column select line and the local column select line, and self boosts the self boosting node to a voltage level higher than the power supply voltage level in response to the active leading edge of the global column select signal. And a pull-up means for pulling up the local column selection line to the power supply voltage.

Further, the present invention provides a plurality of cell arrays, a plurality of array groups including the plurality of cell arrays,
A plurality of memory blocks including a plurality of array groups, a plurality of memory banks including a plurality of memory blocks, and a CMOS-level bank selection signal for selecting from the plurality of memory banks are generated on a plurality of bank selection lines. And a plurality of row decoders for selecting the word line of the cell array belonging to the selected memory bank. Further, the same as a plurality of column decoders for generating and transmitting a CMOS level global column selection signal for selecting an array group of the same column of a memory block of the same column of a plurality of memory banks to a plurality of global column selection lines. A plurality of global I / O lines shared by the memory blocks in the column and an array group in the same row of each memory block are shared, and a plurality of local I / O lines connected to each global I / O line and each array group A plurality of local column selecting means sharing a local column selecting line and connected between each local input / output line and each cell array;
The local column select line is connected between each global column select line and each local column select line, and responds to the CMOS level bank select signal by the CMOS level global column select signal.
And a plurality of local column selection line driving means driven by the S level voltage.

The configuration of the present invention has a self-voltage boosting processing function capable of supplementing a decrease in the column selection line drive voltage due to line loading when a bank address is specified. Therefore, the load time of the bank information line is minimized, the setup time margin of the bank address is improved, and the occurrence of data access failure can be reliably prevented, so that the device operates stably.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the multi-bank memory device of the present invention will be described in detail with reference to the accompanying drawings. In the following text and drawings, the same components as those shown in FIGS. 4 to 7 are denoted by the same reference numerals. Hereinafter, FIG. 5 showing the entire configuration of the multi-bank memory device will be repeatedly described, and the description thereof will be omitted.

FIG. 1 is a circuit diagram showing a detailed configuration of the multi-bank memory device of the present invention. In FIG. 1, the multi-bank memory device has a first bank and a second bank in which left and right same-shaped partial circuits are assembled. The partial circuit 100 of the bank is connected between the global column selection line a and the source voltage source, and includes first and second lines,
It has a local column selection line drive circuit 110 that generates a column selection control signal in response to the positive / negative bank information Bank0 and BankOB transmitted through the second bank selection line b.

Further, the multi-bank memory device includes:
A plurality of transistors M connected in correspondence with the plurality of local input / output lines c and the bit lines of the bank memory and driven simultaneously in response to a column selection control signal.
3 to M6, and a plurality of global input / output units, each of which is connected to each of the plurality of local input / output lines c and has a sense amplifier (not shown) for amplifying a bit signal transmitted from the local input / output line. And an output line d.

FIG. 2 is a circuit diagram showing a detailed configuration of the local column selection line driving circuit 110 in FIG. FIG.
In this, the local column selection line driving circuit 11
0 is connected between the local column selection line LCSL and the ground, and includes a pull-down unit 111 for pulling down the local column selection line LCSL in response to the second bank selection signal transmitted through the second bank selection line L2. And connected between the first bank selection line L1 and the self-boosting node N, and the self-boosting node is lower than the power supply voltage level of the CMOS level in response to the active leading edge of the first bank selection signal. It has a precharge means 112 for precharging to a voltage.

Further, the local column selection line driving circuit 110 includes a global column selection line GCSL.
And a local column selection line LCSL connected between the local column selection line LCSL and self-boosting node N at a voltage level higher than the power supply voltage level in response to the active leading end of the global column selection signal. It has a pull-up means 114 for sufficiently pulling up to a voltage.

The pull-down means 111, the pre-charge means 112 and the pull-up means 114 are respectively NM
It comprises OS transistors M1, M2 and M3, and corresponds to the first, second and third NMOS transistors in the claims.

Next, the operation of the configuration of the embodiment will be described. When the level of the voltage VDD is applied to the first terminal of the NMOS transistor M2, the self-boosting node N is precharged from 0V to “voltage VDD−Vtn”. Thereafter, when the voltage of the global column selection line GCSL changes from 0 V to the voltage VDD,
Self-boosting node N is self-boosted at a sufficient level. Then, when the self-boosting node N is boosted to “voltage VDD + Vtn” or more, the CMOS level of the global column selection line is transmitted to the local column selection line LCSL.

FIG. 3 is a timing chart of the operation of the multi-bank memory device of this embodiment. In FIG. 3, after the row address strobe signal RASB changes to an active state of low level, even if the bank address (column address) CASB changes in a long active period, the level of the voltage VPP of the bank information ADD, BANK1 is kept constant. Will be retained. Incidentally, in the conventional example, as shown in FIG.
The PP level is reduced by a fixed amount to a level at which data access failure occurs.

[0025]

As is apparent from the above description, according to the present invention, the bank information voltage for driving the local column selection line driving circuit is not required, and the self-voltage boosting function can be used when the bank address changes. The charge of the bank information voltage can be reliably removed by loading the bank designation line. As a result, the load effect of the bank information line can be minimized, the setup time margin of the bank address can be improved, and the failure of data access can be reliably prevented, and the stable operation can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a multi-bank memory device of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a local column selection line driving circuit in FIG.

FIG. 3 is a timing chart showing an operation state of the multi-bank memory device of the embodiment.

FIG. 4 is an overall block diagram of a conventional semiconductor memory device having a multi-bank structure.

FIG. 5 is a detailed circuit diagram for explaining a conventional multi-bank memory device.

FIG. 6 is a main part circuit diagram for explaining a conventional local column selection line drive circuit.

FIG. 7 is a timing chart of the operation of the conventional multi-bank memory device.

[Explanation of symbols]

 110 Local column select line drive circuit 111 Pull down means 112 Precharge means 114 Pull up means LCSL Local column select line GCSL Global column select line

Claims (8)

[Claims] A local column selection line driving circuit;
A first column having a CMOS level, a local column selection line transmitting a local column selection signal, a global column selection line transmitting a global column selection signal,
And a multi-bank memory device having first and second bank selection lines for transmitting a second bank selection signal, wherein the local column selection line driving circuit is connected between the local column selection line and ground, The second transmitted through the second bank select line
A pull-down means for pulling down the local column select line in response to a bank select signal; connected between the first bank select line and a self-boosting node, in response to an active tip of the first bank select signal The self-boosting node is C
A precharge means for precharging to a voltage lower than a power supply voltage level of a MOS level; a precharge means connected between the global column select line and the local column select line; A multi-bank memory device comprising: a pull-up means for self-boosting a boosting node to a voltage level higher than a power supply voltage level to pull up the local column selection line to a power supply voltage. 2. The multi-bank memory device according to claim 1, wherein the pull-up unit, the pull-down unit, and the precharge unit are configured by NMOS transistors. 3. A plurality of cell arrays, a plurality of array groups including the plurality of cell arrays, a plurality of memory blocks including the plurality of array groups, and a plurality of memory blocks including the plurality of memory blocks A memory bank; and a plurality of row decoders for generating and transmitting a CMOS level bank select signal to be selected from the plurality of memory banks to a plurality of bank select lines, and for selecting a word line of a cell array belonging to the selected memory bank. A plurality of column decoders for generating and transmitting a CMOS level global column selection signal to a plurality of global column selection lines for selecting an array group of the same column of a memory block of the same column of the plurality of memory banks; Multiple global I / O lines shared by memory blocks in the same column And a plurality of local input / output lines connected to the global input / output lines, and a local column selection line for each array group, and A plurality of local column selecting means connected between each of the local input / output lines and each cell array; a plurality of local column selecting means connected between each of the global column selecting lines and each of the local column selecting lines;
A plurality of local column selection line driving means for driving said local column selection line with a CMOS level voltage in response to said CMOS level global column selection signal in response to a level bank selection signal. Memory device. 4. Each of the local column selection line driving means is connected between the local column selection line and a ground, and is connected to the second bank selection line.
A first NMOS transistor that pulls down the local column selection line in response to a bank selection signal; a first NMOS transistor connected between the first bank selection line and a self-boosting node; A second NMOS transistor for precharging the self-boosting node to a voltage lower than a power supply voltage level of a CMOS level; and a second NMOS transistor connected between the global column selection line and the local column selection line; A third NMO for self-boosting the self-boosting node to a voltage level higher than the power supply voltage level in response to a leading end and sufficiently pulling up the local column selection line to the power supply voltage;
4. An S transistor, comprising:
2. The multi-bank memory device according to claim 1. 5. The multi-bank memory device according to claim 3, wherein each of the memory blocks is composed of a 2 × 2 array group. 6. The multi-bank memory device according to claim 5, wherein each of the array groups comprises four cell arrays. 7. The multi-bank memory device according to claim 5, wherein each memory block has a cell array disposed between a pair of local input / output lines. 8. The multi-bank memory device according to claim 7, wherein each of said cell arrays is alternately arranged with a pair of cell arrays of a different array group.