JPH09180467A - Data readout method in ferroelectric memory and ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a ferroelectric memory in which a dummy cell is not required and whose life is made long by a method wherein, when the ferroelectric memory is read out, different electric fields are applied sequentially so that a ferroelectric capacitor charges its polarization according to a change in the electric fields and a change in the polarization of the ferroelectric capacitor is detected. SOLUTION: When data is read out from a memory cell 29 at a ferroelectric memory, bit lines BL's, the inverse of BL's are precharged to VCC/2, a cell transistor 33 is then turned on, a voltage which is applied to a plate electrode 31B at a ferroelectric capacitor 31 is changed from Vcc /2 to VH to VL and to VCC,/2. When '1' is written in the capacitor 31, a voltage VBL at the bit line BL is raised to Vcc /2+Vα . When '0' is written it is lowered to VCC/2-VB, and the voltage difference between the bit line BL and the inverse of BL is amplified by a sense amplifier 43. Thereby, in the same manner as a DRAM of a type in which a bit line is precharged to VCC/2, data can be detected, a dummy cell which is easy to fatigue is not required, and a long-term operation can be maintained stably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reading data in a ferroelectric memory and a ferroelectric memory, and more particularly to a ferroelectric capacity memory using a ferroelectric such as Pb (ZR, Ti) O _3. The present invention relates to a data reading method and a ferroelectric memory in a ferroelectric memory including a memory cell as a medium.

The present invention also relates to a data reading method and a ferroelectric memory in a ferroelectric memory that can perform a stable read operation while ensuring a signal margin when reading data.

[0003]

2. Description of the Related Art A semiconductor memory using a ferroelectric substance such as Pb (Zr, Ti) O ₃ for a capacitor is excellent in that it is non-volatile and has a write / read speed equivalent to that of a DRAM. Therefore, large future demand is expected.

Regarding the operation system of the ferroelectric memory, several types are known, for example, US Pat. No. 4,8.
73,664 (Ramtron), Japanese Examined Patent Publication 7-138
No. 77 (Toshiba) etc. In these methods, a voltage is applied to the ferroelectric capacitor and the data is discriminated by reversing the polarization. When the memory cell is configured by one transistor and one capacitor, it is necessary to configure the reference circuit (dummy cell) that generates an intermediate load by the ferroelectric capacitor in order to determine whether the polarization is inverted. is there. However, the characteristics of this circuit are likely to change due to variations in the process of the ferroelectric film and inversion fatigue. Therefore, there is a problem that the signal margin is reduced and a stable read operation cannot be performed.

The detailed operation of the above-mentioned conventional ferroelectric memory will be described below. FIG. 23 is a circuit diagram showing a main part of an example of a conventional ferroelectric memory. 23, 1 and 2 are memory cells, 3 and 4 are ferroelectric capacitors, 5 and
Reference numeral 6 is a transistor forming a transfer gate, that is, a so-called cell transistor.

Further, WL0 and WL1 are word lines for selecting a memory cell, and PL0 and PL1 are plate lines for driving a plate electrode of a ferroelectric capacitor of the selected memory cell. Further, 7 and 8 are dummy cells, 9 and 10 are ferroelectric capacitors whose opposing areas of the electrodes are 1/2 of those of the ferroelectric capacitors 3 and 4, 11 and 1
2 is a cell transistor. In this example, a logical 1 (hereinafter referred to as “1”) is written in the ferroelectric capacitors 9 and 10.

DWL0 and DWL1 are word lines for selecting dummy cells, and DPL0 and DPL1 are plate lines for driving the plate electrodes of the ferroelectric capacitors of the selected dummy cells. Further, BL and / BL are bit lines forming a data line (data transmission line), and 13 is a voltage difference between the bit lines BL and / BL which is amplified when a data is read and is read from a selected memory cell. It is a sense amplifier that detects the data.

/ BL represents a bit line that provides a reference voltage for the bit line BL, and the potential difference between the bit lines BL and / BL can represent data. 24 and 25
FIG. 3 is a diagram for explaining writing of data to a memory cell in this ferroelectric memory, taking as an example the writing of data to the memory cell 1, and the horizontal axis indicates the plate line P.
The voltage of the bit line BL with respect to L0, ie, the voltage V _BL of the bit line BL with respect to ground-the plate line PL with respect to ground
0 voltage VPL0, vertical axis shows polarization P of the ferroelectric capacitor 3
Is shown.

For example, when "1" is written in the memory cell 1, the voltage VPL0 of the plate line PL0 is set to 0V, the cell transistor 5 is turned on, and the bit line BL is set.
Of the voltage V _BL of 0V → VCC → 0V. In this way, the state of polarization P of the ferroelectric capacitor 3 is
As shown in FIG. 24, the polarization changes from point a to point b to point c, the polarization P of the ferroelectric capacitor 3 becomes a positive polarization PS, and the ferroelectric capacitor 3 stores "1". become. It should be noted that the closed curve consisting of b point → c point → d point → e point → b point shows a hysteresis loop.

On the other hand, when "0" is written in the memory cell 1, the voltage V _BL of the bit line BL is set to 0V,
With the cell transistor 5 in the conductive state, the plate line PL
The voltage VPL0 of 0 is changed from 0V → VCC → 0V. By doing so, the storage electrode 3A of the ferroelectric capacitor 3
Of the plate electrode 3B is 0V → −VCC →
The polarization P of the ferroelectric capacitor 3 changes to 0 V and the polarization P of FIG.
As shown in FIG. 5, the polarization P of the ferroelectric capacitor 3 changes to a negative polarization −PS, and the ferroelectric capacitor 3 stores “0”. become.

FIG. 26 is a waveform diagram for explaining a method of reading data from a memory cell in this ferroelectric memory, taking data reading from the memory cell 1 as an example, and FIG. 26A is a word line. FIG. 26B shows voltage changes on the WL0 and DWL0, FIG. 26B shows voltage changes on the plate lines PL0 and DPL0, and FIG. 26C shows voltage changes on the bit line BL.

That is, when reading data from the memory cell 1, the bit lines BL and / BL are set to 0V, the word lines WL0 and DWL0 are raised to VCC + VTH (threshold voltage of cell transistor), and the cell transistor 5 and 11 is made conductive, and then the plate line PL
0, DPL0 is raised to VCC.

Here, for example, when "1" is written in the ferroelectric capacitor 3, the polarization P of the ferroelectric capacitor 3 changes from point c to point K1 as shown in FIG. and, i.e., to move the voltage V _BL of the bit line BL, the amount of charge ΔQ1 ferroelectric capacitor 3 that the intensity and the voltage of the storage electrode 3A of the ferroelectric capacitor 3 is equal to the bit line BL, the bit line BL The voltage V _BL rises from 0V to V1.

On the other hand, when "0" is written in the ferroelectric capacitor 3, the polarization P of the ferroelectric capacitor 3 changes from the point e to the point K2, that is, the bit line BL. Of the electric charge ΔQ2, which is equal to the voltage V _BL of the storage capacitor 3A of the ferroelectric capacitor 3, moves from the ferroelectric capacitor 3 to the bit line BL,
The voltage V _BL of V rises from 0V to V2.

In this case, the facing area of the electrodes of the ferroelectric capacitor 9 in the dummy cell 7 is 1/2 of that in the case of the ferroelectric capacitor 3 in the memory cell 1, and the ferroelectric capacitor 9 has "1". Since it has been written, the voltage V _{/ BL} of the bit line / _BL has an intermediate value between V1 and V2. This serves as a reference voltage (function of the dummy cell).

Therefore, when "1" is written in the ferroelectric capacitor 3, the sense amplifier 13
Since V _BL (= V1) is larger than V _{/ BL} , the voltage V _BL of the bit line BL is raised to VCC and the voltage V _{/ BL} of the bit line / BL is lowered to 0V.

On the other hand, when "0" is written in the ferroelectric capacitor 3, the sense amplifier 13
Since V _BL (= V2) is smaller than V _{/ BL} , the voltage V _BL of the bit line BL is lowered to 0V and the voltage V _{/ BL} of the bit line / BL is raised to VCC.

Next, the operation method of the ferroelectric memory disclosed in Japanese Patent Publication No. 7-13877 (Toshiba) mentioned above will be further described. This operation method is "Vcc /
(2) Proposal of operation system of non-volatile ferroelectric memory that enables two common plates "(Proceedings of the Electronics Society Conference of the Institute of Electronics, Information and Communication Engineers 1995, C-509).

The ferroelectric memory proposed here is
It has a cell structure similar to that of a DRAM using a ferroelectric film for a capacitor. This ferroelectric memory is usually a DRAM
The information is stored by remanent polarization when the power is turned off, and is read when the power is turned on. Therefore, this ferroelectric memory can be used as a non-volatile memory.

The above ferroelectric memory will be described below in more detail. When the ferroelectric memory operates as a DRAM, data is stored not by the remanent polarization of the capacitor but by the electric charge accumulated in the linear capacitance.
At this time, the plate potential is fixed to Vcc / 2, and the potential of the storage node becomes Vcc or 0V according to the data. In this case, when the memory operates as DRAM, refreshing is required.

Subsequently, when the power is turned off, the data is retained as remanent polarization. Furthermore, when the power is turned on, the remnant polarization is converted into accumulated charges, so that after all cells have been read (in FRAM mode), the memory is set in DRAM mode. At this time,
Plate potential is set to Vcc / 2 and bit line is 0V
Precharged. In addition, the word line is selected,
When the potential is raised and the bit line and the capacitor are connected, the potential of the bit line rises above 0V. But,
Since the width differs depending on the direction of polarization inversion, the data is discriminated by this difference. In this way, after the data has been read out for all cells, the memory
The M mode is set.

[0022]

Thus, the dummy cell is used as a reference voltage for all the memory cells connected to the bit line. Therefore, in this ferroelectric memory, the dummy cell 7 is driven every time all the memory cells such as the memory cell 1 connected to the bit line BL are selected, and the dummy cell 8 is driven such that the memory cell 2 etc. It is driven each time the memory cell connected to the line / BL is selected.

Therefore, the ferroelectric capacitors 9 and 10 of the dummy cells 7 and 8 undergo inversion fatigue more than the ferroelectric capacitors of normal memory cells such as the ferroelectric capacitors 3 and 4 and the characteristic change thereof causes The read margin becomes small. Here, it is extremely difficult to set a dummy cell in consideration of characteristic change due to inversion fatigue. Therefore, in the conventional ferroelectric memory shown in FIG. 23, it is necessary to secure stable operation for a long period of time. There was a problem that I could not do it.

The facing area of the electrodes of the ferroelectric capacitors 9 and 10 is made twice as large as that of the memory cells 3 and 4,
A ferroelectric memory in which "0" is written has also been proposed, but this ferroelectric memory also has the same problem as the ferroelectric memory shown in FIG.

The reading method of the ferroelectric memory disclosed in Japanese Patent Publication No. 7-13877 (Toshiba) is Ra
Unlike the mtron method, the potential of the bit line is changed instead of driving the plate line. However, also in this case, a dummy cell for generating a reference potential is required to determine the presence or absence of polarization inversion. Therefore, the characteristics of the dummy cell affect the read reliability. Especially DR
Since the voltage applied to the capacitor is Vcc / 2, which is low for compatibility with the AM mode, there is a problem that the signal voltage is low and a read error is likely to occur.

In view of the above point, the present invention eliminates the need for the dummy cell required for detecting the data read from the memory cell, and ensures the stable operation for a long period of time. An object of the present invention is to provide a method of reading data in a body memory and a ferroelectric memory.

Another object of the present invention is to provide a ferroelectric memory and a method of reading data in the ferroelectric memory, in which fatigue of the dummy cell is reduced and stable operation can be secured for a long period of time. The purpose is to

[0028]

According to a first aspect of the present invention, there is provided a method of reading data in a ferroelectric memory according to the present invention, wherein the ferroelectric memory includes a memory cell having a ferroelectric capacitor as a storage medium. A method of reading data in, wherein the ferroelectric capacitor changes polarization in response to a change in electric field, the first direction being reversed,
The second electric field is sequentially applied to the ferroelectric capacitor and the change in polarization of the ferroelectric capacitor is detected to read the data stored in the memory cell.

In the method of the present invention as defined in claim 2,
A transfer gate whose charge input / output terminal is connected to the data line,
A transfer gate in a ferroelectric memory comprising a memory cell comprising a ferroelectric capacitor having a first electrode connected to a second charge input / output terminal of a transfer gate and a second electrode connected to a drive voltage line. To make the transfer gate conductive after precharging the data line so that the ferroelectric capacitor changes the polarization in response to the change in the electric field.
A drive voltage for sequentially applying first and second electric fields having opposite directions to the ferroelectric capacitor is applied to the second electrode of the ferroelectric capacitor through the drive voltage line, and the memory cell stores the data. The data is read to the data line.

According to the method of reading data in the ferroelectric memory of the present invention, the DRAM (dynamic random) which adopts a method of precharging the data read from the memory cell to, for example, the bit line to VCC / 2.・
It can be detected as in the case of access memory) and does not require a dummy cell.

According to an eighth aspect of the present invention, a ferroelectric memory of the present invention is a ferroelectric memory including a memory cell having a ferroelectric capacitor as a storage medium. Ferroelectric capacitors are obtained by sequentially applying first and second electric fields having opposite directions, which change the polarization correspondingly, to the ferroelectric capacitors and detecting the change in polarization of the ferroelectric capacitors. Is provided with a data reading means for reading the data stored therein.

In the invention device according to claim 9, the first
A transfer gate whose charge input / output terminal is connected to the data line,
A ferroelectric memory comprising a memory cell including a ferroelectric capacitor having a first electrode connected to a second charge input / output terminal of a transfer gate and a second electrode connected to a drive voltage line The precharge means for precharging and the transfer gate are made non-conductive, the data line is precharged by the precharge means, and the ferroelectric capacitor is polarized in response to the change of the electric field with the transfer gate made conductive. A driving voltage for sequentially applying first and second electric fields having opposite directions that change the voltage to the ferroelectric capacitor is applied to the second electrode of the ferroelectric capacitor through the driving voltage line. Drive voltage supply means, the transfer gate is made non-conductive, the data line is precharged, the transfer gate is made conductive, and the first and second electric fields are sequentially applied to the ferroelectric capacitor. And by, is that configured to read the data memory cell stores the data line.

According to the ferroelectric memory of the present invention, the data read from the memory cell, for example, the bit line V
It can be detected similarly to the case of the DRAM adopting the method of precharging to CC / 2, and does not require a dummy cell. In the invention method according to claim 15 and the invention device according to claim 19, in the data read method and the ferroelectric memory of the ferroelectric memory of the present invention described above, the parasitic capacitance C _BL of the data line is logical 1 And logic 0
When the data is read, the potential difference appearing on the data line is set to a value that is substantially the maximum or less.

The invention method according to claim 17 and claim 21
In the invention device described above, in the above-mentioned method for reading out a ferroelectric memory and the ferroelectric memory, the first and second
One of the electric fields of 1 is set to be higher than the internal power supply voltage.

In the ferroelectric memory reading method and the ferroelectric memory of the present invention described above, the capacitance ratio between the data line and the ferroelectric capacitor is optimized, or one of the first and second electric fields is internally set. By increasing the power supply voltage of
A large read signal can be obtained, and a memory element that operates stably for a long time can be realized.

According to a twenty-third aspect of the present invention, a memory cell having a ferroelectric capacitor as a storage medium and a dummy cell having a ferroelectric capacitor are provided, and data is obtained according to a polarization direction of the ferroelectric capacitor of the memory cell. In a method of reading data in a ferroelectric memory in which is stored, (a) a first drive voltage is applied to a ferroelectric capacitor of the memory cell, and (b) the data is stored in the memory cell in accordance with the stored data. One of a first voltage and a second voltage is generated on the data line, and (c) a second driving voltage lower than the first driving voltage is applied to the ferroelectric capacitor of the dummy cell to generate a reference potential. And (d) the step (b)
The first and second voltages generated in 1) are identified based on the reference potential, and the data is read.

According to a thirty-first aspect of the present invention, there is provided a memory cell having a ferroelectric capacitor as a storage medium, and a dummy cell having a ferroelectric capacitor, and data is set according to a polarization direction of the ferroelectric capacitor of the memory cell. Is stored, and one of a first voltage and a second voltage is generated on the data line in accordance with the data at the time of reading, and the first driving voltage is applied to the ferroelectric capacitor of the memory cell. And a second means for generating a reference potential by applying a second drive voltage lower than the first drive voltage to the ferroelectric capacitor of the dummy cell.
And means for reading the data by identifying the first and second voltages generated at the time of reading the data based on the reference potential.

In the above-mentioned reading method and the ferroelectric memory of the ferroelectric memory having the dummy cell according to the present invention,
By setting the second drive voltage of the ferroelectric capacitor of the dummy cell lower than the first drive voltage of the ferroelectric capacitor of the memory cell, the inversion fatigue of the dummy cell is reduced, and stable write and read operations for a long time are performed. Can be achieved.

According to the 39th aspect of the present invention, a ferroelectric capacitor is used, and the DR is substantially used during normal use.
A method of reading data in a non-volatile ferroelectric memory, which operates in an AM mode and retains data by residual polarization of the ferroelectric capacitor when the power is cut off, comprising: (a) a plate electrode when the power is turned on. And the potential of the bit line is substantially equal to the internal power supply voltage (Vcc) of 2
(B) The potential of the plate electrode is set to Vc
c / 2 → (Vcc / 2 + Vα) → (Vcc / 2−Vβ)
→ Vcc / 2, (where Vα and Vβ are the first and second
The data is converted from remnant polarization into accumulated charge holding information in the DRAM mode when the power is turned on.

In the method of the 40th aspect of the present invention, a ferroelectric capacitor is used, and the DR is substantially used during normal use.
A non-volatile ferroelectric memory that operates in an AM mode and retains data by remanent polarization of the ferroelectric capacitor when the power is turned off, and when the power is turned on, the potentials of the plate electrode and the bit line are substantially changed. First voltage setting means for setting the internal power supply voltage (Vcc) to 1/2 and the potential of the plate electrode is Vcc / 2 → (Vc
c / 2 + Vα) → (Vcc / 2−Vβ) → Vcc / 2,
(However, Vα and Vβ are first and second predetermined voltages)
And a second voltage setting means for changing the order of the above, and when the power is turned on, the data is converted from the remnant polarization into the accumulated charge holding information in the DRAM mode.

In the above-mentioned reading method of the nonvolatile ferroelectric memory and the nonvolatile ferroelectric memory according to the present invention, when the power is turned on, the residual polarization of all the memory cells is converted into the accumulated charges, and the data is stored. A recall is performed. Therefore, a stable data read operation can be performed regardless of the characteristics of the dummy cell.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to FIGS.
Embodiments of a method of reading data in a ferroelectric memory and a ferroelectric memory of the present invention will be described. 1 is a circuit diagram showing a main part of an example of an embodiment of a ferroelectric memory of the present invention. In FIG. 1, 20 is a memory cell array in which memory cells are arranged, and 21 is a row address signal decoded. A row decoder for selecting a row.

Further, 22 is a word line drive voltage generation circuit for generating a word line drive voltage φWL for driving the word line,
Reference numeral 23 denotes a plate electrode drive voltage generation circuit that generates a plate electrode drive voltage φPL that drives the plate electrode of the ferroelectric capacitor that constitutes the memory cell.

Further, 24 is provided for each row, and a word plate driver for arranging the word line drive voltage φWL and the plate electrode drive voltage φPL is arranged in the word line and the plate line of the corresponding row, respectively. It is a plate driver row. Reference numeral 25 is a sense amplifier row in which sense amplifiers for detecting the data read from the selected memory cell are arranged.

26 is a column decoder for decoding a column address signal to generate a column selection signal, and 27 is a column selection gate for selecting a column based on the column selection signal output from the column decoder 26. It is a column selection gate column. Further, FIG. 2 shows a memory cell array 20 and a sense amplifier row 25.
3 is a circuit diagram showing a part of a column selection gate column 27. FIG.

In FIG. 2, in the memory cell array 20,
29 and 30 are memory cells, 31 and 32 are ferroelectric capacitors that form a storage medium, and 33 and 34 are cell transistors that are nMOS transistors that form a transfer gate. Further, WL0 and WL1 are word lines for selecting a memory cell, PL0 and PL1 are plate lines for driving the plate electrodes of the ferroelectric capacitors of the selected memory cells, and BL and / BL are data lines ( It is a bit line that forms a data transmission path.

Further, 35 is a precharge circuit for precharging the bit lines BL, / BL, 36 is a precharge voltage line for supplying VCC (power supply voltage) / 2 as the precharge voltage VPR, and 37 is precharge control. Signal φ
A precharge control signal line for transmitting PR, 38 to 40 is controlled to be conductive (hereinafter referred to as ON) or non-conductive (hereinafter referred to as OFF) by the precharge control signal φPR.
It is a MOS transistor.

In the sense amplifier row 25, 41
Is a sense amplifier drive voltage line for supplying the sense amplifier drive voltage φP, 42 is a sense amplifier drive voltage line for supplying the sense amplifier drive voltage φN, and 43 is a sense amplifier.
44 and 45 are pMOS transistors, 46 and 47 are nM
OS transistor.

Further, in the column selection gate column 27, 48
Is a column selection gate, 49 and 50 are nMOS transistors whose ON / OFF is controlled by a column selection signal CL,
IO and / IO are input / output buses shared by a plurality of columns. FIG. 3 is a circuit diagram showing a part of the row decoder 21 and the word plate driver column 24.

In FIG. 3, in the row decoder 21, 52 is a dynamic NAND circuit for decoding the row address signals Xi, Xj, Xk to select the word line WLm and the plate line PLm, and 53 is a reset signal. RP
The pMOS transistors 54, 55, 56 whose ON and OFF are controlled by the row address signals Xi,
An nMOS transistor whose ON / OFF is controlled by Xj and Xk.

In this NAND circuit 52, before decoding, reset signal RP = low level (hereinafter referred to as L level), pMOS transistor 53 state = ON, node 57 is precharged to power supply voltage VCC, During decoding, reset signal RP = high level (hereinafter,
H level), the state of the pMOS transistor 53 =
It is turned off.

When a word line other than the word line WLm is selected, the row address signals Xi, Xj, Xk are selected.
Any of or all of the nMOS transistors 54, 55, 56 are turned off, and the level of the node 57 is maintained at the power supply voltage VCC.

On the other hand, when the word line WLm is selected, all the row address signals Xi, Xj, Xk are at H level, and the nMOS transistors 54, 55, 5 are.
All of 6 are turned on, and the level of the node 57 is set to 0V. In the word plate driver row 24, 58 is a word plate driver for driving the word line WLm and the plate line PLm, and 59 is N.
An inverter for inverting the output of the AND circuit 52, 60, 6
Reference numeral 1 is an nMOS transistor having a gate to which the power supply voltage VCC is applied.

Reference numeral 62 is an nMOS transistor to which the output of the inverter 59 is applied to the gate via the nMOS transistor 60 and the word line drive voltage φWL is applied to the drain. Further, 63 is an inverter 5 at the gate
The output of 9 is applied via the nMOS transistor 61, and the plate electrode drive voltage φPL is applied to the drain.

Further, 64 and 65 are nMOS transistors whose ON and OFF are controlled by the output of the NAND circuit 52, the source of the nMOS transistor 64 is grounded, and VCC / 2 is applied to the source of the nMOS transistor 65. In this example, the word line WLm is connected to the connection point between the source of the nMOS transistor 62 and the drain of the nMOS transistor 64, and the plate line PLm is connected to the connection point between the source of the nMOS transistor 63 and the drain of the nMOS transistor 65. Has been done.

In the word plate driver 24, when the output of the NAND circuit 52 = VCC, that is, when a word line other than the word line WLm is selected, the states of the nMOS transistors 64 and 65 = ON, Output of inverter 59 = 0V, nMOS transistor 6
The states of 2 and 63 = OFF, the voltage of the word line WLm = 0V, and the voltage of the plate line PLm = VCC / 2.

On the other hand, the output of the NAND circuit 52 =
In the case of 0V, that is, when the word line WLm is selected, the states of the nMOS transistors 64 and 65 = OFF,
The output of the inverter 59 = VCC, the states of the nMOS transistors 62 and 63 = ON, and the word line WLm is
Word line drive voltage φ via nMOS transistor 61
WL is supplied, and the plate electrode drive voltage φPL is supplied to the plate line PLm via the nMOS transistor 63.

FIG. 4 is a circuit diagram showing a first configuration example of the plate electrode drive voltage generation circuit 23. The first configuration example of the plate electrode drive voltage generation circuit 23 is a plate electrode drive voltage generation control signal φ1. , Φ2 to generate the plate electrode drive voltage φPL.

In FIG. 4, reference numeral 67 is a NAND circuit for performing NAND processing on the plate electrode drive voltage generation control signals φ1 and φ2,
Reference numeral 68 denotes an inverter that inverts the plate electrode drive voltage generation control signal φ1, and 69 denotes NO that NOR-processes the output of the inverter 68 and the plate electrode drive voltage generation control signal φ2.
It is an R circuit.

Reference numeral 70 denotes a pMOS transistor whose ON / OFF is controlled by the output of the NAND circuit 67,
Reference numeral 1 is an nMOS transistor whose ON / OFF is controlled by the output of the inverter 68, 72 is an nMOS transistor whose ON / OFF is controlled by the output of the NOR circuit 69, and the voltage VH is applied to the source of the pMOS transistor 70. VCC / 2 is applied to the drain of the nMOS transistor 71,
The voltage VL is applied to the source of the.

Here, VH is a voltage higher than VCC / 2, VL is a voltage lower than VCC / 2, and VCC /
If 2 is, for example, 1.5 V, then VH is, for example,
It is set to 2.5V, and VL is set to 1.0V, for example. In this example, the drain of the pMOS transistor 70, the source of the nMOS transistor 71, and the nM
The drains of the OS transistors 72 are commonly connected, and the plate electrode drive voltage φPL is obtained at the connection point.

Further, as the voltage VL and the voltage VH, for example, an internal step-down power supply circuit and an internal step-up power supply circuit shown in FIGS. 36A and 36B described later can be applied. FIG. 5 shows the plate electrode drive voltage generation circuit 2
3 is a waveform diagram showing an operation of the first configuration example of FIG. 3, showing plate electrode drive voltage generation control signals φ1, φ2 and plate electrode drive voltage φPL.

That is, in the first configuration example of the plate electrode drive voltage generation circuit 23, when the plate electrode drive voltage generation control signals φ1 and φ2 = L level, the output of the NAND circuit 67 = H level and the output of the inverter 68. = H level, the output of the NOR circuit 69 = L level.

As a result, in this case, the state of the pMOS transistor 70 = OFF, the nMOS transistor 71
State = ON, nMOS transistor 72 state = OF
F, the plate electrode drive voltage φPL = VCC / 2. From this state, when the plate electrode drive voltage generation control signals φ1, φ2 = H level, the output of the NAND circuit 67 = L level, the output of the inverter 68 = L level, and the output of the NOR circuit 69 = L level is maintained. .

As a result, the state of the pMOS transistor 70 = ON, the state of the nMOS transistor 71 = OFF, the state of the nMOS transistor 72 = OFF is maintained, and the plate electrode drive voltage φPL = VH. From this state, the plate electrode drive voltage generation control signal φ2 = L
At the level, the output of the NAND circuit 67 = H level,
The output of the NOR circuit 69 becomes H level, and the inverter 6
8 outputs = L level is maintained.

As a result, the state of the pMOS transistor 70 = OFF, the state of the nMOS transistor 72 = ON, the state of the nMOS transistor 71 = OFF is maintained, and the plate electrode drive voltage φPL = VL. From this state, the plate electrode drive voltage generation control signal φ1 = L
At the level, the output of the NAND circuit 67 = H level,
The output of the inverter 68 = H level and the output of the NOR circuit 69 = L level.

As a result, the state of the nMOS transistor 71 = ON, the state of the nMOS transistor 72 = OFF, the state of the pMOS transistor 70 = OFF is maintained, and the plate electrode drive voltage φPL returns to the state of VCC / 2. Further, FIG. 6 shows a plate electrode drive voltage generation circuit 2
3 is a circuit diagram showing a second configuration example of No. 3, and a second configuration example of the plate electrode drive voltage generation circuit 23 is that the plate electrode drive voltage φPL is generated based on the plate electrode drive voltage generation control signal φ1. is there.

In FIG. 6, reference numeral 74 denotes an inverting delay circuit for inverting and delaying the plate electrode drive voltage generation control signal φ1, and 75
˜77 are inverters, 78˜80 are resistors, and 81˜83 are capacitors. Reference numeral 84 designates the plate electrode drive voltage generation control signal φ1 and the output φA of the inversion delay circuit 74 as N.
AND circuit for AND processing, 85 is an inverting delay circuit 74
An inverter for inverting the output .phi.A of the plate electrode, 86 a NOR circuit for NOR processing the plate electrode drive voltage generation control signal .phi.1 and the output of the inverter 85, and 87 for the plate electrode drive voltage generation control signal .phi.1 and the output .phi.A of the inversion delay circuit 74. Is a NOR circuit for NOR processing.

Further, 88 is a pMOS transistor whose ON / OFF is controlled by the output of the NAND circuit 84,
Reference numeral 9 is an nMOS transistor whose ON / OFF is controlled by the output of the NOR circuit 86, 90 is an nMOS transistor whose ON / OFF is controlled by the output of the NOR circuit 87, and the voltage VH is applied to the source of the pMOS transistor 88. , VCC / 2 is applied to the drain of the nMOS transistor 89,
The voltage VL is applied to the source of the.

In this example, the drain of the pMOS transistor 88, the source of the nMOS transistor 89, and the drain of the nMOS transistor 90 are commonly connected, and the plate electrode drive voltage φPL is obtained at the connection point. . FIG. 7 is a waveform diagram showing the operation of the second configuration example of the plate electrode drive voltage generation circuit 23. The plate electrode drive voltage generation control signal φ1, the output φA of the inversion delay circuit 74 and the plate electrode drive voltage φPL are shown.
Is shown.

That is, in the second configuration example of the plate electrode drive voltage generation circuit 23, when the plate electrode drive voltage generation control signal φ1 = L level, the output φA = H level of the inversion delay circuit 74 and the NAND circuit 84 output. Output = H level, output of inverter 85 = L level, NOR circuit 86
Output = H level, and the output of the NOR circuit 87 = L level.

As a result, in this case, the state of the pMOS transistor 88 = OFF, the nMOS transistor 89
State = ON, nMOS transistor 90 state = OF
F, the plate electrode drive voltage φPL = VCC / 2. From this state, when the plate electrode drive voltage generation control signal φ1 = H level, the output of the NAND circuit 84 =
L level, the output of the NOR circuit 86 = L level, and N
The output of the OR circuit 87 = L level is maintained.

As a result, the state of the pMOS transistor 88 is ON, the state of the nMOS transistor 89 is OFF, the state of the nMOS transistor 90 is maintained OFF, and the plate electrode drive voltage φPL = VH. After that, when the plate electrode drive voltage generation control signal φ1 becomes L level and the output φA of the inversion delay circuit 74 becomes L level, the output of the NAND circuit 84 becomes H level and the inverter 8
5 output = H level, NOR circuit 87 output = H level, and NOR circuit 86 output = L level is maintained.

As a result, the state of the pMOS transistor 88 is OFF, the state of the nMOS transistor 90 is ON, the state of the nMOS transistor 89 is maintained OFF, and the plate electrode drive voltage φPL = VL. After that, when the output φA of the inverting delay circuit 74 becomes H level,
The output of the inverter 85 = L level, the output of the NOR circuit 86 = H level, the output of the NOR circuit 87 = L level, and the output of the NAND circuit 84 = H level is maintained.

As a result, the state of the nMOS transistor 89 = ON, the state of the nMOS transistor 90 = OFF, the state of the pMOS transistor 88 is maintained OFF, and the plate electrode drive voltage φPL = VCC / 2 is restored. FIG. 8 is a circuit diagram showing a third configuration example of the plate electrode drive voltage generation circuit 23. In the third configuration example of the plate electrode drive voltage generation circuit 23, the plate electrode drive voltage generation control signals φ1, φ2, The plate electrode drive voltage φPL is generated based on φ3 and φ4.

In FIG. 8, reference numeral 92 denotes a NAND circuit for performing NAND processing on the plate electrode drive voltage generation control signals φ1 and φ2,
Reference numeral 93 is an inverter that inverts the plate electrode drive voltage generation control signal φ1;
It is an R circuit.

Further, 95 is a pMOS transistor whose ON / OFF is controlled by the output of the NAND circuit 92, and 9
Reference numeral 6 is an nMOS transistor whose ON / OFF is controlled by the output of the NOR circuit 94. The voltage VH is applied to the source of the pMOS transistor 95, and the voltage VL is applied to the source of the nMOS transistor 96.

Reference numeral 97 is a NAND circuit for performing NAND processing on the plate electrode drive voltage generation control signals φ3 and φ4, and 9
Reference numeral 8 is an inverter for inverting the plate electrode drive voltage generation control signal φ3, and 99 is NOR for NOR processing the output of the inverter 98 and the plate electrode drive voltage generation control signal φ4.
Circuit.

Further, 100 is a pMOS transistor whose ON / OFF is controlled by the output of the NAND circuit 97,
Reference numeral 101 is an nMOS transistor whose ON / OFF is controlled by the output of the NOR circuit 99. The voltage VHH is applied to the source of the pMOS transistor 100, and
The voltage VLL is applied to the source of the OS transistor 101.

Here, VHH is a voltage higher than VH, and VH
LL is a voltage lower than VL, for example, VCC / 2
= 1.5V, VH = 2.5V, VL = 1.0V, VH is set to 3.0V, for example, and VLL is
For example, it is set to 0V. Further, 102 is a NAND circuit for performing NAND processing on the plate electrode drive voltage generation control signals φ1 and φ3, 103 is an nMOS transistor whose ON / OFF is controlled by the output of the NAND circuit 102, and the drain of the nMOS transistor 103 is VCC.
/ 2 is applied.

In this example, the drains of the pMOS transistors 95 and 100, the nMOS transistor 96,
The drain of 101 and the source of the nMOS transistor 103 are commonly connected, and the plate electrode drive voltage φPL is obtained at the connection point.

FIG. 9 is a waveform diagram showing the operation of the third configuration example of the plate electrode drive voltage generation circuit 23. The plate electrode drive voltage generation control signals φ1, φ2, φ3, φ4 and the plate electrode drive voltage φPL are shown in FIG. Shows. That is, in the third configuration example of the plate electrode drive voltage generation circuit 23, the plate electrode drive voltage generation control signals φ1, φ
When 2, φ3, φ4 = L level, output of NAND circuit 92 = H level, output of inverter 93 = H level, N
Output of OR circuit 94 = L level, output of NAND circuit 97 = H level, output of inverter 98 = H level, NO
The output of the R circuit 99 = L level and the output of the NOR circuit 102 = H level.

As a result, in this case, the states of the pMOS transistors 95 and 100 = OFF, the states of the nMOS transistors 96 and 101 = OFF, the states of the nMOS transistor 103 = ON, and the plate electrode drive voltage φ
PL = VCC / 2. From this state, when the plate electrode drive voltage generation control signals φ1, φ2 = H level,
The output of the NAND circuit 92 = L level, the output of the inverter 93 = L level, the output of the NOR circuit 102 = L level, the output of the NOR circuit 94 = L level, the output of the NAND circuit 97 = H level, the output of the inverter 98 = The H level and the output of the NOR circuit 99 = L level are maintained.

As a result, the state of the pMOS transistor 95 = ON and the state of the nMOS transistor 103 = OFF.
And the state of the pMOS transistor 100 = OFF,
The state of the nMOS transistors 96 and 101 = OFF is maintained, and the plate electrode drive voltage φPL = VH.

From this state, when the plate electrode drive voltage generation control signal φ2 = L level, the output of the NAND circuit 92 = H level, the output of the NOR circuit 94 = H level, the output of the NAND circuit 97 = H level, the inverter 9
8 output = H level, NOR circuit 99 output = L level, NOR circuit 102 output = L level.

As a result, the state of the pMOS transistor 95 = OFF, the state of the nMOS transistor 96 = ON, and the state of the pMOS transistor 100 = OFF, n
The state of the MOS transistors 101 and 103 = OFF is maintained, and the plate electrode drive voltage φPL = VL.

From this state, when the plate electrode drive voltage generation control signal φ1 = L level, the output of the inverter 93 = H level, the output of the NOR circuit 94 = L level, NO.
The output of the R circuit 102 becomes H level, and the NAND circuit 9
2 output = H level, NAND circuit 97 output = H level, inverter 98 output = H level, NOR circuit 99
Output = L level is maintained.

As a result, the state of the nMOS transistor 96 = OFF and the state of the nMOS transistor 103 = ON.
And the state of the pMOS transistors 95 and 100 = O
The state of the FF and nMOS transistor 101 = OFF is maintained, and the plate electrode drive voltage φPL returns to VCC / 2.

From this state, when the plate electrode drive voltage generation control signals φ3 and φ4 = H level, the output of the NAND circuit 97 = L level, the output of the inverter 98 = L level, the output of the NOR circuit 99 = L level, NAND
Output of circuit 92 = H level, output of inverter 93 = H
Level, the output of the NOR circuit 94 = L level is maintained.

As a result, the state of the pMOS transistor 100 = ON, the state of the nMOS transistor 103 = OF
F, the state of the pMOS transistor 95 = OFF,
The state of the nMOS transistors 96 and 101 = OFF is maintained, and the plate electrode drive voltage φPL = VHH.

In this state, when the plate electrode drive voltage generation control signal φ4 = L level, the output of the NAND circuit 97 = H level, the output of the NOR circuit 99 = H level, the output of the NAND circuit 92 = H level, the inverter 9
3 output = H level, NOR circuit 94 output = L level, NOR circuit 102 output = L level.

As a result, the state of the pMOS transistor 100 = OFF and the state of the nMOS transistor 101 = O
N, the state of the pMOS transistor 95 = OFF,
The state of the nMOS transistors 96 and 103 = OFF is maintained, and the plate electrode drive voltage φPL = VLL.

From this state, when the plate electrode drive voltage generation control signal φ3 = L level, the output of the inverter 98 = H level, the output of the NOR circuit 99 = L level, NO.
The output of the R circuit 102 becomes H level, and the NAND circuit 9
7 output = H level, NAND circuit 92 output = H level, inverter 93 output = H level, NOR circuit 94
Output = L level is maintained.

As a result, the state of the nMOS transistor 101 = OFF, the state of the nMOS transistor 103 = O
N, the state of the pMOS transistors 95 and 100 =
OFF, the state of the nMOS transistor 96 = OFF is maintained, and the plate electrode drive voltage φPL returns to VCC / 2.

FIGS. 10 and 11 are views for explaining the data writing to the memory cell in the example of the embodiment of the ferroelectric memory of the present invention by taking the data writing to the memory cell 29 as an example. Yes, the horizontal axis represents the voltage V _BL −VPL0 of the bit line BL with respect to the plate line PL0.
The vertical axis indicates the polarization P of the ferroelectric capacitor 31.

For example, when writing "1" to the memory cell 29, the voltage VPL0 of the plate line PL0 is set to VCC /
2, the cell transistor 33 is turned on, and the voltage V _BL of the bit line BL is changed from VCC / 2 → VCC → VCC / 2.
And change. By doing so, the state of the polarization P of the ferroelectric capacitor 31 is, as shown in FIG.
The change occurs from point to point C, the polarization P of the ferroelectric capacitor 31 becomes a positive polarization PR, and the ferroelectric capacitor 31 stores "1". It should be noted that a closed curve consisting of B point → C point → D point → E point → B point shows a hysteresis loop.

On the other hand, when "0" is written in the memory cell 29, the voltage VPL0 of the plate line PL0 is set to V
As CC / 2, the cell transistor 33 is turned on, and the voltage V _BL of the bit line BL is changed from VCC / 2 → 0V → VC.
Change to C / 2. By doing so, the voltage of the storage electrode 31A of the ferroelectric capacitor 31 with respect to the plate electrode 31B changes from 0V → −VCC / 2 → 0V, and the polarization P of the ferroelectric capacitor 31 is as shown in FIG. ,
The change occurs from point A to point D to point E, the polarization P of the ferroelectric capacitor 31 becomes a negative polarization -PR, and the ferroelectric capacitor 31 stores "0".

FIG. 12 is a method of reading data from a memory cell in an example of the embodiment of the ferroelectric memory of the present invention (first embodiment of the method of reading data in the ferroelectric memory of the present invention. 12A is a waveform diagram for explaining reading of data from the memory cell 29 as an example, FIG. 12A is a voltage waveform of the word line WL0, FIG. 12B is a voltage waveform of the plate line PL0, and FIG. 12C is a ferroelectric capacitor. 12 shows voltage changes of the bit lines BL and / BL when "1" is written in 31. FIG. 12D shows voltage changes of the bit lines BL and / BL when "0" is written in the ferroelectric capacitor 31. Is shown.

That is, when starting the reading of data from the memory cell 29, the precharge control signal φPR = H level and the nMOS transistors 38 to 40 are started before the start.
State = ON, and bit lines BL and / BL are set to VCC / 2.
Precharge to. Next, the word line WL0 is raised to VCC + VTH (VTH is the threshold voltage of the cell transistor) via the word plate driver,
The cell transistor 33 is turned on, and then the plate electrode drive voltage φPL is set to VCC / 2 → V via the word plate driver as shown in FIG. 5, FIG. 7 or FIG.
Change from H to VL to VCC / 2.

FIG. 13 shows the ferroelectric capacitor 3
Bit line B when "1" is written in 1
FIG. 13A is a diagram for explaining a voltage change of L, FIG. 13A is a change of polarization P of the ferroelectric capacitor 31, and FIG. 13B is a relationship between a change of polarization P of the ferroelectric capacitor 31 and a voltage change of the bit line BL. Is shown.

[0102] Incidentally, the straight line 105, ferroelectric QBL the charge transferred to the bit line BL from the capacitor 31, QBL = CBLV _BL when the capacitance value was CBL of the bit line BL
Is a line showing the relationship. That is, the ferroelectric capacitor 31
When "1" is written in, the plate electrode drive voltage φPL is changed to VCC / 2 → VH → VL → VCC.
When changed to / 2, the polarization P changes, as shown in FIG. 13A, from point C → Z1 point → Z2 point → Z3 point → Z4 point,
Eventually, an amount of charge ΔQ3 that makes the voltage V _BL of the bit line BL equal to the voltage of the storage electrode 31A of the ferroelectric capacitor 31 moves from the ferroelectric capacitor 31 to the bit line BL, and the charge of the bit line BL. The voltage V _BL is VCC / 2 + Vα
To rise.

In this way, when "1" is written in the ferroelectric capacitor 31, the voltage V _BL of the bit line BL rises to VCC / 2 + Vα, and the bit line / BL
Since the voltage V _{/ BL} of V is maintained at VCC / 2,
As shown in C, by the sense amplifier 43, the voltage V _BL of the bit line BL rises to VCC and the voltage V _{/ BL} of the bit line / BL falls to 0 V, so that the bit line BL,
The voltage difference between / BL is amplified.

In this case, the plate electrode drive voltage φ
Since PL is maintained at VCC / 2, by the voltage V _BL of the bit line BL is raised to VCC from VCC / 2 + V.alpha, the ferroelectric capacitor 31, a read data "1" is again Written.

FIG. 14 is a diagram for explaining the voltage change of the bit line BL when “0” is written in the ferroelectric capacitor 31, and FIG. 14A is the polarization P of the ferroelectric capacitor 31. 14B shows the relationship between the change in polarization P of the ferroelectric capacitor 31 and the change in voltage of the bit line BL.

That is, when "0" is written in the ferroelectric capacitor 31, if the plate electrode drive voltage φPL is changed from VCC / 2 → VH → VL → VCC / 2, the polarization P becomes As shown in 14A, point E → W
It changes from 1 point → W2 point → W3 point → W4 point, and finally,
The amount of charge ΔQ4 where the voltage of the storage electrode 3A of the voltage V _BL and the ferroelectric capacitor 31 of the bit line BL becomes equal to move the dielectric capacitor 31 strength from the bit line BL, and the voltage V _BL of the bit line BL, and VCC / 2−Vβ.

As described above, when "0" is written in the ferroelectric capacitor 31, the voltage V _BL of the bit line BL drops to VCC / 2-Vβ, and the bit line / BL.
Since the voltage V _{/ BL} of V is maintained at VCC / 2,
As shown in D, the sense amplifier 43 causes the bit line B
The voltage V _BL of L drops to 0V and the bit line / B
The voltage V _{/ BL of} L rises to VCC and the bit lines BL, /
The voltage difference between BL is amplified.

In this case, the plate electrode drive voltage φ
Since PL is VCC / 2 is maintained by the voltage V _BL of the bit line BL is lowered to 0V from VCC / 2-V?, The ferroelectric capacitor 31, a read data "0" Is rewritten.

As described above, in the example of the embodiment of the ferroelectric memory of the present invention, for example, when data is read from the memory cell 29, the bit lines BL and / BL are set to VCC.
After precharging to / 2, turn on the cell transistor 33
N, the plate electrode 31B of the ferroelectric capacitor 31
Voltage to be applied to VCC / 2 → VH → VL → VCC / 2
When “1” is written in the ferroelectric capacitor 31, the voltage V _BL of the bit line BL is increased to VCC / 2 + Vα, and “0” is written in the ferroelectric capacitor 31. In this case, the voltage V _BL of the bit line BL is lowered to VCC / 2−Vβ, and the voltage difference between the bit lines BL and / BL is amplified by the sense amplifier 43.

That is, according to the example of the embodiment of the ferroelectric memory of the present invention, the method of precharging the bit line to VCC / 2 with the data read from the selected memory cell to the bit line is adopted. The detection can be performed as in the case of the adopted DRAM, and since a dummy cell is not necessary, stable operation can be secured for a long period of time.

In the example of the embodiment of the ferroelectric memory of the present invention, the plate electrode drive voltage generating circuit 23
8 is configured as shown in FIG. 8, the plate electrode drive voltage φPL is changed to VCC / 2 → VH as shown in FIG.
→ When rewriting data after changing VL → VCC / 2, plate electrode drive voltage φPL is changed to VCC / 2 → VHH
The reliability of data rewriting can be improved by changing → VLL → VCC / 2.

That is, at the time of rewriting, when the plate electrode drive voltage φPL is changed to VCC / 2 → VHH → VLL → VCC / 2, for example, when "1" is written in the ferroelectric capacitor 31, , Plate line PL0
The voltage V _BL -VPL0 of the bit line BL with respect to can be set to VCC, and sufficient polarization indicating that the stored data is "1" can be obtained.

On the other hand, when "0" is written in the ferroelectric capacitor 31, the plate line PL0
The voltage V _BL -VPL0 of the bit line BL with respect to can be set to -VCC, and sufficient polarization indicating that the stored data is "0" can be obtained.

Here, in an example of the embodiment of the ferroelectric memory of the present invention, VHH (for example, 3.0 V)> VH
(Eg, 2.5V), VLL (eg, 0V) <VL
Although the case has been described (for example, 1.0 V), it is not always necessary that VHH> VH and VLL <VL.

In the example of the embodiment of the ferroelectric memory of the present invention, if VH is set so that a voltage larger than the write voltage is applied to the ferroelectric capacitor 31,
That is, the voltage = V _BL applied between the storage electrode 31A and the plate electrode 31B of the ferroelectric capacitor 31 -VPL0 = V
_When VH is set so that _BL −VH <−VCC / 2, when “0” is written in the ferroelectric capacitor 31, the polarization P of the ferroelectric capacitor 31 is as shown in FIG.
As shown in FIG. 6, the voltage changes from the point E to the solid line 107 and returns to the original point E, and the voltage V of the bit line BL is increased.
Or _BL becomes equal to the voltage V _{/ BL} of the bit line / BL, or the polarization P becomes large and in the negative direction than the previous reading, the voltage of the voltage V _BL is the bit line / BL of the bit line BL V
There is a case where it becomes higher than _{/ BL} and erroneous data “1” is read as data.

Also, VH-VCC / 2 <VCC / 2-V
When VL is set so as to be L, when “1” is written in the ferroelectric capacitor 31, the same as in FIG.
As shown in 6, the polarization P of the ferroelectric capacitor 31 is
The voltage changes from the point C to the original point C as shown by the solid line 108, and the voltage V _BL of the bit line _BL changes to the bit line / BL.
Or become equal to the voltage V _{/ BL,} or the polarization P becomes larger in the positive direction than before read, voltage V _BL of the bit line BL becomes lower than the voltage V _{/ BL} of the bit line / BL As a result, erroneous data “0” may be read as data.

Therefore, in one example of the embodiment of the ferroelectric memory of the present invention, V _BL -VH>-is set so that a voltage higher than the write voltage is not applied to the ferroelectric capacitor.
It is preferable to set the value of VH so as to be VCC / 2, and it is preferable to set the value of VL so that VCC / 2−VL <VH−VCC / 2.

That is, when the voltage VH is applied to the plate electrode, the strength of the electric field applied to the ferroelectric capacitor is
The strength of the electric field that is smaller than the electric field applied when writing data to the ferroelectric capacitor and that is applied to the ferroelectric capacitor when the voltage VL is applied to the plate electrode is
It is preferable to make it smaller than the electric field applied to the ferroelectric capacitor when the voltage VH is applied to the plate electrode.

In the example of the embodiment of the ferroelectric memory of the present invention, the read margin when "0" is written in the ferroelectric capacitor and "1" is written in the ferroelectric capacitor. It is preferable to set VH and VL so as to equalize the read margin in the case of being set.

In FIG. 17, the write voltage is set to 5 V, and the voltage initially applied between the storage electrode and the plate electrode of the ferroelectric capacitor at the time of data reading, that is, VH.
The voltage applied second between the storage electrode of the ferroelectric capacitor and the plate electrode when -VCC / 2 is 5V, that is, the magnitude of VL-VCC / 2 and the polarization change of the ferroelectric capacitor. FIG. 9 is a diagram showing the relationship with ΔP, that is, the amount of charge appearing on the electrodes. When a solid line 110 is written with “0” in the ferroelectric capacitor, a solid line 111 is written with “1” in the ferroelectric capacitor. It shows the case. In this case, VL-VCC / 2 = -1.6V
When VL is set so that the read margin when "0" is written in the ferroelectric capacitor is equal to the read margin when "1" is written in the ferroelectric capacitor. You can

Further, in FIG. 18, write voltage = 5V, VH
VL-VC when -VCC / 2 = 2.5V
The magnitude of C / 2 and the polarization change ΔP of the ferroelectric capacitor
The solid line 113 shows the case where "0" is written in the ferroelectric capacitor, and the solid line 114 shows the case where "1" is written in the ferroelectric capacitor.

In this case, VL-VCC / 2 = -1.3V
When VL is set so that the read margin when "0" is written in the ferroelectric capacitor is equal to the read margin when "1" is written in the ferroelectric capacitor. You can

Further, the sense amplifier 43 causes the bit line B
In order to amplify the voltage difference between L and / BL, a charge of at least 10 fC is required for each cell. If the area of the ferroelectric capacitor is 1 μm 2, the required polarization ΔP is 1
It becomes μC / cm 2. Therefore, the pulse applied to the plate electrode of the ferroelectric capacitor can be made small within the range where this condition is satisfied, and in this case, the inversion fatigue of the ferroelectric capacitor becomes small and the life of the element is shortened. In addition to being able to increase the length, it is possible to reduce the charge amount of the electric charge in the ferroelectric capacitor and the discharge amount of the electric charge from the ferroelectric capacitor, so that the read operation can be speeded up and the power consumption can be reduced. be able to.

FIG. 19 shows another method of reading data from a memory cell in the example of the embodiment of the ferroelectric memory of the present invention (second embodiment of the method of reading data in the ferroelectric memory of the present invention. FIG. 19A is a waveform diagram for explaining data read from the memory cell 29 by way of example, FIG. 19A shows a voltage waveform of the word line WL0, and FIG.
Is a voltage waveform of the plate line PL0, FIG. 19C is a voltage change of the bit lines BL and / BL when “1” is written in the ferroelectric capacitor 31, and FIG. 19D is “0” in the ferroelectric capacitor 31. The change in voltage of the bit lines BL and / BL when written is shown.

That is, in the example of the embodiment of the ferroelectric memory of the present invention, for example, when VCC / 2 is set to 1.5V, for example, VL is set to 0.5V and VH is set to 2.0V. Change the plate electrode drive voltage φPL from VCC / 2 to VL
Data can be read from the memory cell even when changing from VH to VCC / 2.

FIG. 20 shows the ferroelectric capacitor 3
Bit line B when "1" is written in 1
20A is a diagram for explaining a voltage change of L, FIG. 20A is a change of polarization P of the ferroelectric capacitor 31, and FIG. 20B is a relationship between a change of polarization P of the ferroelectric capacitor 31 and a voltage change of the bit line BL. Is shown.

[0126] Incidentally, the straight line 116, ferroelectric QBL the charge transferred to the bit line BL from the capacitor 31, QBL = CBLV _BL when the capacitance value was CBL of the bit line BL
Is a line showing the relationship. That is, the ferroelectric capacitor 31
When "1" is written in, the plate electrode drive voltage φPL is changed to VCC / 2 → VL → VH → VCC.
When it is changed to / 2, the polarization P changes as shown in FIG. 20A in the order of C point → S1 point → S2 point → S3 point → S4 point,
Eventually, the amount of charge ΔQ5 that makes the voltage V _BL of the bit line BL equal to the voltage of the storage electrode 31A of the ferroelectric capacitor 31 moves from the ferroelectric capacitor 31 to the bit line BL, and The voltage V _BL is VCC / 2 + Vγ
To rise.

In this way, when "1" is written in the ferroelectric capacitor 31, the voltage V _BL of the bit line BL rises to VCC / 2 + Vγ, and the bit line / BL
Since the voltage V _{/ BL} of V is maintained at VCC / 2,
As shown in C, by the sense amplifier 43, the voltage V _BL of the bit line BL rises to VCC and the voltage V _{/ BL} of the bit line / BL falls to 0 V, so that the bit line BL,
The voltage difference between / BL is amplified.

In this case, the plate electrode drive voltage φ
Since PL is maintained at VCC / 2, by the voltage V _BL of the bit line BL is raised to VCC from VCC / 2 + V.gamma, the ferroelectric capacitor 31, a read data "1" is again Written.

FIG. 21 is a diagram for explaining the voltage change of the bit line BL when “0” is written in the ferroelectric capacitor 31, and FIG. 21A is the polarization P of the ferroelectric capacitor 31. 21B shows the relationship between the change in polarization P of the ferroelectric capacitor 31 and the change in voltage of the bit line BL.

That is, when "0" is written in the ferroelectric capacitor 31 and the plate electrode drive voltage φPL is changed from VCC / 2 → VL → VH → VCC / 2, the polarization P becomes as shown in FIG. As shown in, point E → T1
The charge changes in the order of point → T2 point → T3 point → T4 point, and finally the voltage ΔBL of the bit line _BL is equal to the voltage of the storage electrode 31A of the ferroelectric capacitor 31. The voltage moves from BL to the ferroelectric capacitor 31 and the voltage V _BL of the bit line BL drops to VCC / 2−Vδ.

In this way, when "0" is written in the ferroelectric capacitor 31, the voltage V _BL of the bit line BL drops to VCC / 2-Vδ, and the bit line / BL
Since the voltage V _{/ BL} of V is maintained at VCC / 2,
As shown by D, the sense amplifier 43 lowers the voltage V _BL of the bit line BL to 0 V, and the bit line / B
The voltage V _{/ BL of} L rises to VCC, and the bit lines BL, / B
The voltage difference between L is amplified.

In this case, the plate electrode drive voltage φ
Since PL is maintained at VCC / 2, by the voltage V _BL of the bit line BL is lowered to 0V from VCC / 2-V8, the ferroelectric capacitor 31, a read data "0" Is rewritten.

Here, for example, V _BL -VL> VCC / 2
If “1” is written in the ferroelectric capacitor 31, then the polarization P of the ferroelectric capacitor 31.
22 changes from point C to the point shown by the solid line 118 and returns to the original point C, and the bit line BL
When the voltage V _BL of becomes equal to the voltage V _{/ BL} of the bit line / BL, or the polarization P becomes larger in the positive direction than before reading the voltage V _BL is the bit line / BL of the bit line BL
It becomes lower than the voltage V _{/ BL of}
There is a case where "0" which is erroneous data is read.

Further, VCC / 2-VL <VH-VCC /
In the case where the value is 2, when "0" is written in the ferroelectric capacitor 31, similarly as shown in FIG. 22, the polarization P of the ferroelectric capacitor 31 is from the point E to the solid line 119.
Change to the original point E and the voltage V _BL of the bit line BL becomes equal to the voltage V _{/ BL} of the bit line / BL, or the polarization P is in the negative direction as compared with that before reading. large becomes, voltage V _BL of the bit line BL becomes too higher than the voltage V _{/ BL} of the bit line / BL, as data, if would read "1" is erroneous data occurs.

[0135] Therefore, it is necessary to set the value of the VL in such a way that V _BL -VL <VCC / 2, also, VH-
The value of VH needs to be set so that VCC / 2 <VCC / 2-VL. That is, the strength of the electric field applied to the ferroelectric capacitor when applying the voltage VL to the plate electrode is smaller than the electric field applied when writing data to the ferroelectric capacitor, and the voltage VH is applied to the plate electrode. In this case, the strength of the electric field applied to the ferroelectric capacitor is preferably smaller than the electric field applied to the ferroelectric capacitor when the voltage VL is applied to the plate electrode.

In this case, the plate electrode drive voltage φ
PL is VCC / 2 (for example, 1.5V) → VL (for example, 0.5V) → VH (for example, 2.0V) → VCC /
After changing to 2, change the plate electrode drive voltage φPL to VCC.
/ 2 → VLL (for example, 0V) → VHH (for example, 3.
When changing from 0 V) to VCC / 2, the reliability of rewriting can be increased.

In the above description, the preferred method of setting the voltages VH and VL in the ferroelectric memory according to the present invention has been described. However, in reality, the read margin (the magnitude of the read signal) also changes depending on the capacitance ratio between the bit line capacitance (indicating the parasitic capacitance of the bit line) and the ferroelectric capacitor. Therefore, in order to obtain a sufficient read signal margin, the optimum capacitance ratio and voltages VH, V
It is necessary to set L. The optimum capacitance ratio between the bit line capacitance and the ferroelectric capacitor will be described below.

First, the basic operation of the ferroelectric memory according to the present invention described above will be summarized. FIG. 28 is a schematic circuit configuration example of a ferroelectric memory according to the present invention. FIG.
9 is the hysteresis characteristic of the ferroelectric capacitor,
The information of logic "1" and "0" is stored as the states of a and b in the figure, respectively. FIG. 30 shows a timing chart of the read operation.

During the data retention period, the plate line (P
L) and the bit line (BL) are kept at Vcc / 2. When reading data, the potential of the word line (WL) is raised to turn on the cell transistor 202, and pulses having alternating polarities are input to the plate line (PL). FIG.
The horizontal axis of 9 indicates the potential difference (= V _BL −V _PL ) between the plate line voltage V _PL and the bit line voltage V _BL, and the polarization of the ferroelectric capacitor 204 changes as shown in FIG. .
Finally, the bit line voltage V _BL changes from Vcc / 2 to a positive or negative direction depending on the direction of the held polarization.

At this time, the change of the bit line voltage (dVB
L) is dVBL = ΔP _r S / C depending on the decrease amount (ΔP _r S) of the remanent polarization of the capacitor and the bit line capacitance C _{BL.
Expressed as BL} . The potential of the complementary bit line (/ BL) is Vcc /
Since it is 2, the potential difference between the bit lines BL and / BL is amplified by the sense amplifier 206, and data is read out to the outside and rewritten to the capacitor.

The magnitude of the read signal is the plate line PL.
Depends on the magnitude of the pulse input to. The potential V of the first and second pulses of the plate line voltage measured from Vcc / 2
When H and VL are respectively ΔVH and ΔVL, the read margin when the logic “1” is written in the ferroelectric capacitor 204 is larger as ΔVH is larger and ΔVL is smaller, and the logic “1” is written in the ferroelectric capacitor 204. 0 "
Read margin is ΔVL
Is larger the larger.

In the above-mentioned ferroelectric memory, the read margin when the logic "1" is written in the ferroelectric capacitor 204 and the read margin when the logic "0" is written in the ferroelectric capacitor 204. It is shown that the voltages VH and VL are set so that and become equal.

However, as described above, the read margin (the size of the read signal) changes depending on the capacitance ratio between the bit line capacitance and the ferroelectric capacitor. A method for setting the optimum capacitance ratio and the voltages VH and VL in the ferroelectric memory according to the present invention will be described below.

FIG. 31 is a diagram showing a change in polarization at the time of reading the ferroelectric capacitor in the circuit shown in FIG. (A) is a change in plate line voltage, (B) is a case where logic "1" is read from the ferroelectric capacitor,
(C) shows a case where logic "0" is read from the ferroelectric capacitor. The operating conditions are shown in the figure.

When a pulse is input to the plate line as shown in FIG. 31A, the polarization of the ferroelectric capacitor 204 changes and the voltage change dVBL appearing on the bit line as shown in FIG. 31B. Becomes a read signal. The above operation is
This has already been described in detail with reference to FIGS.

FIG. 32 is a diagram showing the dependence of the bit line capacitance C _BL on the voltage change dVBL of the bit line in the operation shown in FIG. Voltage ΔVL is -0.8V
In this case, the magnitudes of the bit line voltage changes dVBL for calling the logic "1" and the logic "0" are almost equal. In this case, when the bit line capacitance C _BL is 4.26 nF, the read signal margin has the maximum value. Therefore, a stable read operation can be expected. At this time, the capacitance ratio between the bit line BL and the ferroelectric capacitor 204 is C _BL [F] / P _r S
[C] = 1.9 [V ^-1 ].

However, the bit line capacitance C _BL also affects power consumption and operating speed. Below, the bit line capacity C _BL is 1
Compare the case of nF and the case of 8 nF. In FIG. 32, the bit line voltage change dVBL for the case where the bit line capacitance C _BL is 1 nF and 8 nF has almost the same value. FIG.
FIG. 3 is a diagram showing changes in polarization when the bit line capacitance C _BL is 1 nF and 8 nF. (A) shows the case where the logic "1" is read from the ferroelectric capacitor, and (B) shows the case where the logic "0" is read from the ferroelectric capacitor.

As shown in FIG. 33, the change in polarization when the bit line capacitance C _BL is 8 nF is the bit line capacitance C _BL.
Is larger than that of 1 nF. That is, the bit line capacitance C
_{When BL} is 8 nF, this causes an increase in power consumption and a decrease in operating speed. Therefore, it is desirable that the bit line capacitance C _{BL be} smaller.

As a result, the above-mentioned method of increasing the read margin (bit line BL and ferroelectric capacitor 20)
4 and the capacity ratio C _BL [F] / P _r S [C] is 1.9.
[V ⁻¹ ]), it is preferable that the read signal dVBL does not exceed the maximum value, and the capacitance ratio between the bit line BL and the ferroelectric capacitor 204 is 0.5.
It is preferable to satisfy the condition of [V ⁻¹ ] <C _BL [F] / P _r S [C] <2.

Further, the read signal (bit line voltage change) dVBL can be increased by increasing the drive voltage VH of the plate line higher than Vcc by an internal boosting power source or the like. FIG. 34 is a diagram showing the dependence of the bit line capacitance C _BL on the bit line voltage change dVBL when the voltage ΔVH is set to 2.65V. In this case, the voltage ΔV
When L is -1.0 V, the read margins for the logic "1" and the logic "0" are almost equal, and when the bit line capacitance C _BL is 2 to 3 nF, the read signal margin is +90 mV.
And becomes maximum at -80 mV.

FIG. 35 is a diagram showing changes in polarization of the ferroelectric capacitor under the operating conditions of FIG. Compared with the condition of FIG. 31, the width of the polarization change during operation is substantially the same, but the signal margin finally obtained is large. This is because the bit line capacitance C _BL is small. By thus reducing the bit line capacitance C _BL and using the voltage from the boosted power supply as the voltage VH, a large read signal can be obtained without increasing the power consumption (that is, the polarization change is reduced). .

Further, the voltages VL and VH can be formed by, for example, the internal step-down power supply circuit and the internal step-up power supply circuit shown in FIGS. 36 (A) and (B). The internal step-down power supply circuit includes a comparison circuit. The internal booster circuit includes a ring oscillator. Since these circuits are well known, a description of their operation will be omitted here.

As described above, by optimizing the capacitance ratio between the bit line BL and the ferroelectric capacitor 204 or increasing the drive voltage VH of the plate line, a large read signal can be obtained and stable for a long period of time. It is possible to realize a memory element that operates in the above manner.

In the above description of the present invention, the ferroelectric memory capable of stably reading the data from the memory cell without providing the dummy cell has been described.
However, the inventor's analysis has revealed that a ferroelectric memory provided with a dummy cell can also perform stable reading for a long period of time. The structure of the ferroelectric memory provided with the dummy cell according to the present invention will be described below.

First, before the description of the ferroelectric memory according to the present invention, the operation of the conventional ferroelectric memory having dummy cells will be summarized below. FIG. 37 is a polarization hysteresis characteristic of a ferroelectric capacitor, FIG. 38 is a structural example of a conventional ferroelectric memory having dummy cells, and FIG.
9 is a diagram showing a potential change of each line of the ferroelectric memory shown in FIG.

In FIG. 37, the polarizations P0 and P1 correspond to the logic "0" and logic "1" of the data, respectively. The horizontal axis represents the potential of the bit line with respect to the potential of the plate line.
In the operation of the ferroelectric memory, the potentials of the bit line and the plate line are almost equal at first. Next, when the potential of the plate line rises as indicated by PL and DPL in FIG. 39, the polarization changes as indicated by the arrow in FIG. 37 and ΔP0 or ΔP on the bit line.
The potential changes by 1. The written data is discriminated by the magnitude of the potential change of the bit line.

In this case, the reference potentials supplied by the dummy cells compare the potentials of the bit lines, the potential difference is amplified by the sense amplifier, and it is determined whether it is a logic "0" or a logic "1". In the above operation, the driving voltage applied to the plate lines of the memory cell and the dummy cell is substantially the same voltage. The above operation is described in detail in the "Prior Art" section of this specification.

In the above-mentioned operation, as described above, the dummy cell is driven every time data is read, so that there is a problem that the characteristics change due to inversion fatigue and the read margin becomes small. Therefore, the conventional method of using a dummy cell cannot perform a stable read operation.

The ferroelectric memory having dummy cells according to the present invention will be described below. The ferroelectric memory according to the present invention is characterized in that, when the reference potential of the dummy cell is generated, the drive voltage of the plate line DPL of the dummy cell is set lower than the drive voltage of the plate line PL of the memory cell.

Inversion fatigue of a single ferroelectric capacitor is as described by Mihara et al. [Applied Physics 64, 1188 (199).
5)], greatly depends on the driving voltage of the capacitor. Reversal fatigue is exponentially improved by lowering the driving voltage. However, the above report does not teach the application to the memory as it relates to the capacitor alone. In the memory using the ferroelectric capacitor according to the present invention, the drive voltage of the capacitor in the dummy cell for generating the reference potential is set low, and therefore the inversion fatigue of the dummy cell is reduced. As a result, stable reading of data becomes possible.

FIG. 40 shows the relationship between the drive voltage of the plate line in the memory cell or the dummy cell and the potential change of the bit line (BL or / BL). However, the drive voltages of the plate lines PL and DPL are applied in a unit function form as shown in FIG. That is, the plate line PL,
The drive voltage of the DPL changes, for example, as 0V → VP (plate line voltage).

In FIG. 40, when the drive voltage of the plate line is 1.75 V or more, a difference appears in the bit line potential depending on the direction of spontaneous polarization of the ferroelectric capacitor. Therefore, if the dummy cell generates the reference potential so as to be in the middle of these bit line potentials, the direction of spontaneous polarization of the ferroelectric capacitor can be easily determined.

For example, when the drive voltage of the plate line of the memory cell is maintained at 5V and the drive voltage of the plate line of the dummy cell is set to 3 to 4.5V, the potential of the bit line BL becomes 2.7V (logic). (Corresponding to "1") or 1.3 V (corresponding to logic "0"), and the bit line /
The potential of BL (when spontaneous polarization is inverted) is 1.5 to 2.
It becomes 5V. That is, the reference voltage can be located in the middle of the potential of both the logic "1" and logic "0" states of the memory cell. In this way, it can be seen that an appropriate reference potential can be generated by lowering the drive voltage of the plate line of the dummy cell below the drive voltage of the plate line of the memory cell.

As described above, since the dummy cell is driven every time data is read, inversion fatigue occurs earlier than the memory cell. In the ferroelectric memory according to the present invention, since the drive voltage of the plate line of the dummy cell is set low and the inversion fatigue is suppressed, a stable read operation can be expected. FIG. 41 shows the inversion fatigue characteristics of the ferroelectric capacitor. The horizontal axis represents the number of inversions, and the vertical axis represents the remanent polarization (2 × Pr: remanent polarizati).
on). A decrease in remanent polarization indicates increased fatigue.

When the ferroelectric capacitor is driven at 5 V, reversal polarization 2Pr is halved when it is inverted 10 ⁵ times.
On the other hand, when the ferroelectric capacitor is driven at 2V, the remanent polarization 2Pr does not decrease and fatigue is not observed even when the inversion is repeated 10 ⁷ times or more. In order to suppress the inversion fatigue of the dummy cell, it is desirable that the drive voltage of the plate line be set as low as possible within the range where the reference potential can be generated.

FIG. 42 shows the relationship between the drive voltage of the plate line in the memory cell or the dummy cell and the potential change of the bit line (BL or / BL). However, the drive voltages of the plate lines PL and DPL are applied in a rectangular pulse shape. That is, the drive voltage of the plate lines PL and DPL changes, for example, 0V → VP (plate line voltage) → 0V.

In FIG. 42, when the spontaneous polarization of the ferroelectric capacitor is not inverted, the potential of the bit line does not increase greatly with respect to the drive voltage as in the case of FIG. Therefore,
The margin for setting the reference potential increases. For example, when the drive voltage of the plate line of the memory cell is set to 5V and the drive voltage of the plate line of the dummy cell is set to 1.75 to 3.5V, the potential of the bit line BL becomes 0.68V (logic " 1 ") or 0.08V (equivalent to logic" 0 ")
Then, the potential of the bit line / BL as the reference voltage (when the spontaneous polarization is inverted) becomes 0.2 to 0.5V. That is, the reference voltage can be located in the middle of the potential of both the logic "1" and logic "0" states of the memory cell.

Therefore, compared with the case where the read operation is performed by the unit function drive voltage (shown in FIG. 40), the read operation is performed by the rectangular pulse drive voltage (shown in FIG. 42). However, the drive voltage of the plate line of the dummy cell can be set lower.

In the ferroelectric memory having dummy cells according to the present invention described above, different voltages are applied to the plate lines of the memory cells and the dummy cells. Considering the variation of the power supplies that generate the voltage, it is desirable to use the same power supply rather than preparing a dedicated power supply for each.

FIG. 43 is a diagram showing an example of the structure of a ferroelectric memory having dummy cells according to the present invention. In the ferroelectric memory shown in FIG. 43, memory cells 302 and dummy cells 304 are arranged in parallel and coupled to the same power supply (not shown). However, the supply timing is the memory cell 302.
And the dummy cell 304. Further, in order to lower the drive voltage of the plate line DPL of the dummy cell, the capacitor 308 or the resistor (capacitor in FIG. 43) is connected in series with the ferroelectric capacitor 306. In particular, by forming the capacitor 308 with a ferroelectric capacitor, variations in the ferroelectric capacitor 306 are canceled out, and a stable ferroelectric memory can be realized.

As described above, in the ferroelectric memory having the dummy cell according to the present invention, the driving voltage of the ferroelectric capacitor of the dummy cell is set lower than the driving voltage of the ferroelectric capacitor of the memory cell, so that the dummy cell Inversion fatigue is reduced, and stable write and read operations can be achieved for a long period of time.

Another ferroelectric memory according to the present invention is also proposed. The ferroelectric memory according to the present invention solves the problems of the ferroelectric memory disclosed in Japanese Patent Publication No. 7-13877 described in the prior art. In the ferroelectric memory according to the present invention, the potential of the plate line and the bit line is set to Vcc / 2 when the power is turned on. Next, the word line potential is raised for each word line, and the potential of the corresponding plate line becomes Vcc / 2 →
(Vcc / 2 + Vα) → (Vcc / 2−Vβ) → Vcc
/ 2 in order (however, Vα and Vβ are
Predetermined voltage). In this way, reading and rewriting of data are performed. After converting the remnant polarization of all memory cells into accumulated charge, the memory is set to DRAM mode.

Since the data is recalled when the power is turned on by the above-described read method, a stable read operation can be performed regardless of the characteristics of the dummy cell.
The embodiments of the present invention have been described above. However, the present invention is not limited to these embodiments, and it goes without saying that improvements and modifications can be made within the scope of the present invention.

[0174]

As described above, according to the present invention, since data can be read from the memory cell without providing a dummy cell, stable operation can be secured for a long period of time.

In the above ferroelectric memory, a large read signal can be obtained by further optimizing the capacitance ratio between the bit line BL and the ferroelectric capacitor or increasing the plate line drive voltage VH. It is possible to realize a memory element that operates stably for a long period of time.

Further, in the ferroelectric memory having the dummy cell according to the present invention, the inversion fatigue of the dummy cell is set by setting the drive voltage of the ferroelectric capacitor of the dummy cell lower than the drive voltage of the ferroelectric capacitor of the memory cell. Is reduced, and stable write and read operations can be achieved over a long period of time.

Further, in the reading method of the nonvolatile ferroelectric memory and the nonvolatile ferroelectric memory according to the present invention, when the power is turned on, the residual polarization of all the memory cells is converted into the accumulated charge, and the data is stored. A recall is performed. Therefore, a stable data read operation can be performed regardless of the characteristics of the dummy cell.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an example of an embodiment of a ferroelectric memory of the present invention.

FIG. 2 is a circuit diagram showing a part of a memory cell array, a sense amplifier array, and a column selection gate array provided in an example of an embodiment of a ferroelectric memory of the present invention.

FIG. 3 is a circuit diagram showing a part of a row decoder and a word plate driver column provided in an example of an embodiment of a ferroelectric memory of the present invention.

FIG. 4 is a circuit diagram showing a first configuration example of a plate electrode drive voltage generation circuit provided in an example of an embodiment of a ferroelectric memory of the present invention.

FIG. 5 is a waveform diagram showing an operation of the first configuration example of the plate electrode drive voltage generation circuit provided in the example of the embodiment of the ferroelectric memory of the present invention.

FIG. 6 is a circuit diagram showing a second configuration example of a plate electrode drive voltage generating circuit provided in an example of an embodiment of a ferroelectric memory of the present invention.

FIG. 7 is a waveform chart showing an operation of a second configuration example of the plate electrode drive voltage generating circuit provided in the example of the embodiment of the ferroelectric memory of the present invention.

FIG. 8 is a circuit diagram showing a third configuration example of the plate electrode drive voltage generation circuit provided in the example of the embodiment of the ferroelectric memory of the present invention.

FIG. 9 is a waveform diagram showing an operation of a third configuration example of the plate electrode drive voltage generating circuit provided in the example of the embodiment of the ferroelectric memory of the present invention.

FIG. 10 is a diagram for explaining writing of data to a memory cell in an example of an embodiment of a ferroelectric memory of the present invention by taking writing of data to a specific memory cell as an example.

FIG. 11 is a diagram for explaining writing of data to a memory cell in an example of an embodiment of a ferroelectric memory of the present invention by taking writing of data to a specific memory cell as an example.

FIG. 12 specifies a method of reading data from a memory cell in the example of the embodiment of the ferroelectric memory of the present invention (first embodiment of the method of reading data in the ferroelectric memory of the present invention). FIG. 6 is a waveform diagram for explaining data reading from a memory cell as an example.

13 is a diagram for explaining the voltage change of the bit line when "1" is written in the ferroelectric capacitor when the method of reading data from the memory cell shown in FIG. 12 is executed. .

FIG. 14 is a diagram for explaining a voltage change of a bit line when “0” is written in the ferroelectric capacitor when the method of reading data from the memory cell shown in FIG. 12 is executed. .

FIG. 15 is a waveform diagram for explaining a method for surely rewriting data in the example of the embodiment of the ferroelectric memory of the present invention.

FIG. 16 is a diagram for explaining preferable values of the voltage applied to the plate electrode of the ferroelectric capacitor in the example of the embodiment of the ferroelectric memory of the present invention.

FIG. 17 is a diagram showing an example of an embodiment of a ferroelectric memory of the present invention, in which a write voltage applied to a ferroelectric capacitor and a storage capacitor and a plate electrode of the ferroelectric capacitor are applied at the time of data reading. FIG. 3 is a diagram showing the relationship between the voltage applied to the ferroelectric capacitor and the polarization change of the ferroelectric capacitor.

FIG. 18 is a diagram showing an example of the embodiment of the ferroelectric memory of the present invention, in which the write voltage applied to the ferroelectric capacitor and the voltage applied between the storage electrode and the plate electrode of the ferroelectric capacitor at the time of data reading. FIG. 3 is a diagram showing the relationship between the voltage applied to the ferroelectric capacitor and the polarization change of the ferroelectric capacitor.

FIG. 19 shows another method of reading data from a memory cell in the example of the embodiment of the ferroelectric memory of the present invention (second embodiment of the method of reading data in the ferroelectric memory of the present invention). FIG. 6 is a waveform diagram for explaining data reading from a specific memory cell as an example.

20 is a diagram for explaining the voltage change of the bit line when "1" is written in the ferroelectric capacitor when the method of reading data from the memory cell shown in FIG. 19 is executed. .

FIG. 21 is a diagram for explaining a voltage change of the bit line when “0” is written in the ferroelectric capacitor when the method of reading data from the memory cell shown in FIG. 19 is executed. .

22 is a diagram for explaining a preferable value of the voltage applied to the plate electrode of the ferroelectric capacitor when the method of reading data from the memory cell shown in FIG. 19 is executed.

FIG. 23 is a circuit diagram showing a main part of an example of a conventional ferroelectric memory.

FIG. 24 is a diagram for explaining writing of data to a memory cell in the conventional ferroelectric memory shown in FIG. 23 by taking an example of writing data to a specific memory cell.

FIG. 25 is a diagram for explaining writing of data to a memory cell in the conventional ferroelectric memory shown in FIG. 23 by taking data writing to a specific memory cell as an example.

FIG. 26 is a waveform diagram for explaining a method of reading data from a memory cell in the conventional ferroelectric memory shown in FIG. 23, taking data reading from a specific memory cell as an example.

FIG. 27 is a diagram for explaining a method of reading data from a memory cell in the conventional ferroelectric memory shown in FIG. 23, taking data reading from a specific memory cell as an example.

FIG. 28 is a schematic circuit configuration example of a ferroelectric memory according to the present invention.

FIG. 29 is a hysteresis characteristic of a ferroelectric capacitor.

FIG. 30 is a timing chart of a read operation.

FIG. 31 is a diagram showing polarization changes during reading of the ferroelectric capacitor in the circuit shown in FIG. 28. (A) is a change in plate line voltage, (B) is a case where a logic "1" is read from the ferroelectric capacitor, and (C) is a case where a logic "0" is read from the ferroelectric capacitor.

32 is a diagram showing the dependency of the bit line capacitance C _BL on the voltage change dVBL of the bit line in the operation shown in FIG. 31.

FIG. 33 is a diagram showing changes in polarization when the bit line capacitance C _BL is 1 nF and 8 nF. (A) shows a case where a logic "1" is read from the ferroelectric capacitor, and (B) shows a case where a logic "0" is read from the ferroelectric capacitor.

FIG. 34 is a diagram showing the dependency of the bit line capacitance C _BL on the bit line voltage change dVBL when the voltage VH is set to 2.65V.

FIG. 35 is a diagram showing changes in polarization of the ferroelectric capacitor under the operating conditions of FIG. 34.

FIG. 36 is a configuration example of an output circuit of voltages VL and VH.
(A) is an internal step-down power supply circuit, and (B) is an internal step-up power supply circuit.

FIG. 37 is a hysteresis characteristic of polarization of a ferroelectric capacitor.

FIG. 38 is a structural example of a ferroelectric memory having a conventional dummy cell.

FIG. 39 is a diagram showing a potential change of each line of the ferroelectric memory shown in FIG.

FIG. 40 is a diagram showing a relationship between a drive voltage of a plate line and a potential change of a bit line (BL or / BL) in a memory cell or a dummy cell. However, the drive voltage of the plate line is applied in a unit function.

FIG. 41 shows the inversion fatigue characteristics of the ferroelectric capacitor.

FIG. 42 is a diagram showing a relationship between a drive voltage of a plate line and a potential change of a bit line (BL or / BL) in a memory cell or a dummy cell. However, when the plate line drive voltage is applied in the form of a rectangular pulse.

FIG. 43 is a diagram showing a configuration example of a ferroelectric memory having dummy cells according to the present invention.

[Explanation of symbols]

 φWL Word line drive voltage φPL Plate electrode drive voltage 1, 2 Memory cell 3, 4 Ferroelectric capacitor 5, 6 Cell transistor 7, 8 Dummy cell 9, 10 Ferroelectric capacitor 11, 12 Cell transistor 20 Memory cell array 21 Row decoder 22 Word line drive voltage generation circuit 23 Plate electrode drive voltage generation circuit 24 Word plate driver row 25 Sense amplifier row 26 Row decoder 27 Row selection gate row 29, 30 Memory cell 31, 32 Ferroelectric capacitor 33, 34 Cell transistor 35 Precharge circuit 36 Precharge voltage line 37 Precharge control signal line 38-40 nMOS transistor 41 Sense amplifier drive voltage line 42 Sense amplifier drive voltage line 43 Sense amplifier 44, 45 pMOS transistor 46, 4 7 nMOS Transistor 48 Column Select Gate 49, 50 nMOS Transistor 52 NAND Circuit 53 pMOS Transistor 54, 55, 56 nMOS Transistor 57 Node 58 Word Plate Driver 59 Inverter 60, 61 nMOS Transistor 62 nMOS Transistor 63 nMOS Transistor 64, 65 nMOS Transistor 67 NAND circuit 68 Inverter 69 NOR circuit 70 pMOS transistor 71 nMOS transistor 72 nMOS transistor 74 Inversion delay circuit 75-77 Inverter 78-80 Resistor 81-83 capacitor 84 NAND circuit 85 Inverter 86 NOR circuit 87 NOR circuit 88 pMOS transistor 89 nMOS Transistor 90 nMOS transistor 92 NAND circuit 93 inverter 94 NOR circuit 95 pMOS transistor 96 nMOS transistor 97 NAND circuit 98 inverter 99 NOR circuit 100 pMOS transistor 101 nMOS transistor 102 NAND circuit 103 nMOS transistor 202 cell transistor 204 ferroelectric capacitor 206 sense amplifier 302 memory cell 304 dummy cell 306 Ferroelectric capacitor 308 capacitor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 21/8242

Claims (40)

[Claims] 1. A method for reading data in a ferroelectric memory including a memory cell having a ferroelectric capacitor as a storage medium, comprising: (a) the ferroelectric capacitor changing polarization in response to a change in an electric field. The first and second electric fields having opposite directions are sequentially applied to the ferroelectric capacitor, and (b) the change in polarization of the ferroelectric capacitor is detected, whereby the memory cell is stored. The method for reading data in a ferroelectric memory is characterized in that it has respective steps of reading the data to be read to a data line. 2. A transfer gate having a first charge input / output terminal connected to a data line, a first electrode connected to a second charge input / output terminal of the transfer gate, and a second electrode connected to a drive voltage. A method for reading data in a ferroelectric memory comprising a memory cell comprising a ferroelectric capacitor connected to a line, comprising: (a) making the transfer gate non-conductive; and (b) precharging the data line. , (C) the transfer gate is made conductive, and (d) the first and second electric fields having opposite directions such that the ferroelectric capacitor changes polarization in response to a change in electric field are applied to the ferroelectric. A drive voltage for sequentially applying to the body capacitor is applied to the second electrode of the ferroelectric capacitor via the drive voltage line, and (e) each of the data stored in the memory cell is read to the data line. Characterized by having stages Ferroelectric method of reading data in a memory. 3. A first charge input / output terminal is connected to a first data line, and the i-th (where i = 1, 3, ..., 2n-1)
Connected to the second charge input / output terminal of the i-th transfer gate and the i-th transfer gate whose conduction / non-conduction is controlled by the second word line, and the second electrode is connected to the i-th transfer gate. An i-th memory cell including an i-th ferroelectric capacitor connected to a drive voltage line, a first charge input / output terminal connected to a second data line, and an i + 1th word line for conduction and non-conduction. The (i + 1) th transfer gate whose conduction is controlled and the first electrode are connected to the second charge input / output terminal of the (i + 1) th transfer gate, and the second electrode is connected to the (i + 1) th drive voltage line. An (i + 1) th memory cell composed of an (i + 1) th ferroelectric capacitor, a sense amplifier for amplifying a voltage difference between the first and second data lines, and a column selection for selecting the first and second data lines A method of reading data in a ferroelectric memory including a gate , (A) the first, second, ..., 2n transfer gates are made non-conductive, (b) the first and second data lines are precharged, and (c) selected The transfer gate of the memory cell is made conductive, and (d) first and second electric fields having opposite directions such that the ferroelectric capacitor of the selected memory cell changes polarization in response to a change in electric field. A driving voltage for sequentially applying to the ferroelectric capacitor of the selected memory cell is applied to the second electrode of the ferroelectric capacitor of the selected memory cell via the selected driving voltage line. (E) The data stored in the selected memory cell is read to the corresponding data line of the first and second data lines, and the voltage difference between the first and second data lines is amplified. In a ferroelectric memory characterized by having steps Data reading method. 4. The strength of the first electric field is smaller than the strength of the electric field applied to the ferroelectric capacitor when writing data, and the strength of the second electric field is smaller than that of the first electric field. 4. The method of reading data in a ferroelectric memory according to claim 1, wherein the intensity is smaller than the intensity. 5. When rewriting data, the ferroelectric capacitor changes polarization in response to a change in electric field,
It is characterized in that third and fourth electric fields having opposite directions and having strengths higher than those of the first and second electric fields are sequentially applied to the ferroelectric capacitor. A method of reading data in the ferroelectric memory according to claim 1, 2, 3, or 4. 6. The first and second electric fields are a read margin when a logic 1 is written in the ferroelectric capacitor and a read margin when a logic 0 is written in the ferroelectric capacitor. The strength is set such that the margin is the same or substantially the same.
6. A method of reading data in a ferroelectric memory according to 3, 4, or 5. 7. The precharge voltage of the data line is a voltage which is ½ to approximately ½ of the internal power supply voltage. Data read method in ferroelectric memory. 8. A ferroelectric memory including a memory cell having a ferroelectric capacitor as a storage medium, wherein the ferroelectric capacitor changes its polarization in response to a change in an electric field. Application means for sequentially applying first and second electric fields to the ferroelectric capacitor, and by detecting a change in polarization of the ferroelectric capacitor, data stored in the ferroelectric capacitor is read to a data line. A ferroelectric memory comprising a data reading means. 9. A transfer gate having a first charge input / output terminal connected to a data line, a first electrode connected to a second charge input / output terminal of the transfer gate, and a second electrode connected to a drive voltage. A memory cell consisting of a ferroelectric capacitor connected to a line, a precharge means for precharging the data line, a non-conduction of the transfer gate, and precharging the data line by the precharge means, Under the condition that the transfer gate is made conductive, first and second electric fields having opposite directions such that the ferroelectric capacitor changes polarization in response to a change in electric field are applied to the ferroelectric capacitor. Drive voltage supply means for applying a drive voltage for sequentially applying to the second electrode of the ferroelectric capacitor via the drive voltage line, and the transfer gate is made non-conductive.
After precharging the data line, the transfer gate is made conductive, and the first and second electric fields are sequentially applied to the ferroelectric capacitor to read the data stored in the memory cell to the data line. A ferroelectric memory characterized by being configured to emit. 10. A first charge input / output terminal is connected to a first data line, and the i-th (where i = 1, 3, ..., 2n−
1) The i-th transfer gate whose conduction / non-conduction is controlled by the word line and the first electrode are connected to the second charge input / output terminal of the i-th transfer gate, and the second electrode is connected to the second electrode. An i-th memory cell including an i-th ferroelectric capacitor connected to an i-drive voltage line and a first charge input / output terminal connected to a second data line,
I + th, whose conduction and non-conduction are controlled by the +1 word line
No. 1 transfer gate and the first electrode are connected to the second charge input / output terminal of the (i + 1) th transfer gate, and the second electrode is connected to the (i + 1) th drive voltage line. A ferroelectric including an (i + 1) th memory cell including a capacitor, a sense amplifier that amplifies a voltage difference between the first and second data lines, and a column selection gate that selects the first and second data lines. In the body memory, the precharge means for precharging the first and second data lines and the transfer gates for the first, second, ... After precharging the first and second data lines, the ferroelectric capacitor of the selected memory cell is polarized in response to the change of the electric field under the condition that the transfer gate of the selected memory cell is made conductive. Like to change A driving voltage for sequentially applying first and second electric fields having opposite directions to the ferroelectric capacitors of the selected memory cell is applied to the selected memory cell via the selected driving voltage line. Drive voltage supply means for applying to the second electrode of the ferroelectric capacitor, the first, second, ..., 2n transfer gates are made non-conductive, and the first and second data lines are provided. After precharging, the selected transfer gate is made conductive, and the first and second electric fields are sequentially applied to the ferroelectric capacitors of the selected memory cell, whereby the selected memory cell is A ferroelectric memory, which is configured to read data to be stored on a corresponding data line and amplify a voltage difference between the first and second data lines. 11. The driving voltage is smaller than the strength of the electric field applied to the ferroelectric capacitor when writing the data, and the strength of the second electric field is the first electric field. 11. The ferroelectric memory according to claim 9 or 10, wherein the voltage is smaller than the strength of the electric field. 12. The drive voltage supply means reverses the direction so that the ferroelectric capacitor changes polarization in response to a change in an electric field at the time of rewriting data, and the strengths thereof are respectively reversed. Is configured to supply a drive voltage for sequentially applying a third electric field and a fourth electric field, which are higher than the strengths of the first electric field and the second electric field, to the ferroelectric capacitor. The ferroelectric memory according to claim 9, 10 or 11. 13. The drive voltage supply means has a read margin when a logic 1 is written in the ferroelectric capacitor and a read margin when a logic 0 is written in the ferroelectric capacitor. 13. The ferroelectric memory according to claim 9, wherein the ferroelectric memory is configured to supply drive voltages that are the same or substantially the same. 14. The precharge means precharges the data line to a voltage that is ½ to approximately ½ of the internal power supply voltage.
The ferroelectric memory according to 1, 12, or 13. 15. The parasitic capacitance C _BL of the data line has a logic 1
3. The method of reading data in a ferroelectric memory according to claim 1, wherein the potential difference appearing on the data line when reading data of logic 0 is set to a value that is substantially the maximum or less. 16. The parasitic capacitance C _BL of the first data line is
4. The method of reading data in a ferroelectric memory according to claim 3, wherein the potential difference appearing on the data line when reading data of logic 1 and logic 0 is set to a value that is substantially the maximum or less. 17. The one of the first and second electric fields is higher than the internal power supply voltage, and the voltage appearing on the data line at the time of reading increases.
7. A method of reading data in a ferroelectric memory according to item 6. 18. The ferroelectric capacitor comprises Pb (Z
The ratio of the parasitic capacitance C _{BL of the} data line to the capacitance PrS of the ferroelectric capacitor, including r, Ti) O ₃ , is substantially 0.5 [V ⁻¹ ] <(C _BL [F] / 18. The method of reading data in a ferroelectric memory according to claim 17, wherein the relationship PrS [C]) <2 [V ^-1 ] is satisfied. 19. The parasitic capacitance C _BL of the data line has a logic 1
10. The ferroelectric memory according to claim 8 or 9, wherein the potential difference appearing on the data line when data of logic 0 is read is set to a value that is substantially the maximum or less. 20. The parasitic capacitance C _BL of the first data line is
11. The ferroelectric memory according to claim 10, wherein the potential difference appearing on the data line when reading data of logic 1 and logic 0 is set to a value that is substantially the maximum or less. 21. One of the first and second electric fields is higher than an internal power supply voltage, and the voltage appearing on the data line at the time of reading increases.
0. The ferroelectric memory described in 0. 22. The ferroelectric capacitor comprises Pb (Z
The ratio of the parasitic capacitance C _{BL of the} data line to the capacitance PrS of the ferroelectric capacitor, including r, Ti) O ₃ , is substantially 0.5 [V ⁻¹ ] <(C _BL [F] / 22. The ferroelectric memory according to claim 21, having a relationship of PrS [C]) <2 [V ^-1 ]. 23. A ferroelectric memory comprising a memory cell having a ferroelectric capacitor as a storage medium and a dummy cell having a ferroelectric capacitor, wherein data is stored according to a polarization direction of the ferroelectric capacitor of the memory cell. (A) applying a first drive voltage to a ferroelectric capacitor of the memory cell, and (b) first and second data lines according to the data stored in the memory cell. One of the two voltages is generated, and (c) the first capacitor is applied to the ferroelectric capacitor of the dummy cell.
A second driving voltage lower than the driving voltage is applied to generate a reference potential, and (d) the first and second voltages generated in the step (b) are discriminated based on the reference potential. A method of reading data in a ferroelectric memory, comprising the steps of reading the data. 24. The step (c) includes the step (c-1) of setting the second drive voltage of the dummy cell so that the reference potential is generated between the first and second voltages. 24. The method of reading data in a ferroelectric memory according to claim 23, comprising: 25. The step (c) includes the step (c) of setting the second drive voltage of the dummy cell to a necessary minimum value.
25. The method of reading data in a ferroelectric memory according to claim 23, further comprising: -2). 26. The step (c) is a step (c) of applying the second drive voltage to the ferroelectric capacitor of the dummy cell and stopping the supply of the second drive voltage after a predetermined period.
26. The method of reading data in a ferroelectric memory according to claim 23, further comprising: -3), wherein the step (d) is performed after the step (c). 27. The method of reading data in a ferroelectric memory according to claim 23, wherein the memory cells and the dummy cells are arranged in parallel and driven by the same power source. 28. The ferroelectric capacitor of the dummy cell is connected in series with a capacitor, and the second drive voltage applied to the ferroelectric capacitor is adjusted by the capacitor. Data read method in ferroelectric memory. 29. The method of reading data in a ferroelectric memory according to claim 28, wherein the capacitor connected in series to the ferroelectric capacitor of the dummy cell is composed of a ferroelectric capacitor. 30. The resistance is connected in series to the ferroelectric capacitor of the dummy cell, and the second drive voltage applied to the ferroelectric capacitor is adjusted by the resistance. Data read method in ferroelectric memory. 31. A memory cell having a ferroelectric capacitor as a storage medium, and a dummy cell having a ferroelectric capacitor, wherein data is stored according to a polarization direction of the ferroelectric capacitor of the memory cell, and the data is stored at the time of reading. A ferroelectric memory in which one of a first voltage and a second voltage is generated in a data line in accordance with the above, and a first means for applying a first drive voltage to a ferroelectric capacitor of the memory cell. Second means for applying a second drive voltage lower than the first drive voltage to the ferroelectric capacitor of the dummy cell to generate a reference potential, and the first and second means generated at the time of reading data. And a third means for reading out the data by discriminating the voltage of 1 based on the reference potential. 32. The second drive voltage of the dummy cell is set so that the reference potential is generated between the first voltage and the second voltage.
The ferroelectric memory described. 33. The ferroelectric memory according to claim 31, wherein the second drive voltage of the dummy cell is set to a necessary minimum value. 34. The second drive voltage is applied to a ferroelectric capacitor of the dummy cell, and after a predetermined period of time, the second drive voltage is applied to the second capacitor.
4. The supply of the drive voltage according to claim 1 is stopped, and then the data is read out.
3. The ferroelectric memory according to any one of 3. 35. The ferroelectric memory according to claim 31, wherein the memory cells and the dummy cells are arranged in parallel and are driven by the same power source. 36. A capacitor connected in series to a ferroelectric capacitor of the dummy cell, wherein the second drive voltage applied to the ferroelectric capacitor is adjusted by the capacitor. 36. The ferroelectric memory according to claim 35. 37. The ferroelectric memory according to claim 36, wherein the capacitor connected in series to the ferroelectric capacitor of the dummy cell is composed of a ferroelectric capacitor. 38. A resistor connected in series to the ferroelectric capacitor of the dummy cell, wherein the second drive voltage applied to the ferroelectric capacitor is adjusted by the resistor. The ferroelectric memory according to claim 35. 39. Data in a non-volatile ferroelectric memory that uses a ferroelectric capacitor and operates substantially in a DRAM mode during normal use, and retains data by remanent polarization of the ferroelectric capacitor when the power is cut off. (A) When the power is turned on, the potential of the plate electrode and the bit line is set to substantially one half of the internal power supply voltage (Vcc), and (b) the potential of the plate electrode. To Vcc / 2 → (Vcc
/ 2 + Vα) → (Vcc / 2−Vβ) → Vcc / 2,
(However, Vα and Vβ are first and second predetermined voltages)
The method for reading data in a ferroelectric memory is characterized in that the data is converted from remanent polarization into accumulated charges that retain information in a DRAM mode when the power is turned on. 40. A non-volatile ferroelectric memory which uses a ferroelectric capacitor, operates substantially in a DRAM mode during normal use, and retains data by residual polarization of the ferroelectric capacitor when the power is cut off. Then, when the power is turned on, a first voltage setting means for setting the potentials of the plate electrode and the bit line to substantially one half of the internal power supply voltage (Vcc), and the potential of the plate electrode is Vcc / 2. → (Vcc / 2 +
Vα) → (Vcc / 2−Vβ) → Vcc / 2, (however,
Vα and Vβ include a second voltage setting unit that changes in the order of first and second predetermined voltages), and when the power is turned on, the accumulated charge that holds the information in the DRAM mode from the remnant polarization of the data. A nonvolatile ferroelectric memory characterized by being converted into.