JP3868660B2 - Semiconductor memory device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and in particular, in a nonvolatile ferroelectric memory, solves a problem that a read signal to a bit line decreases due to a change or deterioration of a ferroelectric film such as Imprint or Depolarization, Provided is a semiconductor memory device that secures a sufficient amount of read signals and has high reliability.
[0002]
[Prior art]
Today, semiconductor memories are used everywhere from the main memory of large computers to personal computers, home appliances, mobile phones, and the like. As types of semiconductor memory, volatile DRAM (Dynamic RAM), SRAM (Static RAM), nonvolatile MROM (Mask ROM), Flash E2PROM (Electrical Erasable Programmable ROM), and the like are on the market. In particular, although DRAM is a volatile memory, it is excellent in terms of its low cost (cell area 1/4 compared to SRAM) and high speed (compared to FlashE2PROM). Is the current situation. The rewritable and non-volatile Flash E2PROM is non-volatile and can be turned off. However, the number of times of rewriting (the number of times of W / E) is only about 10 6, and writing takes about microseconds. However, the market is not as high as DRAM because of the disadvantage that it is necessary to apply a high voltage (12 V to 22 V).
[0003]
On the other hand, a non-volatile memory FRAM (Ferroelectric RAM) using a ferroelectric capacitor has been non-volatile since it was proposed in 1980, and has been read over 10 12 times. However, since the write time has the advantage of DRAM, 3V-5V operation, etc., there is a possibility of replacing the entire memory market, and each manufacturer is developing.
[0004]
In the FRAM cell, the cell size has been reduced by the simplification and miniaturization of the cell structure along with the times, from the SRAM + Shadow Memory configuration at the time of development to the 2transistor + 2Capacitor configuration, and the development of DRAM.
[0005]
FIG. 22 shows a memory cell having a 1transistor + 1Capacitor configuration of the FRAM of Conventional Example 1 and its operation method. The configuration of the memory cell is the same as that of DRAM. The differences are as follows: (1) A DRAM uses a paraelectric material as a capacitor, while an FRAM uses a ferroelectric material, and (2) a DRAM, When the memory cell transistor is turned on, the electric charge stored in the capacitor is read out to the bit line. However, in the FRAM, memory cell data is not read out only by turning on the memory cell transistor, the / EQL is set to High, and the bit line Is precharged to Vss, and when active, / EQL is set to low and floating, the memory cell transistor is turned on, the plate line is raised from Vss to Vdd, and the potential of Vdd is applied to both ends of the ferroelectric capacitor. Only after application is the polarization information read out to the bit line. For example, “1” Data is obtained when a large charge is read to the bit line after polarization inversion, and “0” Data is obtained when a small charge is read to the bit line without polarization. The signal is amplified by a sense amplifier and data is read out.
[0006]
Further, the present inventor has proposed a new memory cell configuration that realizes a high-speed operation while reducing the memory cell size with respect to the FRAM of the conventional example 1, such as Japanese Patent Application Laid-Open No. 10-255483 and Japanese Patent Application No. 9-346404. (Unpublished).
[0007]
FIG. 23 shows a memory cell configuration and an operation example of the prior art 2 shown in Japanese Patent Application No. 9-346404 which is a prior application. In FIG. 23, one cell transistor and one ferroelectric capacitor are connected in parallel to form one memory cell, which is connected in series to form a block, and one end is connected via a block selection transistor. It is connected to the bit line and the other end is connected to the plate line. By providing two block selection signals (BS0, BS1) and two plate lines (PL (/ BL), PL (BL)), cell data is read to either bit line pair (/ BL, BL). A Folded bit line configuration is realized in which the other is a Reference bit line.
[0008]
In operation, all word lines (WL0 to WL7) are set to high level during standby, and all cell transistors are turned on to electrically short-circuit both ends of the ferroelectric capacitor, thereby holding cell data. When standby, / EQL is set to High and the bit line is precharged to Vss.When active, / EQL is set to Low and Floating, or before or after, any selected word line ( Only WL2) is set to Low level, and then WL2 is Low and the bit line is Floating. Then, the block selection transistor BS0 is set High and the Plate potential is raised from Vss to Vdd. As a result, the plate potential is applied to one end of the ferroelectric capacitor of the selected cell, the potential of the floating bit line is applied to the other end of the ferroelectric capacitor, and the polarization information is read out to the bit line. It becomes a mechanism. On the other hand, the ferroelectric capacitor of the non-selected cell in the selected block is shorted because the word line is high, and polarization information is retained. Therefore, for example, when a large charge is read to the bit line after polarization reversal, it is “1” Data, and when a small charge without polarization is read to the bit line, it is “0” Data. Although the circuit configuration and characteristics are also different from those of the conventional FRAM, it is understood that the principle of reading data from the ferroelectric capacitor is the same as that of the conventional FRAM. The signal is amplified by a sense amplifier and data is read out.
[0009]
As described above, there are mainly two types of ferroelectric memories using the ferroelectric capacitor, the conventional examples 1 and 2. In either case, the deterioration of the characteristics of the ferroelectric capacitor film causes the memory cell to the bit line. There is a problem that the read signal decreases. As a problem of deterioration of characteristics, that is, reliability, 1) Depolarization in which the amount of remanent polarization at 0V bias decreases with time (also called Relaxation), 2) Hysteresis curve of ferroelectric film in the direction of ± voltage Imprint to shift, and 3) Fatigue, etc., that the polarization amount decreases when Read / Write is repeated.
[0010]
FIG. 24 shows typical Imprint characteristics. The dotted hysteresis curve in FIG. 24A shows a normal curve without Imprint. The thick hysteresis curve is a hysteresis curve after writing "0" Data to the ferroelectric capacitor and leaving it for a long time at the position of □. Imprint that shifts the hysteresis curve in the positive (right) direction The curve which generate | occur | produced is shown. Similarly, the dotted hysteresis curve in FIG. 24B is a normal curve without Imprint. The thick hysteresis curve is the hysteresis curve after writing "1" Data on the ferroelectric capacitor and leaving it for a long time at the □ position. Imprint that the hysteresis curve shifts in the negative (left) direction The curve which generate | occur | produced is shown.
[0011]
Next, let's see how the read signal changes in two cases. For example, the potential read out to the bit line of "1" Data is drawn from the position of 0V bias of "1" Data by the amplitude potential of the bit line, minus (left) in parallel to the X axis. A load curve having a slope of the value of the load capacitance Cb of the bit line is written, and a value crossing the hysteresis curve can be said to be a read potential. In actual operation, when the bit line is Vss and the plate line is raised from Vss to Vdd, the cell node potential of Vdd drops the charge Q, and the bit line potential rises by receiving the charge Q. Correspond. In terms of the hysteresis curve, the capacitor outputs the charge Q from the 0V position on the hysteresis curve and goes in the negative direction. The bit line receives the same charge Q from the -Vdd position and rises from -Vdd. The crossing point is the actual bit line potential of "1" Data when -Vdd is regarded as the Vss potential of the actual operation.
[0012]
Similarly, the potential read out to the bit line of "0" Data is drawn from the point of 0V bias of "0" Data to the minus (left) in parallel to the X axis by the amplitude potential of the bit line. A load curve having a slope of the value of the load capacitance Cb of the bit line is written, and a value crossing the hysteresis curve can be said to be a read potential. When the imprint of the dotted line in FIGS. 24A and 24B does not occur, the read potential of “1” and “0” Data is represented by ◯, and the difference between the two ◯ is “1” data and “0”. It can be said that there is a difference in data. In the 2T2C configuration cell, this becomes the read potential, and in the 1T1C configuration, the Reference potential is brought between these two circle potentials. Similarly, when Imprint occurs, two “black circles” correspond to “1” Data and “0” Data just by shifting the locus of the hysteresis curve.
[0013]
In the case of Imprint after leaving "0" Data as shown in Fig. 24 (a), the hysteresis curve only shifts to the right, so when you read "1" Data, the operation starts from the 0V position of the hysteresis curve. The trajectory to the point “black circle” undergoes polarization reversal and passes through a steep slope, and a large charge is released with a slight advance of the voltage of the trajectory. As a result, the read potential of “1” Data rises. Looking at "0" Data readout, the locus from the 0V position of the hysteresis curve to the operating point "blackening" passes through a gentle slope with greater polarization saturation, and a small charge is released with the advance of the voltage of the large locus. As a result, the read potential of “0” Data is lowered. As a result, Imprint increases the read signal.
[0014]
On the other hand, in the case of Imprint after leaving “1” Data as shown in FIG. 24 (b), the hysteresis curve shifts to the left. The trajectory from the position to the operating point “black circle” passes through a region where polarization inversion is unlikely to occur at first, and finally a charge due to polarization inversion is released from the point where a large negative voltage was applied. As a result, 1 "Data read potential drops. Looking at "0" Data readout, the locus from the 0V position of the hysteresis curve to the operating point "black" finally enters the polarization saturation region from the polarization inversion region first, so a large charge is released with a small voltage. As a result, the read potential of “1” Data is raised. As a result, the imprint causes a significant decrease in the read signal, resulting in malfunctions, a decrease in operation margin, deterioration in reliability, and the like.
[0015]
[Problems to be solved by the invention]
As described above, in the conventional FRAM, when the imprint of the ferroelectric capacitor occurs, the read potential of “1” Data decreases and the read potential of “0” Data increases. As a result, in both the 1T1C configuration and the 2T2C configuration, There has been a problem in that the read potential from the ferroelectric capacitor to the bit line is decreased, causing malfunction, a decrease in operation margin, deterioration in reliability, and the like.
[0016]
The present invention has been made in consideration of the above circumstances, and the object of the present invention is to suppress a decrease in readout signal even if Imprint occurs when data is left unwritten in a ferroelectric capacitor. It is an object of the present invention to provide a more stable and highly reliable ferroelectric memory by ensuring a stable read signal.
[0017]
[Means for Solving the Problems]
In the first invention of the present application, a memory cell is composed of a first transistor and a first ferroelectric capacitor having one end connected to the source electrode and the other end connected to the drain electrode. The memory cell units are connected in series to form a memory cell unit. One end of the memory cell unit is connected to the bit line via the second transistor, and the other end is connected to the plate line to form a memory cell block. In a driving method of a semiconductor memory device in which a plurality of cell blocks are arranged to constitute a memory cell array, the plate line potential is raised to a second potential while the bit line is fixed to the first potential, and the first strong A first operation in which a first potential and a second potential are applied to both ends of the dielectric capacitor, and following this first operation, the bit line is set in a floating state while being played. A method for driving a semiconductor memory device, comprising: raising a line potential from a second potential to a higher third potential and performing a second operation of reading the charge of the first ferroelectric capacitor to a bit line. is there.
[0018]
According to a second invention of the present application, a memory cell is composed of a first transistor and a first ferroelectric capacitor having one end connected to the source electrode and the other end connected to the drain electrode. The memory cell units are connected in series to form a memory cell unit. One end of the memory cell unit is connected to the bit line via the second transistor, and the other end is connected to the plate line to form a memory cell block. In a semiconductor memory device in which a plurality of cell blocks are arranged to form a memory cell array, the plate line has a first potential, a second potential higher than the first potential, or a third potential higher than the second potential. Is a semiconductor memory device comprising a plate line potential conversion circuit for sequentially applying.
[0019]
A third invention of the present application is a memory configured by a plurality of memory cells including a first transistor and a first ferroelectric capacitor, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines. In the driving method of the semiconductor memory device having a cell array, the plate line potential is raised to the second potential while the bit line is fixed to the first potential, and the first ferroelectric capacitor is connected to both ends of the first ferroelectric capacitor. Following the first operation of applying the potential and the second potential, and following the first operation, the plate line potential is raised from the second potential to a higher third potential while the bit line is in a floating state. A method for driving a semiconductor memory device is characterized in that a second operation of reading the charge of the first ferroelectric capacitor to a bit line is performed.
[0020]
According to a fourth aspect of the present invention, there is provided a memory comprising a plurality of memory cells comprising a first transistor and a first ferroelectric capacitor, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines. In a driving method of a semiconductor memory device having a cell array, a plate line potential in which a first potential, a second potential higher than the first potential, or a third potential higher than the second potential is sequentially applied to the plate line. A semiconductor memory device including a conversion circuit.
[0021]
According to a fifth aspect of the present invention, in a semiconductor memory device that stores data of “1” or “0” depending on the polarization direction of the ferroelectric capacitor, the absolute value of the voltage applied to both ends of the ferroelectric capacitor is 0V. This is a semiconductor memory device that determines “1” or “0” data from the amount of charge read when the voltage changes between a higher first voltage and a second voltage higher than the first voltage.
[0022]
A sixth invention of the present application is the semiconductor memory device according to the fifth invention, wherein the first voltage is not less than 0.3V and not more than 1V.
According to a seventh aspect of the present invention, in a semiconductor memory device in which a dummy cell is configured using a ferroelectric capacitor, a voltage applied to both ends of the ferroelectric capacitor is greater than the first voltage from the first voltage greater than 0V. This is a semiconductor memory device that generates a reference potential from the amount of charge that is read when the voltage changes up to a second voltage.
[0023]
That is, according to the present invention, in a ferroelectric memory using a ferroelectric capacitor, polarization information from 0 V bias of the hysteresis capacitor characteristic of the ferroelectric capacitor to a first voltage greater than 0 V is not used. , Imprint causes the hysteresis curve to shift, and in spite of “1” Data, this shift does not contribute to the read charge in the portion where the polarization inversion is small, and the second voltage higher than the first voltage from the first voltage. Since the portion with a large amount of polarization inversion up to the voltage of 1 is used, even if Imprint occurs, the read potential of “1” Data is high and signal degradation can be suppressed. In spite of “0” Data, this shift should originally have a small polarization reversal and a small read charge, but includes a portion where the polarization reversal is easy. Since the polarization information up to the first voltage greater than 0V is not used, the polarization between the first voltage and the second voltage greater than the first voltage is saturated, and the read signal is used in a small portion. Even if this occurs, the readout potential of "0" Data is low and signal degradation can be suppressed.
[0024]
In this series of operations, by fixing the bit line to the Vss potential and raising the plate line potential to the first potential, the ferroelectric capacitor is applied with the hysteresis curve from 0 V to the first potential, The charge read out to the bit line can be discarded, and then the bit line is floated and the plate line potential is raised from the first potential to a second potential higher than the first potential to the second potential. By applying a voltage up to the ferroelectric capacitor to the ferroelectric capacitor and applying a voltage during this period, the electric charge read out to the bit line can be used as a read signal, and even if Imprint is generated, signal deterioration can be suppressed.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a circuit configuration and an operation diagram of a ferroelectric memory according to the first embodiment of the present invention. This shows the Imprint influence reduction circuit operation method that can be applied to conventional ferroelectric memories. The cell array is equivalent to a 1T1C type conventional FRAM, and the amplification and equalization circuit is a Flip-Flop circuit that amplifies the signal difference between the bit lines, and three that precharge and equalize the bit line pair (/ Bl, BL) to Vss There is an equalize circuit of the transistors (Q1 to Q3). In standby mode, the Plate potential is Vss and the bit line potential is precharged to the Vss potential because the equalize signal / EQL is High. In the active cycle, first, the equalization signal / EQL is kept high, that is, the bit line is fixed to Vss, the word line (WL0) is started up, the cell transistor is turned on, and the plate line (PL0) is turned on. The potential is raised by Voff, specifically, for example, about 0.5V. By this operation, a voltage of Voff is applied to both ends of the ferroelectric capacitor, and the charge flows to the Vss line and disappears because the bit line is fixed to Vss. Second, the equalize signal / EQL is set to Low level, the bit line is set to Floating in the state of Vss, and the Plate line potential is raised from Voff to Vdd. As a result, the ferroelectric capacitor is inverted in polarity by the amount of the bit line capacitance Cb, and the charge is read out to the bit line, thereby increasing the bit line potential. At this time, the voltage applied to both ends of the ferroelectric capacitor becomes a locus that operates from Voff to (Vdd-read potential).
[0026]
FIG. 2 shows a hysteresis curve of the ferroelectric capacitor representing the operation locus of FIG. The hysteresis curve in Fig. 2 (a) is a hysteresis curve after writing "0" Data in a ferroelectric capacitor and leaving it for a long time at the position of □. The hysteresis curve is in the positive (right) direction. Shows the curve where the imprint that shifts occurs. Similarly, the hysteresis curve in Fig. 2 (b) is a hysteresis curve after writing "1" Data in the ferroelectric capacitor and leaving it for a long time at the position of □, and the voltage is in the negative (left) direction. Shows the curve where the imprint that shifts the hysteresis curve occurs. The dotted line operating point analysis indicates the operating point of the conventional readout method, and the solid line operating point analysis indicates the operating point of the operating method of FIG. 1 according to the present embodiment.
[0027]
With the method of FIG. 1, for example, the potential read to the bit line of "1" Data is minus (left) from the Voff bias position of "1" Data, minus (left) parallel to the X axis. From this point, the load curve of the slope of the value of the load capacitance Cb of the bit line is written, and the value crossing the hysteresis curve can be said to be the read potential. In actual operation, when the bit line is Vss and the Plate line is raised from Voff to Vdd, the cell node potential of (Vdd-Voff) drops the charge Q, and the bit line potential receives the charge Q. Corresponds to rising. Like the hysteresis, the potential read to the bit line of "0" Data is drawn from the Voff bias position of "0" Data to the negative (left) in parallel to the X axis by the amplitude potential of the bit line. Thus, a read curve is obtained by writing a load curve with a slope of the value of the load capacitance Cb of the bit line and intersecting the hysteresis curve. In FIG. 2, the final operating point of the conventional method, that is, the read potential of “1”, “0” Data is represented by ◯, and the final operating point of the method of FIG. The read potential of 1 "," 0 "Data is expressed as" black ". Comparing the two, Fig. 2 (a) When "0" Data is left untouched, the difference between the read potential of "1" Data and the read potential of "0" Data is worse in the method of Fig. 1 than in the conventional method. Since the hysteresis curve is shifted in the direction that is not affected by Imprint, the absolute value of the signal amount is large.
[0028]
On the other hand, when “1” Data is left unattended, the difference between the read potential of “1” Data and the read potential of “0” Data is greatly deteriorated and decreased in the conventional method. It can be seen that in the method 1, the deterioration amount is suppressed and a sufficient amount of read signal can be secured. In the 2T2C configuration cell, the potential difference between “black” and “black” becomes the read potential, and in the 1T1C configuration, the reference potential is brought between the two “black” potentials. Secure signal. The reason why there are few signals in the conventional method after leaving "1" Data written is that the Hysteris curve shifts to the left in the case of Imprint after leaving "1" Data left. The trajectory from the position of 0V to the operating point “blackening” passes through a region where polarization inversion hardly occurs at first, and finally a charge due to polarization inversion is released around the time when a large negative voltage is applied. , "1" Data read potential will drop.
[0029]
On the other hand, in the method of FIG. 1, by shifting by Voff, it is not necessary to pass through the region where the first polarization inversion hardly occurs, and the inclination of the polarization inversion region from Voff to “blackening” is steep. Since the electric charge is read out to the bit line, a large electric charge with a slight voltage movement trajectory, that is, when viewed from the bit line, the reading potential of “1” Data rises more than the reading potential of “0” Data, 1 "Data signal becomes large. In addition, in the case of "0" Data reading, in the conventional method, the locus from the position of 0V on the hysteresis curve to the operating point "black circle" finally enters the polarization saturation region from the first polarization inversion region, so a small voltage As a result, a large charge is released, and as a result, the read potential of “1” Data rises. However, since the first polarization inversion region is not used in the method of FIG. 1, the read potential of the bit line does not increase so much. , "0" Data signal increases (decreases). As a result, the decrease in read signal due to the occurrence of Imprint can be suppressed, and a more stable and reliable ferroelectric memory can be realized.
[0030]
In general, the Imprint deviation is about 1V at the maximum, and conversely, if it is less than 0.3V, it is desirable that Voff is not less than 0.4V and not more than 1V considering that it is not enough to take circuit measures.
[0031]
In short, the effect is that the hysteresis curve slope between 0V and Voff causes the signal to decrease when “0” Data is larger than “1” Data. One solution is to set Voff at the point where “1” Data starts to become larger than “0” Data. That is, the maximum Imprint voltage value is set to Voff. In addition, since the Imprint is effective in the operation locus shown in FIG. 2, the circuit operation method is not limited to the circuit and operation method shown in FIG.
[0032]
FIG. 3 shows an operating point analysis in the case of both the conventional method and the method of FIG. 1 when both Imprint and Depolarization (also called “Relaxation”) occur. Normally, a ferroelectric film has a problem that the residual polarization amount at 0 V bias is reduced if it is left after the end of writing. Therefore, even when both imprint and depolarization occur, it is necessary to increase the signal under the condition that the present method is the minimum readout signal than the conventional method. In order to investigate this, FIG. 3 shows an operating point analysis with a hysteresis curve when Imprint and Depolarization occur. “O” indicates the read potential of “1” and “0” Data in the conventional method, and “Black” indicates the read potential of “1” and “0” Data in the method of FIG. It can be seen that even when the worst “1” data is left, the method of FIG. 1 is more effective than the conventional method in that the difference in read potential between “1” data and “0” data is greater.
[0033]
FIG. 4 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof showing the second embodiment of the present invention. The only difference from FIG. 1 is that there are transistors that precharge the bit line to Vss, but the equalizing transistors that make the bit line pair the same potential are omitted. Other circuit operations are the same as those in FIG. 1, and the effects are the same as those in FIGS.
[0034]
FIG. 5 shows a circuit configuration and an operation diagram of a ferroelectric memory according to the third embodiment of the present invention. The only difference from FIG. 1 is that a 2T2C type memory cell in which memory cells are connected to both bit lines of a bit line pair is applied to one word line. Other circuit operations are the same as those in FIG. 1, and the effects are the same as those in FIGS.
[0035]
FIG. 6 shows a circuit configuration and an operation diagram of a ferroelectric memory according to the fourth embodiment of the present invention. The difference from Fig. 1 is the same until the Plate line is raised to Voff while the bit line is fixed to Vss, then the bit line is set to Floating, and then the Plate line is raised to Vdd, but then Plate is temporarily set to Vss. Then, sense amplification is performed, and then the plate line is raised and lowered again from Vss to Vdd and from Vdd to Vss. It has been reported that once the plate line is lowered to Vss and sensed, the dispersion component of the paraelectric component of the ferroelectric capacitor can be canceled, and the plate line of the present invention is applied to the method of raising and lowering the plate twice. This is an example in which a method of increasing two steps from Vss to Voff and Voff to Vdd is combined, and further, the 2T2C configuration of FIG. 5 is combined. Other circuit operations are the same as those in FIG. 1, and the effects are the same as those in FIGS.
[0036]
FIG. 7 shows a circuit configuration and an operation diagram of a ferroelectric memory according to the fifth embodiment of the present invention. This shows an Imprint influence reduction circuit operation method applicable to the ferroelectric memory of Japanese Patent Application No. 9-346404, which is a prior application. In the cell array, a plurality of memory cells in which one cell transistor and one ferroelectric capacitor are connected in parallel are connected in series to form a cell block, and one end is connected to a bit line through a block selection transistor. This is equivalent to the prior application FRAM in which the other end is connected to the plate line, and the amplification equalizing circuit includes a flip-flop circuit for amplifying a signal difference between the bit lines, and a bit line pair (/ Bl, BL) as Vss. There is an equalize circuit of three transistors (Q1 to Q3) for precharge & equalize.
[0037]
As for the operation, during standby, the plate potential is Vss and the bit line potential is precharged to the Vss potential because the equalize signal / EQL is high. In the active cycle, first, the equalize signal / EQL remains High, that is, the bit line is fixed to Vss, the selected word line (WL 2) is lowered, the cell transistor is turned OFF, and the block selection line BS0 is started, the block selection transistor is turned on, and the potential of the plate line (PL (/ BVL)) is raised by Voff, specifically, for example, about 0.5V. By this operation, a voltage of Voff is applied to both ends of the ferroelectric capacitor of the selected cell, and the charge flows to the Vss line and disappears because the bit line is fixed to Vss. At this time, the ferroelectric capacitors of the non-selected cells of the selected block are shorted and protected. Second, the equalize signal / EQL is set to Low level, the bit line is set to Floating in the state of Vss, and the Plate line potential is raised from Voff to Vdd. As a result, the ferroelectric capacitor is inverted in polarity by the amount of the bit line capacitance Cb, and the charge is read out to the bit line, thereby increasing the bit line potential. At this time, the voltage applied to both ends of the ferroelectric capacitor becomes a locus that operates from Voff to (Vdd-read potential). The locus of the potential applied to the ferroelectric capacitor of the selected cell at this time is equivalent to that in FIGS. 2 and 3, and as a result, the decrease in the read signal due to the generation of Imprint can be suppressed, and the stable and highly reliable strength can be suppressed. A dielectric memory can be realized.
[0038]
7 uses a Folded bit line configuration. For example, when the upper cell block is selected, BS0 and PL (/ BL) are selected, cell data is read to the / BL side, and the BL side is a reference. For example, when the lower cell block is selected, BS1 and PL (BL) are selected, cell data is read to the BL side, and the / BL side is the reference bit line.
[0039]
FIG. 8 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to the sixth embodiment of the present invention. The only difference from FIG. 7 is that although there are transistors that preharge the bit line to Vss, the equalizing transistors that make the bit line pair the same potential are omitted. Other circuit operations are the same as those in FIG. 7, and the effects are the same as those in FIGS.
[0040]
FIG. 9 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to the seventh embodiment of the present invention. The difference from Fig. 7 is that the Plate potential is set to Voff potential from the beginning during standby, WL2 is lowered, BS0 is raised, and the bit line is fixed to Vss. It is equivalent to FIG. 8 that the potential of Voff is automatically applied and the charge in this portion can be discarded. After that, the bit line is floated, the plate line is raised to Vdd, the charge is read, sense amplification is performed, the plate is further lowered, and after rewriting is completed, BS0 is lowered, WL2 is raised, the plate line is returned to Voff and the Preharge state The point which enters is different. Other circuit operations are the same as those in FIG. 8, and the effects are the same as those in FIGS. This system uses the feature that the cell polarization is not destroyed because the ferroelectric capacitor is short even if the plate potential during standby is set higher than 0V in the ferroelectric memory configuration of the prior application. Yes. In this method, first, since the plate potentials of all the non-selected cell arrays in the chip are set to Voff, it contributes as a stabilization capacitor, and thus the variation in the plate potential of the selected cell array is reduced. is there. Secondly, since the precharge is increased to Voff, even if the operation is slow, the access time is not affected. As shown in FIG.
[0041]
FIG. 10 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to the eighth embodiment of the present invention. The only difference from FIG. 9 is that there are transistors that preharge the bit line to Vss, but the equalizing transistors that bring the bit line pair to the same potential are omitted. Other circuit operations are the same as those in FIG. 9, and the effects are the same as those in FIGS.
[0042]
FIG. 11 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to the ninth embodiment of the present invention. The difference from Fig. 7 is that in order to make 2T2C configuration, one type of block selection transistor and one type of plate line are integrated, and from both / BL and BL, "1", "0" or "0", "1 This is the point of reading the data of "" on the bit line. Other circuit operations are the same as those in FIG. 7, and the effects are the same as those in FIGS.
[0043]
FIG. 12 shows a circuit configuration and operation diagram of a ferroelectric memory according to the tenth embodiment of the present invention. FIG. 12 is a combination of FIG. 9 and FIG. 11 and has both effects. Other circuit operations are the same as those in FIG. 7, and the effects are the same as those in FIGS.
[0044]
FIG. 13 shows a plate line driving circuit and its operation timing chart showing the eleventh embodiment of the present invention. During standby, CK1 is High and the Plate line PL is Vss. During Active, CK1 is Low, CK3 is High, / CK3 is Low, and the bit line is fixed at Vss, while the potential from the Voff power supply is maintained. To PL and set the Plate line to Voff. After that, the bit line is set to Floating, CK3 is set to Low, / CLK3 is set to High to shut off from the Voff power source, and CK2 is set to Low to transmit the Vdd potential to Plate and raise the plate line to Vdd. Thereafter, the sensing operation is performed, and then CK2 is set to High and CK1 is set to High to return the Plate potential to Vss. By this series of operations, a circuit for driving the plate line used in FIGS. 1 and 7 can be realized, and the effects shown in FIGS. 2 and 3 can be exhibited.
[0045]
FIG. 14 shows a plate line driving circuit and its operation timing chart showing the twelfth embodiment of the present invention. The difference from FIG. 13 is that the / CK3 control line and the PMOS transistor that inputs it to the gate are omitted. Since the Voff potential is as low as about 0.5V, the PMOS can be omitted and the plate drive circuit can be made smaller. By this series of operations, a circuit for driving the plate line used in FIGS. 1 and 7 can be realized, and the effects shown in FIGS. 2 and 3 can be exhibited.
[0046]
FIG. 15 shows a plate line driving circuit and its operation timing chart showing the thirteenth embodiment of the present invention. This circuit can be used in FIG. In standby mode, CK3 is High, / CK3 is Low, and Plate line PL is Voff. When Active, the ferroelectric capacitor is selected by selecting the cell while fixing the bit line to Vss. A voltage of Voff is applied to the capacitor to release charges. Thereafter, the bit line is set to Floating, CK3 is set to Low, and / CK3 is set to High, then the Vdd potential is transmitted to Plate and the plate line is increased to Vdd. Thereafter, after the sensing operation is performed, the Plate potential is returned to Vss by setting CK2 to High and CK1 to High. Then, after closing the cell, CK3 is set to High and / CK3 is set to Low again to return to Standby. By this series of operations, a circuit for driving the Plate line used in FIG. 9 and the like can be realized, and the effects as shown in FIGS. 2 and 3 can be exhibited.
[0047]
FIG. 16 shows a Voff power generation circuit example showing the fourteenth embodiment of the present invention. It has a feedback circuit using a stabilizing capacitor and an operational amplifier that generates the same potential as the Vref potential. Since the Vref potential is as low as 0.3V to 1V, only the Band-gap Reference circuit or the like is suitable for Vref. When Vref and Voff potentials are different, the input of the operational amplifier may be obtained by lowering the Voff potential by resistance division. With this circuit, a power source for the circuit for driving the plate line can be realized, and the effects shown in FIGS. 2 and 3 can be exhibited.
[0048]
FIG. 17 shows a dummy cell according to the fifteenth embodiment of the present invention. Even in the dummy cell, the bit line potential is fixed to Vss, the plate potential is raised to Voff, the bit line is then floated, and then the plate potential is set to any potential (Vdd or VDPL). The potential of the line can be generated. Even if it is a dummy cell, when a ferroelectric capacitor is used, it is affected by Imprint and Depolarization, and the effects shown in FIGS. 2 and 3 can be exhibited. In the figure, the upper left figure shows a case where a dummy cell is provided for each bit line, and the upper right figure shows a case where a dummy cell is shared by a bit line pair. By raising the Plate potential to Voff while keeping the DRST signal High, the charge on the locus from Vss to Voff of the ferroelectric capacitor can be released in the dummy cell. Thereafter, by raising the dummy word line DWL0 and raising Plate to VDPL or Vdd, the Reference potential can be generated.
[0049]
FIG. 18 shows a dummy cell according to the sixteenth embodiment of the present invention. The operation is slightly different from that of FIG. 17 with the same circuit configuration as that of FIG. The effect is the same as in FIG. 18, and the effect as shown in FIGS. 2 and 3 can be exhibited. 17 is different from FIG. 17 in that the DRST signal is set to Low and DWL0 is raised while the bit line is fixed to Vss and then the Plate potential is set to Voff to release the charge.
[0050]
FIG. 19 shows a dummy cell applicable to the ferroelectric memory of the prior application, showing the seventeenth embodiment of the present invention. / Fix the bit line to Vss while keeping EQL high, set DRST to low, set DWL2 to low, set DBS0 to high, and raise the dummy plate line from Vss to Voff. A voltage of Voff is applied to and a charge is released. After that, the / EQL is set to Low and the bit line is set to Floating, then the Plate potential is raised to Vdd or VDPL, and the Reference potential is generated at the portion not affected by Imprint. Therefore, as shown in FIGS. Can be effective.
[0051]
FIG. 20 shows a dummy cell applicable to the ferroelectric memory of the prior application, showing the eighteenth embodiment of the present invention. By raising the dummy plate line from Vss to Voff while DRST is set to High, it is possible to apply a voltage of Voff across the ferroelectric capacitor in the dummy cell block, and the charge is discharged. After that, DRST is set to Low, DBS0 is set to High and connected to the bit line, the Plate potential is raised to Vdd or VDPL, and the Reference potential is generated in the portion not affected by Imprint. The effect as shown can be demonstrated.
[0052]
FIG. 21 shows a dummy cell applicable to the ferroelectric memory of the prior application, showing the nineteenth embodiment of the present invention. When the DPL potential is already set to Voff during standby and the bit line potential is fixed to Vss during Active, DWL2 is lowered and DBS0 is raised, so that the voltage of Voff can be applied across the ferroelectric capacitor. , Excess charge is released. After that, / EQL is lowered, the bit line is floated, and then the DPL potential is raised from Voff to Vdd or VDPL potential, and the Reference potential is generated at the portion not affected by Imprint. After that, DBS0 is lowered, DRST is set to High, “0” potential is written to the ferroelectric capacitor of the dummy cell, DPL is returned to Voff, DRST is set to Low, DWL2 is returned to High, and / EQL is set to High. Then, it becomes the same as the Standby state. This method can also exhibit the effects as shown in FIGS.
[0053]
【The invention's effect】
As described above in detail, according to the present invention, even if Imprint occurs, the bias portion on the hysteresis curve where the readout signal decreases due to the influence of Imprint can be removed, and the decrease in the readout signal is suppressed sufficiently. By securing a stable read signal, a more stable and highly reliable ferroelectric memory can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit configuration of a ferroelectric memory and an operation diagram thereof showing a first embodiment of the present invention.
FIG. 2 is an operation trajectory on a hysteresis curve with Imprint showing the effect of the first embodiment.
FIG. 3 is an operation locus on a hysteresis curve having Imprint and Depolarization, showing the effect of the first embodiment.
FIG. 4 is a circuit configuration and operation diagram of a ferroelectric memory showing a second embodiment of the present invention.
FIG. 5 is a circuit configuration of a ferroelectric memory and its operation diagram showing a third embodiment of the present invention.
FIG. 6 is a circuit configuration of a ferroelectric memory and its operation diagram showing a fourth embodiment of the present invention.
FIG. 7 is a circuit configuration and operation diagram of a ferroelectric memory according to a fifth embodiment of the present invention.
FIG. 8 is a circuit configuration and operation diagram of a ferroelectric memory according to a sixth embodiment of the present invention.
FIG. 9 is a circuit configuration of a ferroelectric memory and its operation diagram showing a seventh embodiment of the present invention.
FIG. 10 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to an eighth embodiment of the present invention.
FIG. 11 is a circuit configuration of a ferroelectric memory and its operation diagram showing a ninth embodiment of the present invention.
FIG. 12 is a circuit configuration of a ferroelectric memory and its operation diagram showing a tenth embodiment of the present invention.
FIG. 13 is a circuit configuration of a ferroelectric memory and its operation diagram showing an eleventh embodiment of the present invention.
FIG. 14 is a circuit diagram of a ferroelectric memory and its operation diagram showing a twelfth embodiment of the present invention.
FIG. 15 is a plate line driving circuit and its operation timing chart showing the thirteenth embodiment of the present invention.
FIG. 16 is a plate line driving circuit and its operation timing chart showing the fourteenth embodiment of the present invention.
FIG. 17 is a plate line driving circuit and its operation timing chart showing the fifteenth embodiment of the present invention.
FIG. 18 shows an example of a Voff power supply generation circuit according to the sixteenth embodiment of the present invention.
FIG. 19 shows a dummy cell according to a seventeenth embodiment of the present invention.
FIG. 20 shows a dummy cell according to the eighteenth embodiment of the present invention.
FIG. 21 shows a dummy cell according to a nineteenth embodiment of the present invention.
FIG. 22 is a circuit configuration of an FRAM ferroelectric memory according to Conventional Example 1 and an operation diagram thereof.
FIG. 23 is a circuit configuration of an FRAM ferroelectric memory according to Conventional Example 2 and its operation diagram;
FIG. 24 is a typical Imprint characteristic diagram.
[Explanation of symbols]
/ BL, BL bit line
PL, PLi, PL (/ BL), PL (BL) Plate wire
WL, WLi Word line
/ EQL bit line Vss Precharge signal
BSi block selection line
DWLi dummy word line
DRST Dummy cell reset signal
Voff Bias voltage to ferroelectric capacitor
CK1, CK2, CK3, / CK3 Plate potential control signal
Vref Reference potential
Ci coupling capacity
Block selection line for DBSi dummy cell
DWLi dummy word line
DPL dummy plate line
VDWL Dummy word line potential
VDPL dummy plate potential

Claims (5)

  A memory cell is composed of a first ferroelectric capacitor and a first ferroelectric capacitor having one end connected to the source electrode and the other end connected to the drain electrode, and a plurality of the memory cells are connected in series. One end of the memory cell unit is connected to the bit line via the second transistor, and the other end is connected to the plate line to form a memory cell block. A plurality of the memory cell blocks are arranged. In the method of driving the semiconductor memory device constituting the memory cell array, the plate line potential is raised to the second potential while fixing the bit line to the first potential, and the both ends of the first ferroelectric capacitor are Following the first operation of applying the first potential and the second potential, and the first operation, the plate line potential is set to the second voltage while the bit line is in a floating state. Higher to raise the third potential, the driving method of the semiconductor memory device and performing a second operation for reading the charges of the first ferroelectric capacitor to the bit line from.   A semiconductor memory device having a memory cell array including a plurality of memory cells including a first transistor and a first ferroelectric capacitor, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines. In the driving method, the bit line is fixed to the first potential, the plate line potential is raised to the second potential, and the first potential and the second potential are applied to both ends of the first ferroelectric capacitor. The first operation to be applied and, following the first operation, while raising the bit line, the plate line potential is raised from the second potential to a higher third potential, and the first ferroelectric is applied. A method for driving a semiconductor memory device, comprising: performing a second operation of reading a charge of a body capacitor to a bit line.   In a semiconductor memory device storing “1” or “0” data depending on the polarization direction of the ferroelectric capacitor, the absolute value of the voltage applied to both ends of the ferroelectric capacitor is from a first voltage greater than 0V. A semiconductor memory device that determines “1” or “0” data from a charge amount read when the voltage changes between a second voltage and a second voltage that is greater than the first voltage.   4. The semiconductor memory device according to claim 3, wherein the first voltage is not less than 0.3V and not more than 1V.   In a semiconductor memory device in which a dummy cell is formed using a ferroelectric capacitor, a voltage applied to both ends of the ferroelectric capacitor is between a first voltage greater than 0 V and a second voltage greater than the first voltage. A semiconductor memory device that generates a reference potential from the amount of charge that is read when it changes.

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