JP3585374B2 - Semiconductor storage device - Google Patents

Description

となる。
【００２９】
式（８）に示すように、図３（ｃ）のビット線電位Ｖ_Ｂ２は、プリチャージ電位Ｖ_Ｂ０、セルプレート電位Ｖ_Ｄ 、ビット線浮遊容量Ｃ_Ｂ 、強誘電体キャパシタ１の近似容量Ｃ_Ｓ１とＣ_Ｓ２の関係で決定されるが、一般にＣ_Ｓ１がＣ_Ｓ２より小さい時にプリチャージ電位Ｖ_Ｂ０より大きくなる傾向にある。強誘電体キャパシタ１が図４のＢ点にある場合はＣ_Ｓ１＜Ｃ_Ｓ２なので、Ｃ_Ｂ やＶ_Ｂ０やＶ_Ｄ を調整すればビット線電位Ｖ_Ｂ２はプリチャージ電位Ｖ_Ｂ０に比べ高くなる。端的に言えば、ビット線浮遊容量６から強誘電体キャパシタ１に電荷が移動するときは、強誘電体キャパシタ１に正方向の電圧がかかり、分極の変化が少ないため移動量は少ないが、強誘電体キャパシタ１からビット線浮遊容量６へ電荷が移動するときは、強誘電体キャパシタ１に負方向の電圧がかかり、分極の変化が大きいため移動量も多くなり、その差し引きの結果、ビット線５へ電荷が移動したことになり、ビット線５の電位が上がるのである。
【００３０】
また、データを読み出す前の強誘電体キャパシタ１が図４のＤ点の状態にある場合も、ビット線電位Ｖ_Ｂ２は同様にして求められるが、その場合はＣ_Ｓ１＞Ｃ_Ｓ２なので、ビット線電位Ｖ_Ｂ２はプリチャージ電位Ｖ_Ｂ０に比べ低くなる。すなわち、ビット線浮遊容量６から強誘電体キャパシタ１に電荷が移動するときは、強誘電体キャパシタ１に正方向の電圧がかかり、分極の変化が大きいため移動量は多く、強誘電体キャパシタ１からビット線浮遊容量６へ電荷が移動するときは、強誘電体キャパシタ１に負方向の電圧がかかり、分極の変化が小さいため移動量は少なく、その差し引きの結果、強誘電体キャパシタ１へ電荷が移動したことになり、ビット線５の電位が下がるのである。
【００３１】
以上の様な原理により、データ読み出し後のビット線５の電位が、データの種類によってプリチャージ電位より高くなったり低くなったりするので、プリチャージ電位をリファレンスとしたデータの判別が可能となるのである。
この実施の形態によれば、ビット線５と７のプリチャージ電位をセルプレート４のＨレベルとＬレベルとの間の電位とし、強誘電体キャパシタ１からビット線５へデータを読み出す際に、ビット線７に保たれているプリチャージ電位をリファレンス電位として増幅するようにしているため、従来、リファレンス電位を発生させるために必要としていたリファレンスセル用の強誘電体キャパシタを無くし、その設計・製造上の問題を回避することができる。また、プリチャージ電位をリファレンス電位として用い、データが読み出されるビット線５の電位がプリチャージ電位より高いか低いかということでデータを判別するため、メモリセル用の強誘電体キャパシタの特性やビット線容量のバラツキの影響は大幅に軽減され、使用中の強誘電体キャパシタ特性の変動に対しても同様である。したがって、広い動作マージンにより安定に動作し、高い信頼性を持った１Ｔｒ−１Ｃ型ＦｅＲＡＭを実現できる。
【００３２】
なお、この実施の形態では、セルプレート４のＬレベルをグランドに、Ｈレベルを電源電圧にとって説明したが、セルプレート４のＬレベルをグランドレベル以下にとって動作させることも可能で、その場合、ビット線５と７のプリチャージ電位をグランドレベルにすることも可能であり、電位供給回路３３を簡略化することができる。
【００３３】
また、ワード線３のレベルを上げた時と、セルプレート４の電位を上げた時に、強誘電体キャパシタ１とビット線５の間で電荷の移動が発生するが、電荷の移動が止まり状態が安定する前に、セルプレート４の電位を上げることや、差動増幅器１６を活性化させる動作も可能であり、アクセスタイムを短縮することができる。
【００３４】
さらに、図５は図１の半導体記憶装置での第２のデータ読みだし動作のタイミング図である。この第２のデータ読みだし動作では、図２の第１のデータ読みだし動作タイミングに対し、セルプレート４の電位ＣＰをＨレベルに上げた後に、一度Ｌレベルに戻して再びＨレベルに上げること以外は同じなので詳しい説明は割愛するが、このように、セルプレート４の電位ＣＰの上げ下げを２回以上繰り返してから、差動増幅器１６を活性化させる動作も可能である。
【００３５】
〔第２の実施の形態〕
図６は本発明の第２の実施の形態の半導体記憶装置のメモリセル列の回路図であり、１Ｔｒ−１Ｃ型ＦｅＲＡＭを示す。図６において、２１はメモリセル用の強誘電体キャパシタ、２２はメモリセルへアクセスするＮＭＯＳトランジスタからなるアクセス用トランジスタ、２３はワード線、２４はセルプレート、１８はデータ線、２０はビット線７とデータ線１８を接続するトランスファーゲートで、制御信号φ_ｔ２によってそれらの電気的導通・遮断を制御することができる。なお、ビット線５とデータ線１７を接続するトランスファーゲート１９は、ここでは制御信号φ_ｔ１によって制御される。その他の構成要素は図１と同様なので詳しい説明は省略する。
【００３６】
前述の第１の実施の形態では、全てのメモリセルにおいて、メモリセル用の強誘電体キャパシタ１のデータがアクセス用トランジスタ２を介してビット線５に読み出されるように構成されていたが、この第２の実施の形態では、ビット線５と対をなすビット線７にも強誘電体キャパシタ２１からアクセス用トランジスタ２２を介してデータが読み出されるように構成され、ビット線７にもトランスファーゲート２０を介してデータ線１８が接続されている。図６におけるビット線５にデータが読み出される強誘電体キャパシタ１を第１のメモリセルとし、ビット線７にデータが読み出される強誘電体キャパシタ２１を第２のメモリセルとすると、メモリセルアレイを構成するそれぞれのメモリセル列内に第１のメモリセルと第２のメモリセルとを設けてあれば、第１のメモリセルと第２のメモリセルとの配置に特に制限はない。
【００３７】
この構成では、ワード線３と２３、セルプレート４と２４、トランスファゲート１９と２０について、動作させる側を選択する以外は第１の実施の形態と同じ動作なのでその説明は省略する。また、トランスファゲート１９と２０は異なる信号φ_ｔ１，φ_ｔ２によって制御するため、データを読み出したビット線の側だけデータ線に接続することが可能であるが、２つのトランスファゲート１９と２０を両方ともオンして、２本のビット線５・７をそれぞれデータ線１７・１８に接続しても問題は無い。
【００３８】
この実施の形態によれば、対をなすビット線５・７のそれぞれにアクセス用トランジスタ２・２２を介してメモリセルの強誘電体キャパシタ１・２１を接続し、データを読み出すビット線とリファレンス電位に保つビット線を交互に入れ換えることで、ビット線を有効に活用し、第１の実施の形態に比べ、メモリセルブロック面積を縮小することが可能である。すなわち、第１の実施の形態では、データを読み出すビット線５に対をなすリファレンス電位用のビット線７が一本必要であるが、第２の実施の形態では、データを読み出さない側のビット線をリファレンス電位用として使用することで、リファレンス電位用のみに使用するビット線が無いため、同じビット数のリードに必要なビット線の数は第１の実施の形態の場合の１／２になる。
【００３９】
また、セルプレート４とセルプレート２４は共通化することが可能なので、さらにメモリセルブロックの面積を縮小することができる。
〔第３の実施の形態〕
図７は本発明の第３の実施の形態の半導体記憶装置のメモリセル列の回路図であり、１Ｔｒ−１Ｃ型ＦｅＲＡＭを示す。図７において、４１、４２、・・・・・・、４３は電位供給回路で、その電位は各回路毎に異なっている。４４、４５、・・・・・・、４６はスイッチ素子であり、その他の構成要素は図６と同様なので詳しい説明は省略する。
【００４０】
この実施の形態では、図６の電位供給回路３３に代えて、それぞれ供給する電位の異なる複数の電位供給回路４１，４２，・・・・・・，４３と、各電位供給回路４１，４２，・・・・・・，４３を選択するためのスイッチ素子４４，４５，・・・・・・，４６とを設けている。この構成により、スイッチ素子４４，４５，・・・・・・，４６で電位供給回路４１，４２，・・・・・・，４３のうちの１つを選択することにより、異なるビット線プリチャージ電位を選択することができる。その他の構成および動作は図６に示す第２の実施の形態と同じであり、説明を省略する。
この実施の形態によれば、第２の実施の形態と同様の効果が得られる他、それぞれ異なるビット線プリチャージ電位を供給する電位供給回路４１，４２，・・・・・・，４３をスイッチ素子４４，４５，・・・・・・，４６で選択できるため、Ｐ検時（拡散終了直後のウエハ状態でのデバイス検査時）のメモリセルキャパシタ特性や、デバイス使用時の特性変動にあわせて最適なビット線プリチャージ電位を選択することができ、動作条件を最適化してより安定して動作させることが可能である。
【００４１】
また、第１の実施の形態においても、図１の電位供給回路３３に代えて、複数の電位供給回路４１，４２，・・・・・・，４３とスイッチ素子４４，４５，・・・・・・，４６とを設けることにより、同様の効果を得ることができる。
なお、スイッチ素子４４〜４６に代えて、複数の電位供給回路４１，４２，・・・・・・，４３を選択して切り替え接続可能な切り替え回路を設けてもよい。
【００４２】
【発明の効果】
本発明によれば、ビット線のプリチャージ電位をセルプレートのハイレベルとローレベルとの間の電位とし、メモリセルから対をなす一方のビット線へデータを読み出す際に、他方のビット線に保たれているプリチャージ電位をリファレンス電位として増幅するようにしているため、従来、リファレンス電位を発生させるために必要としていたリファレンスセル用の強誘電体キャパシタを無くし、その設計・製造上の問題を回避することができる。また、プリチャージ電位をリファレンス電位として用い、データが読み出されるビット線の電位がプリチャージ電位より高いか低いかということでデータを判別するため、メモリセル用の強誘電体キャパシタの特性やビット線容量のバラツキの影響は大幅に軽減され、使用中の強誘電体キャパシタ特性の変動に対しても同様である。したがって、広い動作マージンにより安定に動作し、高い信頼性を持ったＦｅＲＡＭを実現できる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態の半導体記憶装置のメモリセル列の回路図。
【図２】第１の実施の形態の半導体記憶装置での第１のデータ読みだし動作のタイミング図。
【図３】第１の実施の形態におけるデータの読み出し動作の原理を説明するための図。
【図４】第１の実施の形態におけるデータの読み出し時の強誘電体キャパシタの状態変化を示す電圧−電荷量特性図。
【図５】第１の実施の形態の半導体記憶装置での第２のデータ読み出し動作のタイミング図。
【図６】本発明の第２の実施の形態の半導体記憶装置のメモリセル列の回路図。
【図７】本発明の第３の実施の形態の半導体記憶装置のメモリセル列の回路図。
【図８】ＦｅＲＡＭおよびＤＲＡＭのメモリセルキャパシタ電圧−電荷量特性（ヒステリシス特性）図。
【図９】従来の半導体記憶装置であるＦｅＲＡＭのデータ読み出し時のメモリセルキャパシタ電圧−電荷量特性（ヒステリシス特性）および強誘電体キャパシタの状態変化を示す図。
【図１０】従来の半導体記憶装置のメモリセル列の回路図。
【図１１】従来の半導体記憶装置でのデータ読み出し動作タイミング図。
【符号の説明】
１，２１ メモリセル用の強誘電体キャパシタ
２，２２ アクセス用トランジスタ
３，２３ ワード線
４，２４ セルプレート
５，７ ビット線
１６ 差動増幅器
１７，１８ データ線
１９，２０ トランスファーゲート
３１，３２ トランスファーゲート
３３，４１，４２，４３ 電位供給回路
４４，４５，４６ スイッチ素子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device using a ferroelectric for a capacitance insulating film of a charge storage capacitor of a memory cell.
[0002]
[Prior art]
A typical semiconductor memory device at present is a dynamic random access memory (DRAM), but recently, a ferroelectric memory device (FeRAM) using a ferroelectric material as an insulating film of a charge storage capacitor of the DRAM memory cell. Has been developed. This memory device can be used as a non-volatile memory due to the characteristic of a ferroelectric material, in which the polarization remains even when an external electric field is removed, while the DRAM is a volatile memory. In addition, existing rewritable nonvolatile memory devices have excellent characteristics such as low power consumption and high rewrite speed. For this reason, interest is increasing as a next-generation main memory device.
[0003]
FIG. 8A is a voltage-charge amount characteristic diagram of the memory cell capacitors of the DRAM and the FeRAM. The horizontal axis represents the voltage V between both electrodes of the capacitor, and the vertical axis represents the charge amount Q stored in the electrodes of the capacitor. . As shown in FIG. 8B, the direction of the voltage and the direction of the polarization are positive in the direction from top to bottom.
The amount of charge Q stored in the capacitor is obtained by the product of the capacitor capacitance C and the voltage V between the capacitor electrodes. In a capacitor of a DRAM memory cell using a paraelectric material as an insulating film (paraelectric capacitor), the capacitance C Is specific to the capacitor and takes a constant value. When the voltage V is 0 volt, the charge amount Q is also 0 coulomb. The characteristic shown by the straight line {circle around (1)} in FIG. 8A is an example. On the other hand, in a capacitor (ferroelectric capacitor) of a FeRAM memory cell using a ferroelectric as an insulating film, the capacitance C changes depending on the value and history of the voltage V, and the charge amount Q when the voltage V is 0 volt. Also changes depending on the history of the voltage V. The characteristic shown by the curve (2) in FIG. 8A is an example.
[0004]
Hereinafter, the voltage-charge amount characteristic of the ferroelectric capacitor represented by the curve (2) in FIG. 8A will be described in detail.
As an initial state, it is assumed that the ferroelectric capacitor is in a state indicated by a point O in the drawing where no electric field is applied and no polarization occurs. As the voltage V between the plates of the capacitor increases, the amount of charge Q generated at the electrodes increases along the path of the curve OA, and changes to the state at point A. At point A, a voltage is applied between the two electrode plates of the capacitor. Due to the voltage, electric charges are generated in the electrode plates and polarization occurs in the ferroelectric material. Next, when the voltage V is reduced to 0, the state of the capacitor changes to the state at the point B following the path of the curve AB. At point B, the voltage V between the two plates of the capacitor is 0, but since the polarization generated at point A remains in the ferroelectric material (residual polarization), charges are generated on the plates by the polarization. ing. Further, when the voltage V is applied in the negative direction, the state of the capacitor changes to the state at the point C following the path of the curve BC. At the point C, a voltage in the opposite direction to that of the point A is applied between the electrode plates, and a charge having a polarity opposite to that of the A is generated in the electrode plate and a polarization in the opposite direction is generated in the ferroelectric material. Further, when the voltage V is returned to 0, the state changes to the point D following the path of the curve CD. At the point D, the polarization generated at the point C remains in the ferroelectric material. A charge having a polarity opposite to that of the point B is generated on the plate. Further, when a positive voltage is applied again, the state changes to the state at the point A by following the path of the curve DA.
[0005]
FIG. 9 shows one method of applying a ferroelectric capacitor having the above characteristics as a semiconductor memory device of FeRAM. FIG. 9A is a voltage-charge amount characteristic diagram of the ferroelectric capacitor similarly to FIG. 8A, but when applied to the memory cells shown in FIGS. It shows a change in the state of the capacitor that occurs when reading out to a line. Here, different data is written in the memory cell of FIG. 9B and the memory cell of FIG. 9C. 9 (b) and 9 (c), 1 is a ferroelectric capacitor for a memory cell, 2 is an access transistor formed of an NMOS transistor, 3 is a word line, 4 is a cell plate, 5 is a bit line, 6 Is the floating capacitance of the bit line 5, and the polarization direction in the ferroelectric capacitor 1 is the same as in FIG. 8B. Hereinafter, the principle of data storage of the FeRAM will be described with reference to FIGS. 9 (a), 9 (b) and 9 (c).
[0006]
Residual polarization occurs when a voltage is applied in the positive direction to the ferroelectric capacitor 1 of the memory cell in FIG. 9B, and the state is represented by a point B in FIG. 9A. Further, remnant polarization occurs when a voltage is applied in the negative direction to the ferroelectric capacitor 1 of the memory cell in FIG. 9C, and the state is represented by a point D in FIG. 9A. .
When reading data from the memory cells shown in FIGS. 9B and 9C, first, the potential BL of the bit line 5 is precharged to the ground level, and then the potential WL of the word line 3 is raised to access the data. Transistor 2 is turned on, and the potential CP of the cell plate 4 is set to V_BCUp to Then, a negative voltage is applied to the ferroelectric capacitor 1 and changes toward the state at the point C in FIG. 9A. However, the voltage applied to the ferroelectric capacitor 1 is V_BCIs determined by dividing the capacitance of the ferroelectric capacitor 1 by the stray capacitance 6 of the bit line 5 and the ferroelectric capacitor 1, so that the state change of the ferroelectric capacitor 1 in the middle up to the point C differs from the description of FIG. Stops. That is, when the state is at the point B in FIG. 9A, the potential changes to the point E on the curve BC, and the potential generated on the bit line 5 at that time is V.₁It is. On the other hand, when it is in the state of the point D, it changes to the point F on the curve DC, and the potential of the bit line 5 at that time becomes V₀It is. The relationship of the bit line potential at this time is V₁> V₀It is. That is, if the state of the ferroelectric capacitor 1 in FIG. 9B is data “1”, the potential of the bit line 5 becomes H (high) level, and the state of the ferroelectric capacitor 1 in FIG. Is data "0", the potential of the bit line 5 becomes L (low) level.
[0007]
As described above, when data is stored in association with the direction of polarization of the ferroelectric capacitor 1 and data is read from the memory cell to the bit line 5, the potential generated on the bit line 5 differs depending on the direction of polarization. It is the data storage principle of FeRAM that discriminates between data "1" and "0" using this fact.
FIG. 10 is a circuit diagram of a memory cell column showing an example of a conventional 1Tr-1C (1-Transistor 1-Capacitance) type semiconductor memory device that stores data using the operation principle of the FeRAM described above. In FIG. 10, 1 is a ferroelectric capacitor for a memory cell, 2 is an access transistor formed of an NMOS transistor for accessing the memory cell, 3 is a word line, 4 is a cell plate, 5 and 7 are bit lines, and 9 is a reference. This is a ferroelectric capacitor for a cell. The area of the ferroelectric capacitor 9 is larger than that of the ferroelectric capacitor 1. Reference numeral 10 denotes an access transistor formed of an NMOS transistor for accessing a reference cell, 11 denotes a reference word line, 12 denotes a reference cell plate, and 13 and 14 denote NMOS transistors for precharging the bit lines 5 and 7 to ground potential. A charging transistor 15 is a control signal φ_bIs a control signal line that supplies Reference numeral 16 denotes a differential amplifier for amplifying the potential difference between the bit lines 5 and 7, and here, a control signal φ_s, And two clocked CMOS inverters whose activation and deactivation can be controlled. Reference numeral 17 denotes a data line, 19 denotes a transfer gate connecting the bit line 5 and the data line 17, and a control signal φ._tThus, their electrical conduction / interruption can be controlled.
[0008]
FIG. 11 is a timing chart of the data read operation of the semiconductor memory device of FIG. In FIG. 11, WL, CP, RWL, RCP, BL, and / BL are the potentials of the word line 3, cell plate 4, reference word line 11, reference cell plate 12, bit line 5, and bit line 7, respectively._s, Φ_bAre the levels of the control signals for the differential amplifier 16 and the precharge transistors 13 and 14, respectively.
[0009]
A data read operation in the conventional semiconductor memory device will be described with reference to FIGS.
In the initial state, all the nodes in FIG. 10 are at the ground potential, and it is assumed that data “0” is written in the ferroelectric capacitor 9 for the reference cell. First, the potentials WL and RWL of the word line 3 and the reference word line 11 are raised to turn on the access transistors 2 and 10, and the potentials CP and RCP of the cell plate 4 and the reference cell plate 12 are raised. Then, a different potential appears on the potential BL of the bit line 5 depending on the direction of spontaneous polarization of the ferroelectric capacitor 1 for a memory cell, and data “1” and data “0” are read out on the potential / BL of the bit line 7. There is a certain potential between the potentials at the time of contact. Next, the control signal φ_sTo activate the differential amplifier 16, and amplify the potential BL of the bit line 5 with reference to the potential / BL of the bit line 7. After the amplification is completed, the control signal φ_tTo turn on the transfer gate 19 and send the potential BL of the bit line 5 to the data line 17. The above is the reading operation in this device.
[0010]
[Problems to be solved by the invention]
In the above-described conventional semiconductor memory device, the potential used as a reference when determining whether the potential read from the memory cell to the bit line 5 is the H (high) level or the L (low) level is set to the reference cell potential. Is generated by writing data "0" to the ferroelectric capacitor 9 and reading it out to the bit line 7, using a capacitor having a larger area than the ferroelectric capacitor 1 for the memory cell. However, a capacitor having a smaller area than the ferroelectric capacitor 1 for the memory cell is used as the ferroelectric capacitor 9 for the reference cell, and data “1” is written into the ferroelectric capacitor 9 and the data is written to the ferroelectric capacitor 9. It may be generated by reading to the bit line 7.
[0011]
However, in any case, it is possible to design the area of the ferroelectric capacitor 9 for the reference cell which just generates an intermediate potential between the H level and the L level, or to use the ferroelectric capacitor for the reference cell having a certain characteristic as designed. It is difficult to manufacture the body capacitor 9 due to the problem of manufacturing variations.
There are also variations in the characteristics and bit line capacitance of the ferroelectric capacitor 1 for a memory cell, and these factors narrow the 1Tr-1C operation margin and realize a 1Tr-1C FeRAM device that operates stably. It is difficult to achieve high yields.
[0012]
In addition, since the characteristics of the ferroelectric capacitors 1 and 9 change due to stress or the like during use of the device, a phenomenon in which the H-level and L-level potentials from the memory cell and the reference potential from the reference cell fluctuate during use. Occurs and the operation margin is narrowed, which is a major problem in reliability.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which is a FeRAM which operates stably with a wide operation margin and does not require a ferroelectric capacitor for a reference cell.
[0013]
[Means for Solving the Problems]
A semiconductor memory device according to claim 1, wherein a memory cell using a ferroelectric capacitor having a capacitance insulating film made of a ferroelectric is used, and data is read from the memory cell.By activating the word lineA first bit line from which data is read, a second bit line paired with the first bit line, and a low-level potential and a high-level potential connected to one electrode of a ferroelectric capacitor of the memory cell A cell plate that suppliesThe precharge potential for optimizing operating conditions isPotential between high level and low level of cell plateA plurality of precharge potentials that can be selected and supplied from different precharge potentials.A potential supply circuit, first and second transfer gates for conducting the potential supply circuit and the first bit line and the second bit line during a precharge period, and cutting off the data read operation; A differential amplifier that amplifies a potential difference between the first bit line and the second bit line by using a precharge potential held on the bit line as a reference potential,After the cell plate activates the word line and before the amplification by the differential amplifier starts,There is both a period in which the cell plate supplies a low-level potential and a period in which the cell plate supplies a high-level potentialDriven asIt is characterized by the following.
[0014]
According to this configuration, the precharge potential of the bit line is set to a potential between the high level and the low level of the cell plate, and when data is read from the memory cell to the first bit line, the precharge potential is held on the second bit line. Since the dropped precharge potential is amplified as the reference potential, the ferroelectric capacitor for the reference cell, which was conventionally required to generate the reference potential, is eliminated, thereby avoiding design and manufacturing problems. can do. In addition, since the precharge potential is used as a reference potential and data is determined based on whether the potential of a bit line from which data is read is higher or lower than the precharge potential, the characteristics of a ferroelectric capacitor for a memory cell and the bit line The effect of the variation in capacitance is greatly reduced, and the same is applied to the fluctuation of the characteristics of the ferroelectric capacitor during use. Therefore, an FeRAM that operates stably with a wide operation margin and has high reliability can be realized.
Furthermore, since a potential supply circuit for supplying different precharge potentials can be selected, the ferroelectric capacitor characteristics for memory cells at the time of P detection (during device inspection in a wafer state immediately after the end of diffusion) and the characteristics at the time of device use An optimal precharge potential can be selected according to the fluctuation, and the operation conditions can be optimized to operate more stably.
[0015]
A semiconductor memory device according to claim 2, wherein first and second memory cells using a ferroelectric capacitor having a capacitive insulating film made of a ferroelectric, and when reading data from the first memory cell.By activating the first word lineA first bit line from which data is read, and a pair with the first bit line, when reading data from the second memory cellBy activating the second word lineA second bit line from which data is read, a cell plate connected to one electrode of a ferroelectric capacitor of the memory cell, and supplying a low-level potential and a high-level potential;The precharge potential for optimizing operating conditions isPotential between high level and low level of cell plateA plurality of precharge potentials that can be selected and supplied from different precharge potentials.A potential supply circuit, first and second transfer gates that conduct the potential supply circuit and the first bit line and the second bit line during a precharge period, and shut off the data read operation; The potential difference between the first bit line and the second bit line is amplified by using the precharge potential held on the second bit line as a reference potential at the time of reading data, and the first potential is read at the time of reading data from the second memory cell. And a differential amplifier for amplifying a potential difference between the first bit line and the second bit line using the precharge potential held on the bit line as a reference potential.After the cell plate activates the first or second word line and before the amplification by the differential amplifier starts,There is both a period in which the cell plate supplies a low-level potential and a period in which the cell plate supplies a high-level potentialDriven asIt is characterized by the following.
[0016]
According to this configuration, in addition to the same effect as the first aspect, the data of the first memory cell is read out to the first bit line, and the data of the second memory cell is read out to the second bit line. Thus, by alternately replacing the bit line for reading data and the bit line for maintaining the reference potential, it is possible to effectively use the bit line and reduce the memory cell block area.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a circuit diagram of a memory cell column of a semiconductor memory device according to a first embodiment of the present invention, and shows a 1Tr-1C FeRAM. In FIG. 1, 1 is a ferroelectric capacitor for a memory cell, 2 is an access transistor formed of an NMOS transistor for accessing the memory cell, 3 is a word line, 4 is a cell plate, 5 and 7 are bit lines (5 is a 1 is a bit line, 7 is a second bit line), 16 is a differential amplifier for amplifying the potential difference between the bit lines 5 and 7, and here a control signal φ_s, And two clocked CMOS inverters whose activation and deactivation can be controlled. Reference numeral 17 denotes a data line, 19 denotes a transfer gate connecting the bit line 5 and the data line 17, and a control signal φ._tThus, their electrical conduction / interruption can be controlled. Transfer gates 31 and 32 connect the bit lines 5 and 7 and the potential supply circuit 33, respectively._mThus, their electrical conduction / interruption can be controlled. The potential supply circuit 33 can supply an arbitrary potential.
[0019]
The semiconductor memory device of this embodiment eliminates the ferroelectric capacitor 9 for the reference cell and its access transistor 10 in the conventional example shown in FIG. 10, and applies a precharge potential to the bit lines 5 and 7 forming a pair. There are provided a potential supply circuit 33 for supplying, and transfer gates 31 and 32 for conducting / cutting off the potential supply circuit 33 and the respective bit lines 5 and 7. The potential supply circuit 33 supplies a potential between the L level and the H level of the cell plate 4 to the bit lines 5 and 7 as a precharge potential.
[0020]
FIG. 2 is a timing chart of a first data read operation in the semiconductor memory device of FIG. 1, and WL, CP, BL, and / BL indicate a word line 3, a cell plate 4, a bit line 5, and a bit line, respectively. 7 and φ_s, Φ_mAre the levels of the control signals for the differential amplifier 16 and the transfer gates 31 and 32, respectively. A data read operation in this device will be described with reference to FIGS. Here, the description will be made with the L level of the cell plate 4 as the ground and the H level as the power supply voltage.
[0021]
As an initial state, the transfer gates 31 and 32 in FIG. 1 are in an ON state, and the bit lines 5 and 7 are precharged by the potential supply circuit 33 to a potential intermediate between the ground level and the power supply voltage level. Are all at the ground potential.
First, after the precharge is completed, the control signal φ_mThen, the transfer gates 31 and 32 are turned off, the potential WL of the word line 3 is raised, and the access transistor 2 is turned on. Then, charge moves from the bit line 5 to the ferroelectric capacitor 1 in accordance with the data written in the ferroelectric capacitor 1, and the potential BL of the bit line 5 decreases.
[0022]
Next, when the potential CP of the cell plate 4 is increased, charge moves from the ferroelectric capacitor 1 to the bit line 5 in accordance with the data written in the ferroelectric capacitor 1, and the potential BL of the bit line 5 is increased. Rises. Eventually, the potential BL of the bit line 5 becomes higher than the bit line precharge potential when data “1” is written in the ferroelectric capacitor 1, and when the data “0” is written, It becomes lower than the bit line precharge potential. The control signal φ_sTo enable the differential amplifier 16 to amplify the precharge potential (/ BL) held on the bit line 7 as a reference potential. After the amplification is completed, the control signal φ_tTo enable the transfer gate 19 and send the potential BL of the bit line 5 to the data line 17 to complete the read operation.
[0023]
Further, the principle of the data read operation will be described with reference to FIGS. FIG. 3 is a diagram for explaining the principle of the data read operation. 3A, 3B, and 3C, reference numeral 6 denotes a stray capacitance of the bit line 5, and the directions of voltages of the ferroelectric capacitor 1 and the bit line stray capacitance 6 are the same as those in FIG. 8B. The direction from top to bottom is positive. FIG. 4 is a voltage-charge amount characteristic diagram of the ferroelectric capacitor 1 for a memory cell. The horizontal axis represents the voltage V between both electrodes of the capacitor, and the vertical axis represents the charge amount Q stored in the electrode of the capacitor. FIG. 4 shows a state change of the ferroelectric capacitor 1 which occurs when the read operation shown in FIGS. 3A, 3B, and 3C is performed.
[0024]
FIG. 3A shows a state immediately before data is read out._B0Is charged in the electrode plate by the voltage._B0Has occurred. The ferroelectric capacitor 1 is in the state shown by the point B in FIG. 4 and the voltage V between the plates is 0, but the charge Q_S0Has occurred. The value of the bit line stray capacitance 6 is C_B, The capacitance value of the ferroelectric capacitor 1 is C_SAnd put, C_BTakes a constant value, but C_SHas different values depending on the position on the curve showing the voltage-charge amount characteristic in FIG. One electrode plate of the bit line stray capacitance 6 is connected to the ground, and the other electrode plate is in a high impedance state. One electrode plate of the ferroelectric capacitor 1 is connected to the cell plate 4 kept at the ground level, and the other electrode plate is in a high impedance state.
[0025]
From this state, the potential of the word line 3 is increased, the access transistor 2 is turned on, and the electrode plate in the high impedance state of the bit line floating capacitor 6 and the ferroelectric capacitor 1 as shown in FIG. When electrically connected, charges move from the bit line floating capacitance 6 to the ferroelectric capacitor 1 until the voltage of the two capacitors (1, 6) becomes equal to the inter-electrode voltage, and finally the bit line floating capacitance 6 Voltage V_B1And charge Q_B1Is applied to the ferroelectric capacitor 1 with the voltage V_S1And charge Q_S1Occurs and stabilizes. Further, the state of the ferroelectric capacitor 1 changes to the state at the point G following the curve BG in FIG. The bit line potential V in this stable state_B1And ask for
From the law of conservation of charge,
Q_B0+ Q_S0= Q_B1+ Q_S1    (1)
Also, since the voltage of both capacitors is equal,
V_B1= V_S1    (2)
Since the amount of charge stored in the capacitor is the product of the capacitance value and the voltage between the plates, the amount of charge in the bit line stray capacitance 6 is
Q_B0= C_B・ V_B0
Q_B1= C_B・ V_B1
It becomes.
[0026]
The state change of the ferroelectric capacitor 1 from the point B to the point G in FIG._S1, The charge amount Q of the ferroelectric capacitor 1_S1Is
Q_S1= C_S1・ V_S1+ Q_S0    (3)
Substituting these into equation (1) gives
C_B・ V_B0+ Q_S0= C_B・ V_B1+ C_S1・ V_S1+ Q_S0
Furthermore, rearranging by substituting equation (2),
C_B・ V_B0= (C_B+ C_S1) ・ V_B1
Therefore, the bit line potential V_B1Is
V_B1= ｛C_B/ (C_B+ C_S1)｝ ・ V_B0    (4)
It becomes.
[0027]
Next, as shown in FIG. 3C, the potential CP of the cell plate 4 is changed to the power supply potential V._D3B, charges move from the ferroelectric capacitor 1 to the bit line stray capacitance 6 in a manner opposite to the case of FIG._DV divided by the capacitance of the bit line stray capacitance 6 and the capacitance of the ferroelectric capacitor 1_B2And V_S2Occurs and stabilizes. At this time, the charge Q is stored in the bit line stray capacitance 6 and the ferroelectric capacitor 1, respectively._B2And Q_S2Has occurred. Further, the state of the ferroelectric capacitor 1 changes to the state at the point H following the curve GH in FIG. The bit line potential V in this stable state_B2And ask for
From the law of conservation of charge,
Q_B0+ Q_S0= Q_B2+ Q_S2    (5)
The sum of the voltages of the bit line floating capacitor 6 and the ferroelectric capacitor 1 is equal to the voltage V._DSo
V_B2-V_S2= V_D      (6)
The charge amount of the bit line stray capacitance 6 is
Q_B0= C_B・ V_B0
Q_B2= C_B・ V_B2
It becomes.
[0028]
The state change of the ferroelectric capacitor 1 from the point G to the point H in FIG. 4 is approximated by a straight line connecting two points, and its slope is expressed by C_S2, Q contact piece to Q₂Then,
The approximate straight line is
Q = C_S2・ V + Q₂
Since this approximation straight line passes through the point G, the relationship between the charge amount Q and the voltage V at the point G is obtained from Expression (3) and substituted.
C_S1・ V_S1+ Q_S0= C_S2・ V_S1+ Q₂
When deformed,
(C_S1-C_S2) ・ V_S1+ Q_S0= Q₂
Therefore, the amount of charge of the ferroelectric capacitor 1 is
Q_S2= C_S2・ V_S2+ (C_S1-C_S2) ・ V_S1+ Q_S0    (7)
Substituting these into equation (5) gives
C_B・ V_B0+ Q_S0= C_B・ V_B2+ C_S2・ V_S2+ (C_S1-C_S2) ・ V_S1+ Q_S0
Substituting equation (6) and rearranging,
C_B・ V_B0= (C_B+ C_S2) ・ V_B2-C_S2・ V_D+ (C_S1-C_S2) ・ V_S1
Further, from equations (2) and (4), V_S1Substituting the value of

It becomes.
[0029]
As shown in equation (8), the bit line potential V in FIG._B2Is the precharge potential V_B0, Cell plate potential V_D, Bit line stray capacitance C_B, The approximate capacitance C of the ferroelectric capacitor 1_S1And C_S2, But generally C_S1Is C_S2Precharge potential V when smaller_B0It tends to be larger. When the ferroelectric capacitor 1 is at the point B in FIG._S1<C_S2So, C_BAnd V_B0And V_DIs adjusted, the bit line potential V_B2Is the precharge potential V_B0Higher than. In short, when electric charges move from the bit line stray capacitance 6 to the ferroelectric capacitor 1, a positive voltage is applied to the ferroelectric capacitor 1 and the change in polarization is small, so that the amount of movement is small. When electric charges move from the dielectric capacitor 1 to the bit line floating capacitance 6, a negative voltage is applied to the ferroelectric capacitor 1 and the amount of movement increases because of a large change in polarization. 5 has been transferred, and the potential of the bit line 5 rises.
[0030]
Also, when the ferroelectric capacitor 1 before reading data is in the state of the point D in FIG._B2Is obtained in the same manner, in which case C_S1> C_S2Therefore, the bit line potential V_B2Is the precharge potential V_B0Lower than That is, when electric charges move from the bit line stray capacitance 6 to the ferroelectric capacitor 1, a positive voltage is applied to the ferroelectric capacitor 1, and a large change in polarization causes a large amount of movement. When the charge moves from the capacitor to the bit line floating capacitor 6, a negative voltage is applied to the ferroelectric capacitor 1 and the amount of movement is small due to a small change in polarization. As a result, the charge is transferred to the ferroelectric capacitor 1. Has moved, and the potential of the bit line 5 drops.
[0031]
According to the principle as described above, the potential of the bit line 5 after data reading is higher or lower than the precharge potential depending on the type of data, so that it is possible to determine data using the precharge potential as a reference. is there.
According to this embodiment, when the precharge potential of the bit lines 5 and 7 is set to a potential between the H level and the L level of the cell plate 4 and data is read from the ferroelectric capacitor 1 to the bit line 5, Since the precharge potential held on the bit line 7 is amplified as the reference potential, the ferroelectric capacitor for the reference cell, which was conventionally required for generating the reference potential, is eliminated, and its design and manufacture are eliminated. The above problems can be avoided. In addition, since the precharge potential is used as a reference potential and data is determined based on whether the potential of the bit line 5 from which data is read is higher or lower than the precharge potential, the characteristics and bit of the ferroelectric capacitor for a memory cell are determined. The effect of variations in line capacitance is greatly reduced, as is the case with variations in ferroelectric capacitor characteristics during use. Therefore, a 1Tr-1C type FeRAM that operates stably with a wide operation margin and has high reliability can be realized.
[0032]
In this embodiment, the L level of the cell plate 4 has been described as ground and the H level has been described as the power supply voltage. However, the operation can be performed with the L level of the cell plate 4 being equal to or lower than the ground level. The precharge potentials of the lines 5 and 7 can be set to the ground level, and the potential supply circuit 33 can be simplified.
[0033]
When the level of the word line 3 is raised and when the potential of the cell plate 4 is raised, charge transfer occurs between the ferroelectric capacitor 1 and the bit line 5, but the charge transfer stops. Before stabilization, it is possible to raise the potential of the cell plate 4 and to activate the differential amplifier 16, so that the access time can be shortened.
[0034]
FIG. 5 is a timing chart of the second data reading operation in the semiconductor memory device of FIG. In the second data reading operation, the potential CP of the cell plate 4 is raised to the H level and then returned to the L level once and raised to the H level again with respect to the first data reading operation timing of FIG. Other than the above, the detailed description is omitted, but the operation of activating the differential amplifier 16 after repeating the raising and lowering of the potential CP of the cell plate 4 twice or more as described above is also possible.
[0035]
[Second embodiment]
FIG. 6 is a circuit diagram of a memory cell column of the semiconductor memory device according to the second embodiment of the present invention, and shows a 1Tr-1C type FeRAM. In FIG. 6, reference numeral 21 denotes a ferroelectric capacitor for a memory cell, 22 denotes an access transistor including an NMOS transistor for accessing the memory cell, 23 denotes a word line, 24 denotes a cell plate, 18 denotes a data line, and 20 denotes a bit line 7. Transfer gate connecting the data line 18 to the control signal φ_t2Thus, their electrical conduction / interruption can be controlled. Note that the transfer gate 19 connecting the bit line 5 and the data line 17 is controlled by the control signal φ here._t1Is controlled by Other components are the same as those in FIG.
[0036]
In the first embodiment described above, in all the memory cells, the data of the ferroelectric capacitor 1 for the memory cell is read out to the bit line 5 via the access transistor 2. In the second embodiment, data is read from the ferroelectric capacitor 21 via the access transistor 22 to the bit line 7 paired with the bit line 5, and the transfer gate 20 is connected to the bit line 7. Is connected to the data line 18 via the. If the ferroelectric capacitor 1 from which data is read to the bit line 5 in FIG. 6 is a first memory cell and the ferroelectric capacitor 21 from which data is read to the bit line 7 is a second memory cell, a memory cell array is formed. There is no particular limitation on the arrangement of the first and second memory cells as long as the first and second memory cells are provided in each memory cell column.
[0037]
In this configuration, the operation of the word lines 3 and 23, the cell plates 4 and 24, and the transfer gates 19 and 20 is the same as that of the first embodiment except that the operation side is selected, and therefore the description thereof is omitted. Further, the transfer gates 19 and 20 generate different signals φ._t1, Φ_t2Therefore, it is possible to connect only the bit line from which data is read to the data line. However, both the transfer gates 19 and 20 are turned on, and the two bit lines 5 and 7 are respectively connected. There is no problem even if connected to the data lines 17 and 18.
[0038]
According to this embodiment, the ferroelectric capacitors 1 and 21 of the memory cell are connected to the paired bit lines 5 and 7 via the access transistors 2 and 22, respectively. By alternately replacing the bit lines, the bit lines can be effectively used, and the memory cell block area can be reduced as compared with the first embodiment. That is, in the first embodiment, one bit line 7 for the reference potential, which is paired with the bit line 5 from which data is read, is required. In the second embodiment, the bit line on which data is not read is used. By using the lines for the reference potential, since there is no bit line used only for the reference potential, the number of bit lines required to read the same number of bits is １ ／ of that in the first embodiment. Become.
[0039]
Further, since the cell plate 4 and the cell plate 24 can be shared, the area of the memory cell block can be further reduced.
[Third Embodiment]
FIG. 7 is a circuit diagram of a memory cell column of a semiconductor memory device according to a third embodiment of the present invention, and shows a 1Tr-1C type FeRAM. In FIG. 7, reference numerals 41, 42,..., 43 denote potential supply circuits, the potentials of which are different for each circuit. , And 46 are switch elements, and other components are the same as those in FIG.
[0040]
In this embodiment, instead of the potential supply circuit 33 of FIG. 6, a plurality of potential supply circuits 41, 42,... , 43 for selecting the switch elements 44, 45, ..., 46 are provided. With this configuration, one of the potential supply circuits 41, 42,..., 43 is selected by the switch elements 44, 45,. The potential can be selected. Other configurations and operations are the same as those of the second embodiment shown in FIG. 6, and a description thereof will be omitted.
According to this embodiment, the same effects as those of the second embodiment can be obtained, and the potential supply circuits 41, 42,... Since elements 44, 45,..., And 46 can be selected, the memory cell capacitor characteristics at the time of P detection (during device inspection in the wafer state immediately after the end of diffusion) and characteristic fluctuations at the time of device use are adjusted. An optimal bit line precharge potential can be selected, and operating conditions can be optimized for more stable operation.
[0041]
Also, in the first embodiment, a plurality of potential supply circuits 41, 42,..., 43 and switch elements 44, 45,. The same effect can be obtained by providing.
Note that, instead of the switch elements 44 to 46, a switching circuit capable of selecting and connecting a plurality of potential supply circuits 41, 42,..., 43 may be provided.
[0042]
【The invention's effect】
According to the present invention, the precharge potential of the bit line is set to a potential between the high level and the low level of the cell plate, and when data is read from the memory cell to one of the paired bit lines, the data is applied to the other bit line. Since the held precharge potential is amplified as the reference potential, the ferroelectric capacitor for the reference cell, which was conventionally required to generate the reference potential, is eliminated, and the design and manufacturing problems are eliminated. Can be avoided. In addition, since the precharge potential is used as a reference potential and data is determined based on whether the potential of a bit line from which data is read is higher or lower than the precharge potential, the characteristics of a ferroelectric capacitor for a memory cell and the bit line The effect of the variation in capacitance is greatly reduced, and the same is applied to the fluctuation of the characteristics of the ferroelectric capacitor during use. Therefore, an FeRAM that operates stably with a wide operation margin and has high reliability can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a memory cell column of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a timing chart of a first data reading operation in the semiconductor memory device according to the first embodiment;
FIG. 3 is a diagram illustrating the principle of a data read operation according to the first embodiment;
FIG. 4 is a voltage-charge amount characteristic diagram showing a state change of a ferroelectric capacitor at the time of reading data in the first embodiment.
FIG. 5 is a timing chart of a second data read operation in the semiconductor memory device according to the first embodiment;
FIG. 6 is a circuit diagram of a memory cell column of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 7 is a circuit diagram of a memory cell column of a semiconductor memory device according to a third embodiment of the present invention.
FIG. 8 is a diagram showing a voltage-charge amount characteristic (hysteresis characteristic) of a memory cell capacitor of a FeRAM and a DRAM.
FIG. 9 is a diagram showing a memory cell capacitor voltage-charge amount characteristic (hysteresis characteristic) and a state change of a ferroelectric capacitor when data is read from an FeRAM which is a conventional semiconductor memory device.
FIG. 10 is a circuit diagram of a memory cell column of a conventional semiconductor memory device.
FIG. 11 is a timing chart of a data read operation in a conventional semiconductor memory device.
[Explanation of symbols]
Ferroelectric capacitors for 1,21 memory cells
2,22 access transistor
3,23 word lines
4,24 cell plate
5, 7 bit line
16 Differential amplifier
17, 18 Data line
19,20 Transfer gate
31, 32 transfer gate
33, 41, 42, 43 Potential supply circuit
44, 45, 46 switch element

Claims (2)

A memory cell using a ferroelectric capacitor having a capacitive insulating film made of a ferroelectric,
A first bit line from which data is read by activating a word line when reading data from the memory cell;
A second bit line paired with the first bit line;
A cell plate connected to one electrode of the ferroelectric capacitor of the memory cell and supplying a low-level potential and a high-level potential;
A plurality of potential supplies configured to be able to select and supply a precharge potential for optimizing an operation condition from a plurality of different precharge potentials between a high level and a low level of the cell plate. Circuit and
First and second transfer gates that conduct the potential supply circuit and the first bit line and the second bit line during a precharge period and cut off at the time of data reading;
A differential amplifier for amplifying a potential difference between the first bit line and the second bit line by using a precharge potential held on the second bit line as a reference potential during data reading;
At the time of data reading, a period in which the cell plate supplies a low-level potential and a period in which the cell plate supplies a high-level potential after the activation of the word line until the start of amplification by the differential amplifier. And a semiconductor memory device driven so that both exist. First and second memory cells using a ferroelectric capacitor having a capacitor insulating film made of a ferroelectric;
A first bit line from which data is read by activating a first word line when reading data from the first memory cell;
A second bit line paired with the first bit line and reading data by activating a second word line when reading data from the second memory cell;
A cell plate connected to one electrode of the ferroelectric capacitor of the memory cell and supplying a low-level potential and a high-level potential;
A plurality of potential supplies configured to be able to select and supply a precharge potential for optimizing an operation condition from a plurality of different precharge potentials between a high level and a low level of the cell plate. Circuit and
First and second transfer gates that conduct the potential supply circuit and the first bit line and the second bit line during a precharge period and cut off at the time of data reading;
Amplifying a potential difference between the first bit line and the second bit line by using a precharge potential held on the second bit line as a reference potential when reading data from the first memory cell; A differential amplifier for amplifying a potential difference between the first bit line and the second bit line by using a precharge potential held on the first bit line as a reference potential when reading data from a second memory cell With
At the time of data reading, after the cell plate activates the first or second word line and before the amplification by the differential amplifier starts, a period during which the cell plate supplies a low level potential and a high level the semiconductor memory device, wherein a and duration for supplying a potential is driven to both present the.

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