JP2000285682A - Semiconductor memory and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the reduction of read-out signals and to secure sufficient read-out signals by applying first and second potentials to both ends of a first ferroelectric capacitor, raising the plate line potential from a second potential to a third potential being higher, and reading out electric charges of the first ferroelectric capacitor to a bit line while keeping the bit line floating. SOLUTION: In the first operation of a cell array, an equalizing signal/EQL is made high as it is, a word line WLO is raised, a cell transistor is turned on, a potential of a plate line PLO is raised by bias voltage Voff. Thereby, voltage of bias voltage Voff is applied to both ends of a ferroelectric capacitor, as a bit line is fixed to Vss, the electric charges are made to flow in a Vss line and disappeared. In the second operation, an equalizing signal EQL is made low, a bit line is made to be floated in a state of Vss, and a PLO potential is raised from bias voltage Voff to Vdd.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile ferroelectric memory.
It is possible to solve the problem that a read signal to a bit line is reduced due to a change or deterioration of a ferroelectric film such as Imprint and Depolarization, and to provide a sufficient read signal amount and a highly reliable semiconductor memory device.

[0002]

2. Description of the Related Art Today, semiconductor memories are mainly used for personal computers, home electric appliances,
It is used everywhere, such as mobile phones. The types of semiconductor memory include volatile DRAM (Dynamic RAM),
SRAM (StaticRAM), nonvolatile MROM (Mask
ROM), Flash E2PROM (Electricaly Erasable)
Promgramable ROM) is on the market. In particular, although a DRAM is a volatile memory, it is superior in terms of low cost (cell area is 1/4 as compared with SRAM) and high speed (compared to FlashE2PROM).
It currently occupies most of the market. A rewritable and non-volatile Flash E2PROM is non-volatile and can be turned off. However, the number of times of rewriting (the number of times of W / E) is only about 10.sup.6, the writing time is about microseconds, and High voltage (12V ~ 2
2V) must be applied.
The market is not as open as AM.

On the other hand, ferroelectric capacitors (Ferr
Non-volatile memory FRA using Oelectric Capacitor)
M (Ferroelectric RAM) has been non-volatile since it was proposed in 1980, has a rewrite frequency of 10 12 or more, and has a read / write time of about 3 to 5 times the DRAM.
Since it has advantages such as V operation, it may replace the entire memory market, and each manufacturer is developing it.

[0004] The cells of FRAM are SRAM + at the beginning of development.
From the Shadow Memory configuration, 2transistor + 2Capacitor
As with the development of the configuration and the DRAM, the cell size has been reduced due to simplification and miniaturization of the cell configuration with the times.

FIG. 22 shows one transi of the FRAM of the conventional example 1.
The memory cell of stor + 1Capacitor configuration and its operation method are shown. It has the same memory cell configuration as DRAM, but differs in
(1) A DRAM uses a paraelectric material as a capacitor, while a FRAM uses a ferroelectric material. (2) A charge stored in a capacitor when a memory cell transistor is turned on in a DRAM. Is read out to the bit line, but in the FRAM, only turning on the memory cell transistor does not read out the memory cell data.
Keep the / EQL high, precharge the bit line to Vss, set the / EQL low and float during Active, turn on the memory cell transistor, and set the Plate line to Vss.
, And the polarization information is read out to the bit line only when the potential of Vdd is applied to both ends of the ferroelectric capacitor. For example, "1" Data is read when a large charge is read out to the bit line due to polarization inversion, and "0" Data is read out when a small charge is read out to the bit line without polarization.
It is so. The signal is amplified by a sense amplifier to read data.

The present inventor has proposed a new memory cell configuration for realizing high-speed operation while reducing the memory cell size with respect to the FRAM of the prior art 1 as disclosed in Japanese Patent Application Laid-Open No. 10-2.
No. 55483 and Japanese Patent Application No. 9-346404 (not disclosed).

FIG. 23 shows a prior application of Japanese Patent Application No. 9-34640.
No. 4 shows a memory cell configuration of Conventional Example 2 and an operation example thereof. In FIG. 23, one memory cell is formed by connecting one cell transistor and one ferroelectric capacitor in parallel, and the memory cell is connected in series to form a block. It is configured to connect to the bit line and connect the other end to the plate line. By providing two block selection signals (BS0, BS1) and two plate lines (PL (/ BL), PL (BL)), the bit line pair (/ B
L, BL) and read the other cell
A folded bit line configuration for a rence (reference) bit line has been realized.

In operation, all word lines (WL0 to WL7) are set to a high level during Standby, and all the cell transistors are turned on to electrically short both ends of the ferroelectric capacitor, thereby storing cell data. Hold. Stand
At the time of by, / EQL is set to High and the bit line is Prec to Vss.
After the harge is set to Floating by setting / EQL to Low during Active, or before or after it, only the selected word line (WL2) is set to Low level.
After the bit line becomes Floating due to Low, the block select transistor BS0 is set to High and the Plate potential is changed from Vss.
Raise to Vdd. As a result, the Plate potential is applied to one end of the ferroelectric capacitor of the selected cell, the potential of the floating bit line is applied to the other end of the ferroelectric capacitor, and the polarization information is read out to the bit line. It works. On the other hand, the ferroelectric capacitors of the non-selected cells in the selected block are short-circuited because the word line is high, and the polarization information is held. Therefore, for example, when a large charge is read out to the bit line after polarization inversion, “1” Dat
a, If a small electric charge is read out to the bit line without polarization, it is called "0" Data. The prior invention has a different circuit configuration and characteristics from the conventional FRAM, but the data of the data from the ferroelectric capacitor is different. The principle of reading itself is the conventional FR
It turns out that it is the same as AM. That signal is amplified by a sense amplifier to read data.

As described above, there are mainly two types of ferroelectric memories using a ferroelectric capacitor, Conventional Examples 1 and 2, and in both cases, the deterioration of the characteristics of the ferroelectric capacitor film causes the bit from the memory cell to change. There is a problem that the read signal to the line decreases. Deterioration of the characteristics, that is, the problem of reliability, 1) Depolarization (also referred to as Relaxation) in which the amount of remanent polarization at 0 V bias decreases with time, 2) The hysteresis curve of the ferroelectric film has a ± voltage direction. There are Imprint which shifts, and 3) Fatigue where the amount of polarization decreases when Read / Write is repeated.

FIG. 24 shows typical Imprint characteristics. The dotted hysteresis curve in FIG. 24A is a normal curve without Imprint. The thick hysteresis curve is "0" Data written on the ferroelectric capacitor, and the hysteresis curve after being left for a long time at the position of □. The hysteresis curve shifts in the positive (right) direction. Shows the curve in which. Similarly, the dotted hysteresis curve in FIG. 24B is a normal curve without Imprint. The thick hysteresis curve is "1" Data written on the ferroelectric capacitor, the hysteresis curve after leaving it for a long time at the position of □, and the hysteresis curve shifts in the negative (left) direction. Shows the curve in which.

Next, how the read signal changes in the two cases will be described. For example, the potential read to the bit line of “1” Data is drawn from the 0 V bias position of “1” Data by the amplitude potential of the bit line to the minus (left) in parallel with the X axis, and from this point, A load curve of the slope of the value of the load capacitance Cb of the bit line is written, and a value that intersects with the hysteresis curve can be said to be a read potential. This is because, in actual operation, when the bit line is at Vss and the Plate line is raised from Vss to Vdd, the cell node potential of Vdd drops out the charge Q,
This corresponds to the fact that the bit line potential increases with the charge Q. In terms of the hysteresis curve, the capacitor generates a charge Q from the position of 0 V on the hysteresis curve, and the potential goes in the negative direction.
The point where the voltage rises from -Vdd and intersects is the actual "1" Data bit line potential when -Vdd is viewed as the actual operation Vss potential.

Similarly, the potential read to the "0" Data bit line is drawn from the position of the 0 V bias of "0" Data by minus (left) parallel to the X axis by the amplitude potential of the bit line. From this point, a load curve having a gradient of the value of the load capacitance Cb of the bit line is written, and the value that intersects with the hysteresis curve can be said to be a read potential. Imprint of dotted line in Fig. 24 (a), (b)
The read potential of “1” and “0” Data when no occurrence occurs is represented by 〇, and the difference between the two 〇 can be said to be the difference between “1” data and “0” data. In the 2T2C configuration, this becomes the read potential, and in the 1T1C configuration, between the two の 間 に potentials.
Reference potential is brought. Similarly Imprin
Similarly, when "t" occurs, two "blackened" correspond to "1" Data and "0" Data only by shifting the locus of the hysteresis curve.

[0013] After leaving "0" Data as shown in FIG.
In the case of Imprint, the hysteresis curve only shifts to the right, so when looking at "1" Data readout, the trajectory from the 0 V position of the hysteresis curve to the operating point "black out" has more polarization reversal and is steeper. After passing through the slope, a large charge is released with a slight lead of the voltage, and as a result, "1" Dat
The read potential of a rises. Looking at the "0" Data readout, the trajectory from the position of 0 V on the hysteresis curve to the operating point "black out" passes through a gentle slope with larger polarization saturation, and a small charge is released with the leading voltage of the larger trajectory As a result, the read potential of "0" Data drops. As a result, the read signal is increased by Imprint.

On the other hand, as shown in FIG.
In the case of Imprint after leaving 1 "Data, the hysteresis curve is shifted to the left.
From the position of 0 V on the hysteresis curve, the operating point "black circle"
The trajectory to first passes through a region where polarization reversal is unlikely to occur,
Only when a large negative voltage is applied, the charges due to the polarization inversion are finally released, and as a result, the read potential of “1” Data drops. Looking at the "0" Data readout, the locus from the 0V position of the hysteresis curve to the operating point "black out" first enters the polarization saturation region from the domain inversion region, so a large charge is released with a small voltage As a result, the read potential of "1" Data rises. As a result, the number of read signals is significantly reduced by Imprint, causing malfunctions, a reduction in operation margin, and a reduction in reliability.

[0015]

As described above, the conventional F
In the RAM, when Imprint of the ferroelectric capacitor occurs, the read potential of "1" Data decreases and the read potential of "0" Data increases, resulting in a 1T1C configuration and 2T
In both of the 2C configurations, there is a problem in that the read potential from the ferroelectric capacitor to the bit line decreases, causing malfunction, a reduction in an operation margin, a deterioration in reliability, and the like.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a read signal even when an imprint occurs when data is written and left in a ferroelectric capacitor. It is another object of the present invention to provide a more stable and highly reliable ferroelectric memory by suppressing the above and securing a sufficient read signal.

[0017]

Means for Solving the Problems The first invention of the present application is the first invention.
, And a first ferroelectric capacitor having one end connected to the source electrode and the other end connected to the drain electrode, and a plurality of memory cells are connected in series to form a memory cell unit. One end of the memory cell unit is connected to a bit line via a second transistor, and the other end is connected to a plate line to form a memory cell block. In a method for driving a semiconductor memory device forming a cell array, a plate line potential is raised to a second potential while the bit line is fixed at a first potential, and a first potential is applied to both ends of the first ferroelectric capacitor. A first operation of applying the potential of the plate line and a second potential, and, following the first operation, while the bit line is in a floating state, the plate line potential is changed to the second potential. Raised to a higher third voltage is a driving method of a semiconductor memory device and performing a second operation for reading the charges of the first ferroelectric capacitor to the bit line.

According to a second aspect of the present invention, a memory cell comprises a first transistor and a first ferroelectric capacitor having one end connected to the source electrode and the other end connected to the drain electrode. A plurality of cells are connected in series to form a memory cell unit. One end of the memory cell unit is connected to a bit line via a second transistor, and the other end is connected to a plate line to form a memory cell block. In a semiconductor memory device in which a plurality of memory cell blocks are arranged to form a memory cell array, a first potential, a second potential higher than the first potential, or a second potential higher than the second potential is applied to the plate line. 3. A semiconductor memory device comprising a plate line potential conversion circuit for sequentially applying the potentials of No. 3 and 3.

According to a third aspect of the present invention, a plurality of memory cells each including a first transistor, a first ferroelectric capacitor, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines are provided. In the method for driving a semiconductor memory device having a memory cell array to be
A first operation of raising the plate line potential to a second potential while fixing the potential to the second potential, and applying a first potential and a second potential to both ends of the first ferroelectric capacitor; Subsequent to the operation 1, the plate line potential is raised from the second potential to a third potential higher while the bit line is in a floating state, and the charge of the first ferroelectric capacitor is read out to the bit line. 2 is a driving method of a semiconductor memory device, characterized by performing the following operations.

According to a fourth aspect of the present invention, a plurality of memory cells each including a first transistor, a first ferroelectric capacitor, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines are provided. In the method for driving a semiconductor memory device having a memory cell array, a first potential, a second potential higher than the first potential, or a third potential higher than the second potential are sequentially applied to the plate line. A semiconductor memory device including a plate line potential conversion circuit.

According to a fifth aspect of the present invention, an absolute value of a voltage applied to both ends of a ferroelectric capacitor is provided in a semiconductor memory device for storing data “1” or “0” depending on a polarization direction of the ferroelectric capacitor. Is a semiconductor memory device that determines "1" or "0" data from the amount of charge read when the voltage changes between a first voltage larger than 0 V and a second voltage larger than the first voltage.

According to a sixth aspect of the present invention, the first voltage is set to 0.1.
The semiconductor memory device according to the fifth invention of the present application, wherein the voltage is 3 V or more and 1 V or less. The seventh invention of the present application is:
In a semiconductor memory device comprising a dummy cell using a ferroelectric capacitor, a voltage applied to both ends of the ferroelectric capacitor ranges from a first voltage higher than 0 V to a second voltage higher than the first voltage. This is a semiconductor memory device that generates a reference potential from the amount of charge read when the voltage changes to.

That is, according to the present invention, in a ferroelectric memory using a ferroelectric capacitor, the hysteresis curve characteristic of the ferroelectric capacitor is changed from 0 V bias to 0 V bias.
Since the polarization information up to the first voltage higher than V is not used, the hysteresis curve is shifted by Imprint, and despite the "1" Data, this shift causes the portion where the polarization inversion is small to contribute to the read charge. However, since the portion where the amount of polarization reversal from the first voltage to the second voltage higher than the first voltage is large is used, even if Imprint occurs, the read potential of "1" Data is high and the signal Deterioration can be suppressed. Also, regardless of "0" Data, this shift should originally have small polarization inversion and small readout charge. However, since it includes a portion where polarization inversion is likely to occur, the characteristic of the hysteresis curve in which readout charge increases is 0 V bias from 0 V bias. 0V
Because we do not use polarization information up to the larger first voltage,
Since the polarization between the first voltage and the second voltage higher than the first voltage is saturated and a portion where the read signal is small is used, even if Imprint occurs, the read potential of "0" Data is low, Signal degradation can be suppressed.

In this series of operations, the plate line potential is raised to the first potential while the bit line is fixed at the Vss potential, so that the ferroelectric capacitor has a zero hysteresis curve.
By applying a voltage from V to a first potential, the charge read out to the bit line can be discarded.
In the oating state, the plate line potential is increased from the first potential to a higher second potential, so that the first potential to the second potential are applied to the ferroelectric capacitor. , The charge read to the bit line can be used as a read signal, and even if Imprint occurs,
Signal degradation can be suppressed.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of a ferroelectric memory according to a first embodiment of the present invention and an operation diagram thereof. This shows a circuit operation method that can be applied to a conventional ferroelectric memory and reduces the influence of Imprint. The cell array is equivalent to a 1T1C type conventional FRAM, and the amplifying and equalizing circuit is:
There are a flip-flop circuit for amplifying a signal difference between bit lines and an equalizing circuit for three transistors (Q1 to Q3) for precharging and equalizing the bit line pair (/ Bl, BL) to Vss.
The operation is as follows. At Standby, the Plate potential is Vss and bit
The line potential is precharged to the Vss potential because the equalizing signal / EQL is high. At the time of the Active Cycle, first, the word line (W) is kept while the equalizing signal / EQL remains High, that is, while the bit line is fixed at Vss.
L0), and turn on the cell transistor.
The potential of the line (PL0) is increased by Voff, specifically, for example, about 0.5V. By this operation, a voltage of Voff is applied to both ends of the ferroelectric capacitor, and the charge flows to the Vss line because the bit line is fixed at Vss, and disappears. Second, the equalizing signal / EQL is set to Low level, and the bit line is set to Vss.
Floating in this state, and raise the Plate line potential from Voff to Vdd. As a result, the ferroelectric capacitor undergoes polarization inversion due to the presence of the bit line capacitance Cb, charges are read out to the bit line, and the bit line potential increases. At this time, the voltage applied to both ends of the ferroelectric capacitor is a locus that operates from Voff to (Vdd-read potential).

FIG. 2 shows a hysteresis curve of the ferroelectric capacitor showing the operation trajectory of FIG. The hysteresis curve in Fig. 2 (a) is a hysteresis curve after writing "0" Data in the ferroelectric capacitor and leaving it for a long time at the position □. Shows the curve on which the imprint has shifted. Similarly,
The hysteresis curve in Fig. 2 (b) is for the ferroelectric capacitor.
This is the hysteresis curve after writing for 1 "Data and leaving it for a long time at the position of □. This is the curve where the imprint occurs that causes the hysteresis curve to shift in the negative (left) direction. The point analysis indicates the operating point of the conventional reading method, and the solid line operating point analysis indicates the operating point of the operating method of FIG. 1 according to the present embodiment.

According to the method shown in FIG. 1, for example, the potential read out to the bit line of "1" Data is minus (left) parallel to the X axis by the amplitude potential of the bit line from the position of the Voff bias of "1" Data. From this point, a load curve of the slope of the value of the load capacitance Cb of the bit line is written, and the value crossing the hysteresis curve can be said to be the read potential. This is because, in actual operation, when the bit line is Vss and the Plate line is raised from Voff to Vdd, the cell node potential of (Vdd-Voff) becomes
This corresponds to a case where the charge Q is discharged and the bit line potential rises by receiving the charge Q. Similarly to the hysteresis, the potential read to the "0" Data bit line is drawn from the position of the "0" Data Voff bias by the amplitude potential of the bit line, minus (left) a line parallel to the X-axis, and this point Therefore, a value obtained by writing a load curve of the slope of the value of the load capacitance Cb of the bit line and intersecting the hysteresis curve can be said to be a read potential. FIG.
The final operating point of the conventional method, that is, the read potential of “1” and “0” Data is represented by 〇, and the final operating point of the method of FIG. , "0" Data read potential is represented by "black out". Fig. 2
(a) If "0" Data is left, "1" Data read potential and "
The difference in the read potential of 0 "Data is worse in the method of FIG. 1 than in the conventional method, but the absolute value of the signal amount is large because the hysteresis curve is originally shifted in a direction not affected by Imprint.

On the other hand, if "1" Data is left unchecked,
The difference between the read potential of 1 "Data and the read potential of" 0 "Data greatly deteriorates and decreases in the conventional method, whereas in the method of FIG. 1, this deterioration amount is suppressed and the read signal amount is reduced. It turns out that it is enough to secure.2T2C
In the cell having the configuration, the potential difference between “blackened” and “blackened” becomes the readout potential. In the 1T1C configuration, the reference potential is brought between the two “blackened” potentials. A signal can be secured. The reason why there are few signals of the conventional method after writing "1" Data is that the hysteresis curve shifts to the left in the case of Imprint after leaving "1" Data, so the hysteresis curve can be seen by reading "1" Data. From the 0 V position to the operating point “black circle”
At first, a large negative voltage is applied through a region where polarization inversion is unlikely to occur, and charges are finally released due to polarization inversion, and as a result, the “1” Data read potential drops.

On the other hand, in the method of FIG. 1, by shifting by Voff, it is not necessary to pass through the region where the initial domain inversion is unlikely to occur, and the slope of the domain-inverted region from Voff to “blackened” is sharp. Charge is read out to the bit line, so a large charge follows the locus of slight voltage movement, that is, the read potential of "1" Data rises higher than the read potential of "0" Data when viewed from the bit line Then, the signal of "1" Data becomes large. Also, when reading "0" Data, in the conventional method, the locus from the position of 0 V of the hysteresis curve to the operating point "black out" is at first entered from the domain-inverted region to the domain of polarization saturation. , A large charge is released, and as a result, the read potential of "1" Data rises. However, in the method of FIG. 1, since the first domain-inverted region is not used, the read potential of the bit line does not increase so much. , "0" Data signal increases (decreases). As a result, a decrease in the read signal due to the occurrence of Imprint can be suppressed, and a more stable and highly reliable ferroelectric memory can be realized.

Normally, the offset of Imprint is about 1 V at the maximum, and conversely, if it is less than 0.3 V, it is not enough to take circuit measures, and Voff is preferably 0.4 V or more and 1 V or less.

In effect, the effect is that the slope of the hysteresis curve between 0 V and Voff changes from “1” Data to “0” Data.
If this is larger, it will cause a reduction in the signal, so this is one solution to set Voff at the point where the "1" Data starts to become larger than the original "0" Data due to the voltage increase. is there. That is, the voltage value of the maximum Imprint is set to Voff. In addition, the operation trace shown in FIG. 2 has an effect on Imprint. Therefore, the circuit operation method is not limited to the circuit and operation method shown in FIG.

FIG. 3 shows Imprint and Depolarization (Relax
FIG. 1 shows the operation point analysis in the case of the conventional method and the method of FIG. 1 when both occur. Usually, when the ferroelectric film is left after the end of writing, there is a problem that the residual polarization amount at 0 V bias decreases. So, with Imprint
Even when both depolarizations occur, it is necessary to increase the signal under the condition that the present system becomes the minimum read signal compared to the conventional system. Fig. 3 shows the results of Impr.
Operating point analysis with hysteresis curve when int and Depolarization occur. 〇 is "1", "
0 "Data read potential," black circle "
Indicates the read potential of 1 "and" 0 "Data. Worst" 1 "Data
Even after leaving, the method of Fig. 1 is "1" Data
It can be seen that the difference between the read potentials of "0" and "0" Data is very effective.

FIG. 4 shows a second embodiment of the present invention.
1 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof. The only difference from FIG. 1 is that there is a transistor that precharges the bit line to Vss, but an equalizing transistor for setting the bit line pair to the same potential is omitted. Other circuit operations are the same as those in FIG. 1, and the effects are the same as those in FIGS.

FIG. 5 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to a third embodiment of the present invention. The only difference from FIG. 1 is that a 2T2C type memory cell in which memory cells are connected to both bit lines of a bit line pair is applied to one word line. Other circuit operations are the same as those in FIG. 1, and the effects are the same as those in FIGS.

FIG. 6 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to a fourth embodiment of the present invention. The difference from Fig. 1 is that the plate line is Voff while the bit line is fixed at Vss.
It is the same until the plate line is raised to Vdd after the bit line is floated and then the plate line is raised to Vss.
The point is to raise and lower the ate line from Vss to Vdd and from Vdd to Vss. It has been reported that once the Plate line is lowered to Vss and sensed, the variation of the paraelectric component of the ferroelectric capacitor can be canceled out.
This is an example in which a method of raising and lowering the Plate line of the present invention in two steps from Vss to Voff and from Voff to Vdd is combined with the method of raising and lowering the plate, and further combining the 2T2C configuration of FIG. Other circuit operations are the same as those in FIG.
Is the same as

FIG. 7 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to a fifth embodiment of the present invention. This shows a circuit operation method for reducing the influence of Imprint which can be applied to the ferroelectric memory of Japanese Patent Application No. 9-346404. The cell array forms a cell block by connecting a plurality of memory cells each having one cell transistor and one ferroelectric capacitor connected in parallel to form a cell block. One end is connected to a bit line through a block selection transistor. , The other end of which is connected to the Plate line, which is equivalent to the FRAM of the prior application. The amplification equalizing circuit includes a flip-flop circuit for amplifying a signal difference between bit lines, and a bit line pair (/ Bl, BL) connected to Vss. Precharge & Equali
There is an equalizing circuit of three transistors (Q1 to Q3) for ze.

The operation is as follows. In Standby, the Plate potential is Vss and the bit line potential is equal to the equalizing signal / EQL.
Since it is h, it is precharged to the Vss potential. At the time of Active Cycle, first, equalize signal /
While the EQL remains High, that is, the bit line is fixed at Vss, the selected word line (WL2) is turned off, the cell transistor is turned off, the block selection line BS0 is turned on, the block selection transistor is turned on, and the plate is turned on. line
The potential of (PL (/ BVL)) is increased by Voff, specifically, for example, about 0.5V. By this operation, a voltage of Voff is applied to both ends of the ferroelectric capacitor of the selected cell, and the charge flows to the Vss line because the bit line is fixed at Vss, and disappears. At this time, the ferroelectric capacitors of the non-selected cells of the selected block are short-circuited and protected. Second, the equalizing signal / EQL is set to Low level, the bit line is set to Floating in the state of Vss, and the Plate line potential is increased from Voff to Vdd. As a result, the ferroelectric capacitor undergoes polarization inversion due to the presence of the bit line capacitance Cb, charges are read out to the bit line, and the bit line potential increases. At this time, the voltage applied to both ends of the ferroelectric capacitor is a locus that operates from Voff to (Vdd-read potential). The locus of the potential applied to the ferroelectric capacitor of the selected cell at this time is equivalent to FIGS. 2 and 3, and as a result, a decrease in the read signal due to the generation of Imprint can be suppressed, and a more stable and highly reliable ferroelectric capacitor can be obtained. A dielectric memory can be realized.

In the method shown in FIG. 7, since a folded bit line configuration is used, for example, when the upper cell block is selected, BS0 and PL (/ BL) are selected, and the cell data is read to the / BL side, and the BL is read. For example, when selecting the lower cell block, BS1 and PL (BL) are selected, the cell data is read out to the BL side, and the / BL side is referred to.
e Become a bit line.

FIG. 8 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to a sixth embodiment of the present invention. 7 is different from FIG. 7 only in that there is a transistor for precharging the bit line to Vss, but an equalizing transistor for setting the bit line pair to the same potential is omitted. Other circuit operations are the same as those in FIG. 7, and the effects are the same as those in FIGS.

FIG. 9 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to a seventh embodiment of the present invention. The difference from Fig. 7 is that the Plate potential is set to the Voff potential from the beginning during standby, WL2 is lowered, and BS0 is raised, the bit line becomes Vs
Since it is fixed to s, the potential of Voff is automatically applied to the selected ferroelectric capacitor, and the charge in this portion can be discarded, which is equivalent to FIG. Then bit
The line is floated, the plate line is raised by Vdd, charge is read, sense amplification is performed, plate is further lowered, and after rewriting is completed, BS0 is lowered, WL2 is raised, and then the plate line is turned off.
The difference is that it returns to and enters the Preharge state. Other circuit operations are the same as those in FIG. 8, and the effects are the same as those in FIGS. This method uses the Pl in Standby in the configuration of the ferroelectric memory of the prior application.
Even if the ate potential is set to be higher than 0 V, the ferroelectric capacitor uses a feature that the cell polarization is not destroyed because it is short. In this method, first, Ch
Plate potential of all unselected cell arrays in ip is Vo
Since it is set to ff, it contributes as a stabilizing capacitance, and thus has the characteristic that fluctuations in the Plate potential of the selected cell array are reduced. Secondly, to raise the precharge to Voff,
Even if the operation is slow, it does not affect the Access Time.
There is a merit that the work to raise to Voff at the time of Access can be omitted and the speed can be increased.

FIG. 10 shows an eighth embodiment of the present invention.
1 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof. 9 is different from FIG. 9 only in that there is a transistor that preharges the bit line to Vss, but an equalizing transistor for making the bit line pair the same potential is omitted. Other circuit operations are the same as those in FIG. 9, and the effects are the same as those in FIGS.

FIG. 11 shows a ninth embodiment of the present invention.
1 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof. The difference from FIG. 7 is that in order to make a 2T2C configuration, one type of block select transistor and one type of Plate line are integrated, and / BL, B
The point is that data of "1", "0" or "0", "1" is read out from both of L to the bit line. Other circuit operations are the same as those in FIG. 7, and the effects are the same as those in FIGS.

FIG. 12 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to a tenth embodiment of the present invention. FIG. 12 shows a configuration obtained by combining FIG. 9 and FIG. 11, and has both effects. Other circuit operations are the same as those in FIG. 7, and the effects are the same as those in FIGS.

FIG. 13 shows a plate line drive circuit and its operation timing diagram showing an eleventh embodiment of the present invention. During standby, CK1 is High and Plate line PL
Is set to Vss. At the time of Active, CK1 is set to Low, CK3 is set to High, / CK3 is set to Low, the bit line is fixed to Vss, the potential from the Voff power source is transmitted to PL, and the Plate line is set to Voff. . Then, float the bit line
After that, set CK3 to Low and / CLK3 to High
The Vdd potential is transmitted to the plate by cutting off from the Voff power supply and making CK2 low to raise the plate line to Vdd. Then, after performing the sensing operation, CK2 is set to High, and C
The Plate potential is returned to Vss by setting K1 to High. This series of operations is used in FIGS.
A circuit for driving the plate line can be realized, and the effects as shown in FIGS. 2 and 3 can be exerted.

FIG. 14 is a diagram showing a plate line drive circuit and its operation timing according to a twelfth embodiment of the present invention. 13 is different from FIG. 13 in that the control line of / CK3 and the PMOS transistor for inputting the control line to the gate are omitted. Since the Voff potential is as low as about 0.5 V, the PMOS can be omitted and the plate drive circuit can be made smaller. Through this series of operations, a circuit for driving the Plate line used in FIGS. 1 and 7 can be realized, and the effects as shown in FIGS. 2 and 3 can be exerted.

FIG. 15 shows a plate line drive circuit and its operation timing diagram showing a thirteenth embodiment of the present invention. This circuit can be used in FIG. 9 and the like. At standby, CK3 is High, / CK3 is Low and Plat
The e-line PL is set to Voff, and in the active state, the bit line is fixed to Vss while the cell is selected, and the voltage of Voff is applied to the ferroelectric capacitor to release the charge. . After that, after the bit line is set to Floating, CK3 is set to Low and / CK3 is set to High, the Vdd potential is transmitted to Plate, and the plate line is raised to Vdd. Then, after performing the sensing operation, CK2 is set to High, C
The Plate potential is returned to Vss by setting K1 to High. Then, after closing the cell, CK3 is set to High again.
Set / CK3 to Low and return to Standby. With this series of operations, a circuit for driving the Plate line used in FIG. 9 and the like can be realized, and the effects as shown in FIGS. 2 and 3 can be exerted.

FIG. 16 shows an example of a Voff power supply generation circuit according to a fourteenth embodiment of the present invention. Capacitor for stability
And an operational amplifier that generates the same potential as the Vref potential
It has a Feedback circuit. Vref potential is 0.3V ~
Since the voltage is as low as 1 V, the band-gap reference circuit or the like is suitable only when the voltage becomes Vref. When Vref and Voff potentials are different,
What is necessary is just to make the Voff potential lowered by resistance division the input of the operational amplifier. With this circuit, a power supply for a circuit for driving the Plate line can be realized, and the effects as shown in FIGS. 2 and 3 can be exerted.

FIG. 17 shows a dummy cell according to the fifteenth embodiment of the present invention. In the dummy cell, the Plate potential is raised to Voff while the bit line potential is fixed at Vss, then the bit line is floated, and then the Plate potential is set to an arbitrary potential (Vdd or VDPL).
rence The potential of the bit line can be generated. Dummy cell, but when using ferroelectric capacitors, Imprint, Depola
Because of the influence of rization, the effects as shown in FIGS. 2 and 3 can be achieved. In this figure, the upper left diagram shows a case where a dummy cell is provided for each bit line, and the upper right diagram shows a case where a dummy cell is shared by a pair of bit lines. By raising the Plate potential to Voff while keeping the DRST signal High, the charge in the locus from Vss to Voff of the ferroelectric capacitor can be released in the dummy cell. Then, raise the dummy word line DWL0 and raise Plate to VDPL or Vdd,
A nce potential can be generated.

FIG. 18 shows a dummy cell according to a sixteenth embodiment of the present invention. The operation is slightly different from that of FIG. 17 with the same circuit configuration as that of FIG. The effect is the same as that of FIG. 18, and the effect as shown in FIGS. 2 and 3 can be obtained. Bit line to Vs
While the DRST signal is low and DWL0 is raised while fixing to s, the plate potential is set to Voff to release the charge.
7 is different from FIG.

FIG. 19 shows a dummy cell according to a seventeenth embodiment of the present invention, which can be applied to the ferroelectric memory of the prior application. While the bit line is fixed at Vss while / EQL is High, DRST is Low, DWL2 is Low, DBS0 is High, and the dummy plate line is raised from Vss to Voff. Is applied with a voltage of Voff, and charges are released.
After that, / EQL is set to Low and the bit line is set to Floating, then the Plate potential is raised to Vdd or VDPL, and Imprint
Since the reference potential is generated in a portion free from the influence of the above, the effects shown in FIGS. 2 and 3 can be exerted.

FIG. 20 shows a dummy cell according to the eighteenth embodiment of the present invention, which can be applied to the ferroelectric memory of the prior application. While DRST is High, dummy plate line
By increasing the voltage from Vss to Voff, it becomes possible to apply a voltage of Voff to both ends of the ferroelectric capacitor in the dummy cell block, and the electric charge is released. Then, change DRST to Lo
w, DBS0 is set to High and connected to the bit line.
Since the potential is raised to Vdd or VDPL and the reference potential is generated in a portion free from the influence of Imprint, the effects shown in FIGS. 2 and 3 can be exerted.

FIG. 21 shows a dummy cell according to a nineteenth embodiment of the present invention, which can be applied to the ferroelectric memory of the prior application. The DPL potential is already set to Voff during standby, and during active, the bit line potential is fixed at Vss while the DW potential is set to Vss.
By lowering L2 and raising DBS0, a voltage of Voff can be applied to both ends of the ferroelectric capacitor, and extra charges are released. Then, lower the / EQL and set the bit line to Floati
ng and then change the DPL potential from Voff to Vdd or VDDL
Increase the reference potential and generate the reference potential at the part that is not affected by Imprint. After that, lower DBS0 and set DRST to High.
h, the potential “0” is written to the ferroelectric capacitor of the dummy cell, then DPL is returned to Voff, DRST is lowered, DWL2 is returned to High, and / EQL is High, the state becomes the same as the Standby state. . Even with this method, the effects as shown in FIGS. 2 and 3 can be exerted.

[0053]

As described in detail above, according to the present invention, even when Imprint occurs, a bias portion on the hysteresis curve where the read signal decreases due to the influence of Imprint can be removed, and the read signal can be removed. Control the decline,
By securing a sufficient read signal, a more stable and highly reliable ferroelectric memory can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration of a ferroelectric memory and an operation diagram thereof according to a first embodiment of the present invention.

FIG. 2 is a motion trajectory on a hysteresis curve with Imprint showing the effect of the first embodiment.

FIG. 3 shows the effects of the first embodiment, Imprint and De.
Motion locus on a hysteresis curve with polarization.

FIG. 4 is a circuit configuration and operation diagram of a ferroelectric memory according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a circuit configuration of a ferroelectric memory and an operation thereof according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to a sixth embodiment of the present invention.

FIG. 9 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to a seventh embodiment of the present invention.

FIG. 10 shows a circuit configuration of a ferroelectric memory and an operation diagram thereof according to an eighth embodiment of the present invention.

FIG. 11 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to a ninth embodiment of the present invention.

FIG. 12 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to a tenth embodiment of the present invention.

FIG. 13 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to an eleventh embodiment of the present invention.

FIG. 14 is a diagram showing a circuit configuration of a ferroelectric memory and an operation thereof according to a twelfth embodiment of the present invention.

FIG. 15 is a diagram showing a plate line drive circuit and an operation timing thereof according to a thirteenth embodiment of the present invention.

FIG. 16 is a diagram illustrating a plate line drive circuit and an operation timing thereof according to a fourteenth embodiment of the present invention.

FIG. 17 is a diagram showing a plate line drive circuit and its operation timing, showing a fifteenth embodiment of the present invention.

FIG. 18 shows a Vof, illustrating a sixteenth embodiment of the present invention.
An example of an f power generation circuit is shown.

FIG. 19 shows a dummy cell according to a seventeenth embodiment of the present invention.

FIG. 20 shows a dummy cell according to the eighteenth embodiment of the present invention.

FIG. 21 shows a dummy cell according to a nineteenth embodiment of the present invention.

FIG. 22 is a circuit configuration of a ferroelectric memory of an FRAM according to a conventional example 1 and its operation diagram.

FIG. 23 is a circuit configuration of a ferroelectric memory of an FRAM according to Conventional Example 2 and an operation diagram thereof.

FIG. 24 is a typical Imprint characteristic diagram.

[Explanation of symbols]

/ BL, BL Bit line PL, PLi, PL (/ BL), PL (BL) Plate line WL, WLi Word line / EQL Bit line Vss Precharge signal BSi block select line DWLi Dummy word line DRST Dummy cell reset signal Voff Ferroelectric Bias voltage to capacitors CK1, CK2, CK3, / CK3 Plate potential control signal Vref Reference potential Ci coupling capacity DBSi Dummy cell block select line DWLi dummy word line DPL dummy plate line VDWL dummy word line potential VDPL dummy plate potential

Claims (7)

[Claims] 1. A memory cell comprises a first transistor and a first ferroelectric capacitor having one end connected to the source electrode and the other end connected to the drain electrode, and a plurality of the memory cells are connected in series. To form a memory cell unit, one end of which is connected to a bit line via a second transistor and the other end of which is connected to a plate line to form a memory cell block. Are arranged in a memory cell array to form a memory cell array, the plate line potential is raised to a second potential while the bit line is fixed at a first potential, and the first ferroelectric A first operation of applying a first potential and a second potential to both ends of the capacitor; and following the first operation, the bit line is placed in a floating state while the plate line voltage is applied. Driving the semiconductor memory device from the second potential to a higher third potential, and performing a second operation of reading the charge of the first ferroelectric capacitor to a bit line. 2. A memory cell comprising a first transistor and a first ferroelectric capacitor having one end connected to the source electrode and the other end connected to the drain electrode, and a plurality of the memory cells are connected in series. To form a memory cell unit, one end of which is connected to a bit line via a second transistor and the other end of which is connected to a plate line to form a memory cell block. Are arranged in a memory cell array to form a memory cell array, a first potential, a second potential higher than the first potential, or a third potential higher than the second potential are sequentially applied to the plate line. A semiconductor memory device comprising a plate line potential conversion circuit to be applied. 3. A memory cell array including a plurality of memory cells including a first transistor and a first ferroelectric capacitor, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines. In the method of driving a semiconductor memory device having the above, the plate line potential is raised to a second potential while the bit line is fixed at a first potential, and a first potential and a A first operation of applying a second potential, and following the first operation, raising the plate line potential from the second potential to a higher third potential while the bit line is in a floating state; A method for driving a semiconductor memory device, comprising: performing a second operation of reading a charge of a first ferroelectric capacitor to a bit line. 4. A memory cell array including a plurality of memory cells including a first transistor and a first ferroelectric capacitor, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines. The driving method of the semiconductor memory device having the first potential and the first potential on the plate line.
And a plate line potential conversion circuit for sequentially applying a second potential higher than the first potential or a third potential higher than the second potential. 5. In a semiconductor memory device storing data of “1” or “0” depending on the polarization direction of a ferroelectric capacitor, an absolute value of a voltage applied to both ends of the ferroelectric capacitor is larger than 0V. A semiconductor memory device that determines "1" or "0" data from the amount of charge read when the voltage changes between a first voltage and a second voltage higher than the first voltage. 6. The semiconductor memory device according to claim 5, wherein said first voltage is 0.3 V or more and 1 V or less. 7. A semiconductor memory device comprising a dummy cell using a ferroelectric capacitor, wherein a voltage applied to both ends of the ferroelectric capacitor is changed from a first voltage higher than 0V to a second voltage higher than the first voltage. Semiconductor memory device that generates a reference potential from the amount of charge read when the voltage changes between the voltages.