JPH1055681A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain electric charge reuse efficiency near a theoretical limit value of an electric charges reuse system and to contrive low power operation by applying an intermediate voltage between a reference voltage and a power source voltage to a charge recovery capacity line at least before the selecting operation of a driving line. SOLUTION: Before at least a driving line CPi (i=1-m) is started to select, a level of a capacity line CPO for collecting electric charges is set to intermediate voltage Vcc/2 between a power source voltage Vcc and a reference voltage. In this state, when switching is performed from the driving line CPi selected and pulse-driven to the next driving line CPi+1, first, a switching element and the capacity line CPO are connected, for example, a level of the driving line CPi being at power source voltage Vcc and pulse-driven is made intermediate voltage Vcc/2. The selected driving line CPi and the capacity line CPO are made a non-connection state and the capacity line CPO and the next driving line CPi+1 are connected by an element STri+1. Consequently, a level of a driving line selected next is made Vcc/2. That is, electric charges of 50% is reused.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device employing a charge recycling system.

[0002]

2. Description of the Related Art The charge recycling method is to collect and reuse charge charged in a node having a large capacity before discharging the charge (for example, IEICE Autumn Meeting 1994, p. 198; See "Charge Recycling in Memory Devices and Optimization").

FIG. 4 is a circuit diagram showing an example in which this charge recycling system is employed in a ferroelectric memory device.

In this ferroelectric memory device 10, memory cells MC11 to MCmj each including a switch transistor Tr and a ferroelectric capacitor FC are arranged in a matrix. Memory cells MC11 to MC1 arranged in the same row
, MCm1 to MCmj, the gates of the switching transistors Tr are connected to the same word lines WL1, WL2,..., WLm, and the memory cells MC11 to MCm1, MC12 to MC arranged in the same column
, MC1j to MCmj, the drains of the switching transistors Tr are the same bit lines BL1, BL2,
.., BLj. One electrode of the ferroelectric capacitor FC of each memory cell is connected to the source of the switching transistor Tr. Then, the memory cells MC11 to MC1j, MC21 to M arranged in the same row
The other electrodes (plate electrodes) of the ferroelectric capacitors FC of C2j,..., MCm1 to MCmj are connected to the same cell plate lines CP1 to CPm.

Each of the cell plate lines CP1 to CPm is connected to a cell plate line decoder / driver (referred to as a driver) DR.
, DR2,..., And DRm, the conduction state of which is controlled by signals CT1, CT2,.
.., Operatively connected to the charge recovery capacitance line CP0 via the STrm. Then, the electric field recovery capacitance line CP0
Is provided with a charge collection capacitor C0. The capacitance of the charge recovery capacitance line CP0 is equal to the cell plate line C
The value is set to a value sufficiently larger than the capacities C0 to Cm of P1 to CPm.

The charge recycling operation in such a configuration will be described by taking as an example a case where the cell plate line CP2 is selected from the state where the cell plate line CP1 is selected.

Before the start of the selection operation, for example, when the power is turned on or the sub-array power is turned on, the level of the charge recovery capacitance line CP0 is the ground level (0 V). When the selection is started, first, the driver DR
One control signal P1 is supplied at a low level, and the control signal N1 is supplied at a high level. At this time, the control signal of the driver DR2 is supplied at a high level for both P2 and N2. as a result,
Cell plate line CP1 is charged to the level of power supply voltage V _CC and held at that level. In addition, cell plate line C
The charge of P2 is discharged and held at the ground level.

Here, when switching from selection of the cell plate line CP1 to selection of the cell plate line CP2, the control signal P1 is switched to a high level and the control signal CT
1 is supplied to the gate of the switching transistor STr1 at a high level. As a result, the switching transistor STr1 is turned on, and the cell plate line CP1 at the V _CC level is electrically connected to the charge recovery capacitance line CP0 at the ground level.
Is supplied to the cell plate line CP2.

Next, after the control signal CT1 is switched to the low level and the switching transistor STr1 is switched to the non-conductive state, the control signal N2 to the driver DR2 is switched to the low level and the driver DR1 is switched to the low level.
Is switched to a high level, the control signal CT2 is at a high level and the switching transistor ST
It is supplied to the gate of r2. As a result, the charge of the cell plate line CP1 is discharged and the level of the cell plate line CP1 becomes the ground level, and the cell plate line CP2 at the ground level is electrically connected to the charge recovery capacitance line CP0. The charge of the charge recovery capacitance line CP0 is supplied to the cell plate line CP2. That is, it is reused.

Next, after the control signal CT2 is switched to the low level and the switching transistor STr2 is switched to the non-conductive state, the control signal P2 to the driver DR2 is switched to the low level only for a predetermined period. As a result, the level of the cell plate line CP2 changes to the power supply voltage V _CC
Charged to a level and held at that level. The above operation is sequentially repeated.

[0011]

However, in the above-described conventional example, the potential of the charge recovery capacitor line CP0 at the time of power-on or power-on of the sub-array is set to the ground level (0).
V), and every time the operation of selecting the cell plate line is repeated, as shown in FIGS. 5 (a) to 5 (c) and (d), charge recovery is performed based on the following equation by a so-called switched capacitor operation. The capacity line CP0 approaches V _CC / 2.

[0012]

## EQU1 ## V0 = ( _Vcc / 2) {1-exp (-t. (2f.Cn/C0)}}

In this process, the cell plate line CP1
The electric charge of CPm is not sufficient to charge not only the cell plate line to be selected next but also the electric charge collecting capacitor line CP0, and the electric charge close to 50% which is the theoretical limit of the electric charge recycling system. It is difficult to obtain reuse efficiency.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor capable of achieving a charge recycling efficiency close to 50%, which is the theoretical limit of a charge recycling system, and consequently reducing power consumption. It is to provide a device.

[0015]

In order to achieve the above object, the present invention provides at least two drive lines pulse-driven between a power supply voltage and a reference voltage, and each of the drive lines is connected to each of the drive lines. A capacitor element, a charge collection capacitor line, and a switching element that connects each of the drive lines and the charge collection capacitor line according to a control signal, and discharges when the selected drive line is pulse-driven. A semiconductor device adopting a charge recycling method of recovering charge to be transferred to the charge recovery capacitor line through a switching element and then reusing the charge to a next selected drive line through the switching element, wherein at least the drive line Before the selection operation starts, the intermediate voltage supply means for supplying an intermediate voltage between the power supply voltage and the reference voltage to the charge recovery capacitance line.

According to the present invention, the level of the charge recovery capacitor line is set to an intermediate voltage between the power supply voltage and the reference voltage at least before starting the operation of selecting the drive line. In this state, when performing selective switching from the selected pulse-driven drive line to the next drive line, first, the drive line selected and pulse-driven by the switching element is connected to the charge recovery capacitor line. For example, when the level of the pulse-driven drive line at the level of power supply voltage V _CC is set to an intermediate voltage, for example, V
_CC / 2. Then, the selected pulse-driven drive line and the charge recovery capacitance line are disconnected, and the charge recovery capacitance line and the next selected drive line are connected by the switching element. As a result, the level of the next selected drive line becomes V _CC / 2. That is, 50% of the charge is reused.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a ferroelectric memory device employing a charge recycling system according to the present invention. FIG.
, MC11 to MCmj are memory cells, DR1,
DRm are drivers (cell plate line decoders / drivers), STr1, STr2, ..., STrm are switching transistors, C0 is a charge recovery capacitor, BL1, BL2, ..., BLj are bit lines, WL1,
WL2,..., WLm are word lines, CP0 is a charge recovery capacitance line, CP1 to CPm are cell plate lines, and 11 is an intermediate voltage supply circuit.

In the ferroelectric memory device 10A, memory cells MC11 to MCmj each including a switch transistor Tr and a ferroelectric capacitor FC are arranged in a matrix. Memory cells MC11 to MC1 arranged in the same row
, MCm1 to MCmj, the gates of the switching transistors Tr are connected to the same word lines WL1, WL2,..., WLm, and the memory cells MC11 to MCm1, MC12 to MC arranged in the same column
, MC1j to MCmj, the drains of the switching transistors Tr are the same bit lines BL1, BL2,
.., BLj. One electrode of the ferroelectric capacitor FC of each memory cell is connected to the source of the switching transistor Tr. Then, the memory cells MC11 to MC1j, MC21 to M arranged in the same row
The other electrodes (plate electrodes) of the ferroelectric capacitors FC of C2j,..., MCm1 to MCmj are connected to the same cell plate lines CP1 to CPm.

Each of the cell plate lines CP1 to CPm is connected to drivers DR1, DR2,..., DRm, and the switching transistors STr1, ST whose conduction state is controlled by signals CT1, CT2,.
are operatively connected to the charge recovery capacitance line CP0 via r2,..., STrm. The electric charge collecting capacitor C0 is provided on the electric field collecting capacitance line CP0. The capacitance C0 of the charge recovery capacitance line CP0 is set to a value sufficiently larger than the capacitances C1 to Cm of the cell plate lines CP1 to CPm.

Driver DR1 is a p-channel MOS transistor connected in series between power supply voltage V _CC and ground line GND.
(PMOS) Transistor PT1 and n-channel MOS
(NMOS) is constituted by a transistor NT1. The gate of the PMOS transistor PT1 receives the control signal P
1 supply line and the NMOS transistor NT
One gate is connected to the supply line of the control signal N1, and the cell plate line CP1 is connected to the connection point between the drains of both transistors. Driver DR2 is connected to a PM connected in series between power supply voltage V _CC and ground line GND.
OS transistor PT2 and NMOS transistor NT2
It consists of. The gate of the PMOS transistor PT2 is connected to the control signal P2 supply line,
The gate of the S transistor NT2 is connected to the supply line of the control signal N2, and the cell plate line CP1 is connected to the connection point between the drains of both transistors. Similarly,
The driver DRm includes a PMOS transistor PTm and an NMOS transistor NTm connected in series between the power supply voltage V _CC and the ground line GND. P
The gate of the MOS transistor PTm is connected to the supply line for the control signal Pm, the gate of the NMOS transistor NTm is connected to the supply line for the control signal Nm, and the cell plate line CP1 is connected to the connection point between the drains of both transistors.
Is connected.

The intermediate voltage supply circuit 11 is connected to a supply line of V _CC / 2 and a charge recovery capacitance line CP0, and is constituted by a gate circuit M0 comprising an NMOS transistor having a gate connected to a supply line of a control signal φC. ing.
The signal φC is supplied at an active high level (V _CC level) before the start of selection of a cell plate line. Here, before the selection is started, for example, when power is turned on or when the subarray selection power is turned on.

Next, the charge recycling operation in the above configuration will be described with reference to FIG. 2 by taking as an example a case where the cell plate line CP2 is selected from the state where the cell plate line CP1 is selected.

For example, when power is turned on, control signal φ
C is supplied at a high level to the gate circuit M0 of the intermediate voltage supply circuit. As a result, the gate circuit M0 is turned on, and the voltage V _CC / 2 is supplied to the charge recovery capacitance line CP0. Then, for example, when the selection operation is started, control signal φC is switched to a low level. That is,
The charge recovery capacitance line CP0 is initialized to V _CC / 2.

When the selection is started, first, the driver DR
One control signal P1 is supplied at a low level, and the control signal N1 is supplied at a high level. At this time, the control signal of the driver DR2 is supplied at a high level for both P2 and N2. as a result,
In the driver DR1, the PMOS transistor PT
1 is maintained in a conductive state, and the NMOS transistor NT1
Are kept in a non-conductive state. As a result, the cell plate line CP1 is charged to the level of the power supply voltage V _CC and held at that level. In the driver DR2, PM
OS transistor PT1 is held in a non-conductive state, and NM
OS transistor NT1 is kept conductive. As a result, the charge on cell plate line CP2 is discharged and maintained at the ground level.

Here, when switching from selection of the cell plate line CP1 to selection of the cell plate line CP2, the control signal P1 is switched to a high level, and the control is performed in a state where the PMOS transistor PT1 is also kept in a non-conductive state. When the signal CT1 is at a high level and the switching transistor S
It is supplied to the gate of Tr1. Thus, the switching transistor STr1 is rendered conductive, since the charge collection capacitor line CP0 in the cell plate line CP1 and V _CC / 2 levels in the V _CC level is electrically connected, the cell plate line CP1 is V _CC / 2 level.

Next, after the control signal CT1 is switched to the low level and the switching transistor STr1 is switched to the non-conductive state, the control signal N2 to the driver DR2 is switched to the low level and the NMOS transistor NT2 is switched to the non-conductive state. Can be switched. Thereafter, the control signal N1 to the driver DR1 is switched to the high level, the NMOS transistor NT1 is switched to the conductive state, and the control signal CT2 is supplied to the gate of the switching transistor STr2 at the high level.
As a result, the charge of the cell plate line CP1 is discharged, and the level of the cell plate line CP1 becomes the ground level. The cell plate line CP2 at the ground level is electrically connected to the charge recovery capacitance line CP0 at the V _CC / 2 level. , The cell plate line CP2 is at the V _CC / 2 level.

Next, after the control signal CT2 is switched to the low level and the switching transistor STr2 is switched to the non-conducting state, the control signal P2 to the driver DR2 is switched to the low level only for a predetermined period and the PMO
S transistor PT2 is switched to the conductive state. As a result, the level of cell plate line CP2 changes to power supply voltage V
_{Charged to CC} level and held at that level. The above operation is sequentially repeated.

As described above, in the circuit of FIG. 1, when the selection operation is switched from the cell plate line CP1 = V _CC to the cell plate line = V _CC , for example, when the switching transistor STr1 is turned on, the cell plate line CP1 is turned on.
Becomes V _CC / 2, and when the switching transistor STr2 is turned on, the cell plate line C
The level of P2 becomes V _CC / 2. That is, 50% of the charge is reused.

As described above, according to the first embodiment, the cell plate line is supplied at the active high level (V _CC level) before the selection of the cell plate line is started, for example, when the power is turned on, or when the sub-array selection power is turned on. Control signal is φC
Gated to the supply line of the connection, is provided with the intermediate voltage supply circuit 11 which is constituted by a gate circuit M0 consisting connected NMOS transistors to V _CC / 2 supply line and the charge collection capacitor line CP0, charge A charge recycling efficiency close to 50%, which is the limit of the recycling system, can be obtained. As a result, power consumption can be reduced. In addition, the electric charge supplied from the cell plate line driver can always be kept constant, whereby there is an advantage that the design of the driver becomes easy and the driver size can be reduced.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of a ferroelectric memory device employing a charge recycling system according to the present invention.

[0031] This differs from the first embodiment the second embodiment described above, an intermediate voltage supply circuit 11A comprises a first and second between the supply line of the power supply voltage V _CC and the ground line
Are connected in series, and a charge collection capacitance line CP0 is connected to a connection point between the capacitors C11 and C12. Note that the first and second capacitors C11, C1
The capacitance values CV11 and CV12 of 2 are set to, for example, equal values.

In such a configuration, for example, when the power is turned on or the sub-array selection power is turned on, the charge recovery capacitance line CP0 is precharged to V _CC / 2 by the capacitance distribution of the capacitors C11 and C12. Further, the capacitors C11 and C12 also function as charge recovery capacitors having a value of (CV11 + CV12).

According to the second embodiment, the above-described first embodiment
In addition to the effects of the embodiment, there is an advantage that the charge recovery capacitor line CP0 can be precharged to V _CC / 2 without a control signal.

[0034]

As described above, according to the present invention,
A charge recycling efficiency close to 50%, which is the limit of the charge recycling method, can be obtained. As a result, power consumption can be reduced. In addition, the electric charge supplied from the driving line driver can always be kept constant, whereby there is an advantage that the driver design becomes easy and the driver size can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a ferroelectric memory device employing a charge recycling system according to the present invention.

FIG. 2 is a timing chart of the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of a ferroelectric memory device employing a charge recycling system according to the present invention.

FIG. 4 is a circuit diagram showing a ferroelectric memory device employing a conventional charge recycling method.

FIG. 5 is a diagram showing a process in which the potential of a charge recovery capacitor line approaches V _CC .

[Explanation of symbols]

10A, 10B: semiconductor device, MC11 to MCmj: memory cell, DR1, DR2,..., DRm: cell plate line decoder / driver (driver), STr1, STr
2, ..., STrm ... switching transistor, C0,
C11, C12: Charge recovery capacitor, BL1, BL
2,..., BLj... Bit lines, WL1, WL2,.
m: word line, CP0: charge recovery capacity line, CP1 to C
Pm: cell plate line; 11, 11a: intermediate voltage supply circuit.

Claims (4)

[Claims] At least two drive lines pulse-driven between a power supply voltage and a reference voltage, capacitance elements respectively connected to the respective drive lines, a charge recovery capacitance line, and the respective drive lines And a switching element for connecting the charge recovery capacitance line with the control signal in response to a control signal, and discharges a charge when the selected drive line is pulse-driven to the charge recovery capacitance line through the switching element. A semiconductor device adopting a charge recycling method in which a charge is reused for a next selected drive line through a switching element after collection, wherein at least before the start of the drive line selection operation, the charge recovery capacitor line is connected to the charge recovery capacitor line. A semiconductor device having intermediate voltage supply means for supplying an intermediate voltage between a power supply voltage and the reference voltage. 2. The gate circuit, wherein the intermediate voltage supply means is controlled to be conductive so as to connect the intermediate voltage source, the charge recovery capacitor line, and the intermediate voltage source before starting the drive line selection operation. 2. The semiconductor device according to claim 1, wherein the semiconductor device comprises: 3. The intermediate voltage supply means has first and second charge recovery capacitance elements connected in series between a power supply voltage source and a reference voltage source, and the charge recovery capacitance line is The semiconductor device according to claim 1, wherein the semiconductor device is connected to a connection point between the first charge collection capacitor and the second charge collection capacitor. 4. The semiconductor device according to claim 3, wherein the first charge collecting capacitor and the second charge collecting capacitor have the same capacitance value.