KR100400048B1 - Ferroelectric memory device - Google Patents

Abstract

The present invention provides a nonvolatile ferroelectric memory device which improves the number of repetitive reads / writes of a ferroelectric and has high reliability.

Equipped with a step-down power supply circuit which is lower than the power supply voltage Vdd supplied from the outside, improves the fatigue resistance and imprint resistance of the ferroelectric, and generates a voltage Vint higher than the withstand voltage of the ferroelectric, and applies Vint to the ferroelectric capacitance. The power supply voltage of the sense amplifier and the voltage supply circuit is set to Vint, the power supply voltage of the other peripheral circuits is set to Vdd, and as the voltage applied to the ferroelectric increases, deterioration of the ferroelectric characteristics due to fatigue or imprint increases. With this configuration, the number of repetitive operations can be improved by minimizing the influence of the signal voltage reduction, and the read / write reliability can be significantly improved compared with the conventional ferroelectric memory device.

Description

Ferroelectric memory device {FERROELECTRIC MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile semiconductor memories, and more particularly to ferroelectric memory devices using ferroelectric materials.

A capacitor made of a ferroelectric material (called a "ferroelectric capacitor") has hysteresis characteristics between the applied voltage and the polarization. For this reason, a ferroelectric memory device using a ferroelectric capacitor as a memory cell can write data by applying a voltage to the ferroelectric capacitor, and then retain the data by residual polarization even when the applied voltage is 0V. Therefore, this characteristic can be used to construct a nonvolatile ferroelectric memory device.

In a ferroelectric memory device, when reading, a bit line potential corresponding to 0/1 of the memory cell stored data is generated by applying a voltage to the ferroelectric capacitor, and the bit line potential difference generated along the polarization direction by the sense amplifier is read out. 0/1 is read. In order to perform the correct read operation by such a configuration, it is important to make the difference between the zero read bit line potential and the one read bit line potential large enough.

In addition, in order to stabilize the read operation, it is also important to design the voltage applied during writing to a voltage at which the polarization of the ferroelectric is sufficiently reversed.

A conventional ferroelectric memory device, particularly in a low voltage operation, is a method of controlling to apply a sufficient voltage to the ferroelectric at the time of reading in order to ensure a sufficient 0/1 read bit line potential difference, for example in Japanese Patent Laid-Open No. 9-7376. It is proposed to call. A conventional control method of this type and its configuration will be described below with reference to FIGS. 8 to 10.

In this conventional control method, the precharge potential of the bit line is set to be higher than the operating power source potential of the sense amplifier or the peripheral circuit in order to perform stable reading.

On the other hand, in a configuration in which the bit line precharge potential is not boosted, the voltage applied to the ferroelectric capacitor during reading becomes a charge redistribution between the ferroelectric capacitor and the bit line parasitic capacitor, and thus becomes smaller than the applied voltage at the time of writing. As a result, stable reading operation cannot be performed.

Therefore, in the ferroelectric memory device disclosed in Japanese Patent Laid-Open No. 9-7376, the precharge potential at the time of reading is increased, and the voltage applied to the ferroelectric capacitor at the time of reading is equal to the voltage applied at the time of writing. This is to realize stable reading operation.

Fig. 8 shows the structure of this conventional ferroelectric memory device. Referring to FIG. 8, a step-down power supply circuit 804 is provided to reduce power consumption of the peripheral circuit 802, and the power supply to the circuit is a step-down power supply that step-downs an external power supply Vhp supplied from the outside. Vcc).

On the other hand, the bit lines BL0 and BL1 are precharged with a voltage higher than the step-down power supply voltage Vcc, for example, the external power supply potential Vhp applied from the outside. That is, the external power supply Vhp is supplied to the precharge circuit 803.

9 is a diagram showing the configuration of a bit line circuit of a conventional ferroelectric memory device. The memory cell MC1 is composed of two ferroelectric capacitors FC11 and FC12 and two cell transistors TC11 and TC12. One end of the ferroelectric capacitors FC11 and FC12 is commonly connected to the plate line PL1, the other end of the ferroelectric capacitor FC11 is connected to the source of the cell transistor TC11, and the other end of the ferroelectric capacitor FC12 is a cell transistor ( TC12) is connected to the source. The gates of the cell transistors TC11 and TC12 are commonly connected to the word line WL1, the drain of the cell transistor TC11 is connected to the bit line BL0, and the drain of the cell transistor TC12 is the bit line BL1. Is connected to. The memory cells MC2 other than the memory cells MC1 also have the same circuit configuration as the MC1, and have the same structure and element size.

In this circuit configuration, the potential of the plate line PL1 is fixed at 1/2 of the step-down power supply voltage Vcc, that is, Vcc / 2.

The sense amplifier (SA) 801 is a first inverter consisting of a P-channel MOS transistor PM1 and an N-channel MOS transistor NM1 connected between sense amplifier activation signals SAP and SAN, and a P-channel MOS transistor PM2. ), And a latch type sense amplifier having an input terminal and an output terminal of a second inverter composed of an N-channel MOS transistor NM2 cross-connected, and an output terminal of the first inverter and an input terminal of the second inverter are connected to a bit line BL0. The input terminal of the first inverter and the output terminal of the second inverter are connected to the bit line BL1.

The precharge signal PBL is input to the gate, and the P-channel MOS transistors PM3 and PM4 connected between the bit lines BL0 and BL1 and the power supply Vhp are turned on when the bit lines are turned on. Is a precharge circuit 803 which precharges to the potential Vhp.

The output terminal of the sense amplifier (SA) 801 is connected to the I / O lines IO0 and IO1, respectively, via column switches Y0 and Y1 controlled on and off by the column select signal YSW.

FIG. 10 is a diagram for explaining the operation of the circuit shown in FIG. 9, and includes word lines WL1, plate lines PL1, precharge signals PBL, bit lines BL0, BL1, sense amplifier activation signals SAN. , SAP). At the time of reading, when the word line WL1 is at the high level, a voltage determined by the ratio of the bit line parasitic capacitances CB0 and CB1 and the ferroelectric capacitance is applied to the ferroelectric capacitor to read the data.

In rewriting, since the potential of the plate line PL1 is Vcc / 2, a voltage of Vcc / 2 is applied between the terminals of the ferroelectric capacitor.

According to this conventional configuration, the precharge voltage of the bit line is set to Vhp and higher than the operating voltage Vcc of the peripheral circuit 802 so that the voltage applied to the ferroelectric capacitor at the time of reading and the applied voltage at the time of writing are the same. As a result, stable reading operation can be realized.

When reading with the plate line at Vcc or ground potential at the time of reading, the voltage applied to the ferroelectric is sufficient, so it is not necessary to boost the precharge potential of the bit line, but may be at the ground potential or Vcc level.

5 shows the hysteresis characteristics of the ferroelectric. In Fig. 5, the horizontal axis represents voltage, and the vertical axis represents polarization (charge Q). The hysteresis characteristic deteriorates with fatigue of the ferroelectric film, imprint depending on the number of times of access to the memory cell, and increase of data retention time. That is, in the ferroelectric film of the memory cell in which the inversion of the hysteresis loop is repeatedly performed, the hysteresis loop decreases due to fatigue.

Fig. 6 shows the effect of increasing the number of repeated accesses of the ferroelectric capacitor on the read bit line potential due to this ferroelectric film fatigue phenomenon. That is, in the " 1 " read involving polarization inversion, the read bit line potential decreases with the increase in the number of read operations. On the other hand, the " 0 " reading of the polarization non-inverting operation does not depend so much on the number of read operations, and the read bit line potential becomes almost constant.

The ferroelectric memory device disclosed in Japanese Patent Laid-Open No. 9-7376 described with reference to FIGS. 8 to 10 has a problem described below.

The first problem is that the number of repetitive operations of a memory cell having a ferroelectric capacitor is reduced.

This is because the fatigue of the ferroelectric film of the memory cell and the characteristic deterioration such as imprint are not considered depending on the applied voltage.

In general, in the read / write cycle, it is at the time of writing that the voltage applied to the ferroelectric becomes maximum. In other words, the applied voltage at the time of writing determines the number of repetitive operations of the ferroelectric capacitor. As will be described later, when the applied voltage is lowered, the number of repetitive operations increases. However, when the applied voltage is less than the withstand voltage of the ferroelectric, correct recording cannot be performed.

Therefore, in this conventional ferroelectric memory device which boosts the bit line precharge potential at the time of reading, the precharge potential Vhp of the bit line is always higher than the minimum write potential and cannot be less than that.

In addition, since the same voltage is applied to the ferroelectric at the time of reading, the number of repetitive operations is smaller due to fatigue, imprint, or the like.

Further, since the need to step up the bit line precharge potential, the effect of reducing the internal power consumption by the step-down power supply circuit is small.

The second problem is that the bit line capacitors are not optimized for ferroelectric capacitor characteristics.

This is because the signal voltage of the bit line is not considered to be determined by the relation between the ferroelectric capacitor and the bit line capacitor. In other words, even if the bit line precharge potential is not boosted, a sufficient signal voltage can be obtained by selecting an optimal bit line capacitor based on the number of memory cells connected to the bit line.

Therefore, from the viewpoint of the stable operation considering the characteristic deterioration characteristic of the ferroelectric such as fatigue or imprint, this conventional method cannot expect the effect of the stable reading operation, but rather promotes the deterioration of the characteristics of the ferroelectric by raising the precharge potential. It causes a decrease in reliability.

Accordingly, the present invention has been made in view of the problems, and an object thereof is to solve a first and second problems relating to the number of repetitive operations of a ferroelectric capacitor in a semiconductor memory using a ferroelectric, and to provide a ferroelectric having a highly reliable readout circuit. It is to provide a memory device.

1 is a block diagram showing a configuration of a first embodiment of the present invention.

2 is a circuit diagram of a first embodiment of the present invention.

Fig. 3 is a signal waveform diagram showing operation timing of the first embodiment of the present invention.

4 is a block diagram showing a configuration of a second embodiment of the present invention;

5 is a graph showing the hysteresis characteristics of the ferroelectric.

6 is a graph showing a change in the bit line read voltage with respect to the number of repetitive operations.

7 is a graph showing changes in signal voltage with respect to the number of repetitive operations.

8 is a block diagram showing a conventional ferroelectric memory device.

9 is a circuit diagram of a conventional ferroelectric memory device.

Fig. 10 is a signal waveform diagram showing operation timing of a conventional ferroelectric memory device.

Explanation of symbols for main parts of the drawings

SA: sense amplifier BL0, BL1: bit line

WL1, WL2: Word line PL1, PL2: Plate line

PBL: precharge signal MC1, MC2: memory cell

FC11, FC12: ferroelectric capacitor TC11, TC12: cell transistor

CB0, CB1: Bit line parasitic capacitance 100, 200, 800: Ferroelectric memory device

101, 201: memory cell array, sense amplifier, voltage supply circuit

102, 202: peripheral circuit 103, 203: step-down power circuit

104: sense amplifier (SA) 105: precharge circuit

106: power supply circuit 107: word line driver circuit (WLD)

108: plate line driving circuit (PLD) 109: sense amplifier driving circuit (SAD)

801: sense amplifier 802: peripheral circuit

803: precharge circuit 804: step-down power circuit

In order to achieve the object, the ferroelectric memory device of the present invention is formed by sandwiching a ferroelectric film between first and second capacitor electrodes facing each other, and a capacitor for storing information by the polarization state of the ferroelectric, and one of a source and a drain. A plurality of memory cells composed of transistors connected to capacitor electrodes on one side of the capacitor are arranged in row and column directions, corresponding to each of the rows of the plurality of memory cells, and transistors of each memory cell in the corresponding row. A plurality of word lines connected to the gates of the plurality of gate lines, plate lines connected to the capacitor electrodes on the other side of the capacitors of the plurality of memory cells, and transistors of the respective memory cells of the corresponding columns, respectively arranged in correspondence with the columns of the plurality of memory cells; Memory cell including a plurality of bit lines connected to the other side of the source and the drain of the A ferroelectric memory device having a voltage supply circuit for supplying a potential to a memory cell array and a plurality of sense amplifiers connected to a bit line, the second supply potential being lower than the first supply potential from a first supply potential supplied from the outside. And a means for supplying a second supply potential and a ground potential to the first and second capacitor electrodes of the capacitor.

In the present invention, the second supply potential is such that the potential difference with the ground potential is equal to or higher than the withstand voltage of the ferroelectric.

In the present invention, the second supply potential is the minimum potential difference at which the potential difference between the second supply potential and the ground potential can be written and read with respect to the capacitor.

In the present invention, a step-down power supply circuit is provided as a means for generating the second supply potential from the first supply potential.

In the present invention, there is provided a plate line voltage supply circuit, a word line voltage supply circuit, and a sense amplifier driving circuit as means for applying the second supply potential and the ground potential to the first and second capacitor electrodes of the capacitor. The line voltage supply circuit has a function of supplying the plate line with a potential from the ground potential to the second supply potential, and the word line voltage supply circuit has a value greater than or equal to the threshold voltage of the memory cell transistor from the ground potential to the second supply potential. It has a function of supplying a potential to the word line, and the sense amplifier driving circuit has a function of supplying a potential from the ground potential to the second supply potential to the sense amplifier.

In the plate line voltage supply circuit according to the present invention, the power supply voltage of the circuit becomes a potential difference between the second supply potential and the ground potential.

In the word line voltage supply circuit according to the present invention, the power supply voltage of the circuit becomes a potential difference between the first supply potential and the ground potential.

In the word line voltage supply circuit according to the present invention, the power supply voltage of the circuit becomes a potential difference between the second supply potential and the ground potential.

In the sense amplifier driving circuit according to the present invention, the power supply voltage of the circuit becomes a potential difference between the second supply potential and the ground potential.

Embodiment of the invention

Embodiment of this invention is described. In the research process leading to completion of the present invention, the change in the read bit line potential due to fatigue depends on the voltage applied to the ferroelectric capacitor. For example, as shown in FIG. This possible number of iterations has been found to improve.

As an example, a starting chip of the ferroelectric memory device disclosed in pages 238 to 241 of the 1998 Symposium on VLSI Circuits will be described. In this paper, the starter chip is designed with a 0.8 µm CMOS process and a power supply voltage of 5 V, indicating that the number of repeat operations is about 10 ⁶ times.

However, in the above study, it was found that the fatigue characteristics were further improved by lowering the power supply voltage.

FIG. 7 replaces the read bit line potential in FIG. 6 with the difference (signal voltage) of the read bit line potential in the two bit lines connected to the sense amplifier SA.

Referring to Fig. 7, the signal voltage becomes smaller due to the applied voltage being smaller. When the input voltage is higher than the minimum allowable input signal voltage of the sense amplifier, correct read operation is possible and the number of repetitions in which the read operation is possible is increased.

The above is also true in the imprint phenomenon, and it is clear from the study that the number of repeatable times can be improved by decreasing the applied voltage as in the case of fatigue.

The present invention was developed on the basis of the above-described research. The ferroelectric is provided by stepping down the external power supply voltage VDD in a step-down circuit so that the voltage VINT applied to the ferroelectric is smaller than the operating voltage of the peripheral circuit and is equal to or greater than the withstand voltage of the ferroelectric. It is to improve the reliability by increasing the number of repetitive reads / writes of the memory device.

According to a preferred embodiment of the present invention, a means for applying a second supply potential VINT and a ground potential that step-down the external power supply voltage VDD to the first and second capacitor electrodes of the ferroelectric capacitor (106 in FIG. 2). And a plate line voltage supply circuit (PLD), a word line voltage supply circuit (WLD) and a sense amplifier drive circuit (SAD), and the plate line voltage supply circuit (PLD) has a second supply potential (VINT) from a ground potential. The word line voltage supply circuit WLD supplies a potential Vboot greater than the threshold voltage of the memory cell transistor from the ground potential to the second supply potential VINT from the ground potential to the word line. The sense amplifier drive circuit SAD is configured to supply a potential from the ground potential to the second supply potential VINT to the sense amplifier.

Example

EMBODIMENT OF THE INVENTION In order to demonstrate embodiment of this invention mentioned above in detail, the Example of this invention is described below with reference to drawings. 1 shows a basic circuit configuration of a nonvolatile semiconductor memory according to the first embodiment of the present invention.

Referring to Fig. 1, the step-down power supply circuit 103 steps down the external power supply voltage VDD to a step-down power supply voltage VINT which becomes an applied voltage to the ferroelectric. The external power supply voltage VDD is a power supply voltage for taking an interface with the outside, for example, 5V or 3.3V. The step-down power supply voltage VINT is a voltage such that the polarization of the ferroelectric capacitor is sufficiently reversed and the number of repetitions is improved, for example, 2.5 V.

The withstand voltage Vc of the ferroelectric capacitor is less than the step-down power supply voltage VINT.

The step-down power supply voltage VINT is a voltage applied to the ferroelectric capacitor and is used for the voltage applied to the plate line, the bit line, and the power supply of the sense amplifier. The step-down power supply voltage VINT is also used as a power supply for a control circuit because a constant potential is supplied regardless of the external power supply voltage VDD variation or temperature change. On the other hand, as the power source of other peripheral circuits in the memory, the external power supply voltage VDD is used as it is.

Fig. 2 shows an example of the memory cell array constituting the memory of the first embodiment of the present invention, the sense amplifier, and the voltage supply circuit 106 for supplying voltage to the memory cell array in detail.

Referring to FIG. 2, two adjacent bit lines BL0 and BO1 have parasitic capacitors CB0 and CB1, and one end of the sense amplifier SA includes four transistors PM1, PM2, NM1, and NM2. 104 is connected. That is, the sense amplifier (SA) 104 includes a first inverter composed of a P-channel MOS transistor PM1 and an N-channel MOS transistor NM1 connected in series between the sense amplifier activation signal SAP and ground GND, An input terminal and an output terminal of a second inverter composed of a P-channel MOS transistor PM2 and an N-channel MOS transistor NM2 are cross-connected with each other, and each includes a latch type sense amplifier connected to the bit lines BL0 and BL1, respectively.

The memory cell MC1 is composed of two ferroelectric capacitors FC11 and FC12 and two cell transistors TC11 and TC12.

One end of the ferroelectric capacitors FC11, FC12 is commonly connected to the plate line PL1, the other end of the ferroelectric capacitor FC11 is connected to the source of the cell transistor TC11, and the other end of the ferroelectric capacitor FC12 is a cell transistor. It is connected to the source of TC12. Gates of the cell transistors TC11 and TC12 are commonly connected to the word line WL1, and drains of the cell transistors TC11 and TC12 are connected to the bit lines BL0 and BL1, respectively.

Memory cells MC2 other than the memory cells MC1 also have the same circuit configuration as the memory cells MC1, and have the same structure and element size.

The plate line PL1 is connected to the output terminal of the plate line driver circuit (PLD) 108, and the sense amplifier activation signal SAP is connected to the output terminal of the sense amplifier drive circuit (SAD) 109. The output stages of the plate line driver circuit (PLD) 108 and the sense amplifier driver circuit (SAD) 109 are both P-channel MOS transistors and N-channel MOS transistors connected in series between the circuit power supply and ground (GND). It consists of the CMOS inverter which consists of.

The power supply potential of the plate line driving circuit (PLD) 108 and the sense amplifier driving circuit (SAD) 109 is a step-down power supply voltage (VINT), and the plate line connected to the output terminal of the plate line driving circuit (PLD) 108. (PL1) and the potential supplied to the bit line connected to the output terminal of the sense amplifier drive circuit (SAD) 109 all become the step-down power supply voltage VINT at maximum.

The word line WL1 is connected to the output terminal of the word line driver circuit (WLD) 107. Since the word line needs to be supplied with a potential Vboot stepped up by the threshold voltage Vt of the cell transistor more than the step-down power supply voltage VINT, the power supply potential of the word line driving circuit WLD 106 is a boost potential ( Vboot).

The power supply voltage Vboot supplied to the word line driver circuit WLD 107 may be boosted by a booster circuit (not shown) of the step-down power supply voltage VINT, or the external power supply potential VDD is higher than VINT. If the value is higher than the voltage Vt, the external power supply potential VDD may be used as it is.

As the other control signals of the memory cell array, the precharge signal PBL input to the gates of the MOS transistors PM3 and PM4 constituting the precharge circuit 105 and the gates of the column switches Y0 and Y1. The boost potential Vboot is also supplied as the high level to the column selection signal YSW input to the input signal.

FIG. 3 is a signal waveform diagram for explaining the timing operation of the circuit shown in FIG. 2, and includes a word line WL1, a plate line PL1, a precharge signal PBL, a sense amplifier activation signal SAP, and a bit line. (BL0, BL1) and signal waveforms of the column selection signal YSW are shown.

The bit lines BL0 and BL1 are precharged to the GND (ground) level in the period during which the precharge signal PBL is at the boost potential Vboot.

Next, the word line WL1 becomes the boost potential Vboot, and the memory cell connected to the word line WL1 is selected.

Next, the plate line PL1 becomes the step-down power supply potential VINT level from the ground level, a voltage is applied to the ferroelectric capacitors FC1 and FC12, and the bit line read potential according to the data of 0/1 Is read on BL0, BL1.

In this embodiment, the potential of the bit line on the side where the ferroelectric capacitor is read inverted is higher than that of the non-inverted read side.

At this time, since charge redistribution occurs between the parasitic capacitors CB0 and CB1 of the bit line and the ferroelectric capacitors FC11 and FC12, the voltage (terminal to terminal voltage) applied between the electrodes of the ferroelectric capacitor is the step-down power supply voltage (VINT). )

Next, the sense amplifier activation signal (SAP) becomes the step-down power supply voltage (VINT) level so that the sense amplifier (SA) 104 is activated, and the data is detected by amplifying the difference (signal voltage) of the two bit line read potentials. do.

Next, the column select signal YSW becomes the boost potential Vboot level, the column switches Y0 and Y1 are turned on, and the read data is output from the I / O buses IO0 and IO1 to the outside. The plate line PL1 is at the ground GND level, and data is rewritten to the ferroelectric capacitor of the memory cell in which the reading is performed.

Finally, the bit lines BL0 and BL1 are discharged to the GND level, the word lines are returned to the GND level, and the read cycle is terminated.

The write cycle is performed except that write data from the I / O bus is written to the bit lines BL0 and BL1 through the column switches Y0 and Y1 that are turned on by the column select signal YSW. The timing waveform of each signal line shown in Fig. 2 is identical to the cycle of reading.

As described above, according to the present embodiment, since the voltage (terminal to terminal voltage) applied between the electrodes of the ferroelectric capacitor becomes the step-down power supply voltage VINT at the maximum, the number of repetitive operations of the ferroelectric can be increased, Reliability can be improved.

In the present embodiment, a ferroelectric memory device using a memory cell having a two transistor two capacitor configuration has been described. However, the present invention can also be applied to a ferroelectric memory device using a one transistor one capacitor type memory cell.

4 is a diagram showing the configuration of a second embodiment of the present invention. Referring to FIG. 4, in the second embodiment of the present invention, the power source potential in the ferroelectric memory device 200 includes the peripheral circuit 202, and all of them are the step-down power supply voltage VINT. The structure is the same as that of the first embodiment except for this.

According to the second embodiment of the present invention, in addition to the effect of increasing the number of repetitive operations of the ferroelectric capacitor, it is not necessary to change the external power supply voltage even when it is necessary to reduce the internal power supply voltage by reducing the transistor size.

In addition, in the second embodiment of the present invention, the power supply voltage is lowered, thereby reducing the power consumption of the entire circuit.

Also in the second embodiment of the present invention, the present invention can be applied not only to ferroelectric memory devices using 2 transistors 2 capacitor type memory cells but also to ferroelectric memory devices using 1 transistor 1 capacitor type memory cells.

As described above, according to the present invention, the effect of reducing the signal voltage can be minimized, the number of repetitive operations can be improved, and the read / write reliability can be significantly improved compared to a conventional ferroelectric memory device. Exert.

The reason is that in the present invention, considering the fact that the higher the voltage applied to the ferroelectric capacitor, the deterioration of the ferroelectric properties due to fatigue or imprint increases, the internal power voltage generated by the external power voltage smaller than the external power voltage defined by the interface with the external memory is It is because it set as the structure supplied as a potential of a cell.

Claims (13)

A memory cell having a ferroelectric film formed between the first and second capacitor electrodes, the capacitor storing information by the polarization state of the ferroelectric film, and a transistor having one side of a source and a drain connected to a capacitor electrode of one side of the capacitor. These are arranged in a plurality of array shapes in the row direction and the column direction, A plurality of word lines arranged corresponding to each of the rows of the plurality of memory cells and connected to the gates of the transistors of the respective memory cells of the corresponding rows; A plurality of plate lines connected to capacitor electrodes on the other side of the capacitors of the plurality of memory cells; A memory cell array disposed corresponding to each of the columns of the plurality of memory cells and having a plurality of bit lines connected to the other side of the source and the drain of the transistor of each of the memory cells in the corresponding column; And In a ferroelectric memory device having a plurality of sense amplifiers connected to the bit line, Means for generating a second supply potential lower than the first supply potential from a first supply potential supplied from the outside; And And means for supplying said second supply potential and ground potential to said first and second capacitor electrodes of said capacitor. The method of claim 1, The potential difference between the second supply potential and the ground potential is greater than the withstand voltage of the ferroelectric. The method according to claim 1 or 2, And the potential difference between the second supply potential and the ground potential is a minimum potential difference that can be written to and read from the capacitor. The method according to claim 1 or 2, And means for generating said second supply potential from said first supply potential comprises a step-down power supply circuit. The method according to claim 1 or 2, Means for supplying the second supply potential and ground potential to the first and second capacitor electrodes of the capacitor, A plate line voltage supply circuit for supplying the plate line with a potential from the ground potential to the second supply potential; A word line voltage supply circuit for supplying the second supply potential to the word line from the ground potential; And And a sense amplifier driving circuit for supplying a potential from the ground potential to the second supply potential to the sense amplifier. The method of claim 5, And the power supply voltage of the circuit in the plate line voltage supply circuit is a potential difference between the second supply potential and the ground potential. The method of claim 5, And the power supply voltage of the circuit in the word line voltage supply circuit is a potential difference between the first supply potential and the ground potential. The method of claim 5, In the word line voltage supply circuit, a power supply voltage of the circuit is a potential difference between the potential applied to the second supply potential or more than the threshold voltage of the memory cell transistor and the ground potential. The method of claim 5, In the sense amplifier driving circuit, the power supply voltage of the circuit is a potential difference between the second supply potential and the ground potential. Based on the second power supply voltage having a lower voltage value than the first power supply voltage supplied from the outside, the maximum value of the terminal-to-terminal voltage applied to the ferroelectric capacitor of the memory cell during the read and write operations is the second power supply voltage. And a ferroelectric memory device. It includes a step-down power circuit for stepping down the external power supply voltage, The step-down power supply voltage stepped down by the step-down power supply circuit is applied to the plate line and the bit line using the voltage applied to the ferroelectric capacitor of each memory cell of the memory cell array, Power the sense amplifier, And a voltage between terminals of the ferroelectric capacitor inserted between the drain or source of the cell transistor of the memory cell and the plate line becomes a step-down power supply voltage at a maximum. The method of claim 11, Supplying a boosted potential higher than a threshold voltage of a cell transistor or the external power supply voltage as a power supply voltage of a circuit for driving a word line for selecting a row in the memory array, A ferroelectric memory, characterized in that the boost potential or the external power supply voltage is supplied as a potential of a high level of a precharge signal that is a control signal for supplying a bit line to a precharge circuit and a column switch signal for selecting a column in the memory array; Device. 12. The ferroelectric memory device according to claim 11, wherein the external power supply voltage is supplied as it is, or the step-down power supply voltage is supplied as a power source for the peripheral circuit in the device.