JPH11134874A - Semiconductor storage device and access method for semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor storage device in which the generation of an in-print effect can be suppressed easily and surely by a method wherein, when first data is stored or read out, a first state s inverted once into a second state so as to be then returned to the first state, the second state is inverted once into the first state so as to be then returned to the second state when second data is stored or read out. SOLUTION: Storage data '1' is stored on a ferroelectric capacitor 61. Storage data '0' is stored on a ferroelectric capacitor 62. In this case, when the data in the ferroelectric capacitors 61, 62 are read out, a control part gives a signal H to a word line WL, and switches 63, 64 are closed. Then, the control part sets a plate line PL to H. When the plate line is set to H, electric charges are discharged toward bit lines BL1, BL2 from the ferroelectric capacitors 61, 62, and a current flows. The amount of the discharged electric charges is different according to the polarization state of the ferroelectric capacitors 61, 62.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for accessing the semiconductor memory device, and more particularly to suppressing the occurrence of an imprint effect.

[0002]

2. Description of the Related Art In recent years, there has been provided a ferroelectric memory device which realizes data non-volatility by using a ferroelectric material for a capacitor of a memory cell. The ferroelectric capacitor has a hysteresis characteristic, and polarization of different polarities according to the history remains even when the electric field becomes “0”. A nonvolatile memory device is realized by expressing data by the polarization of a ferroelectric capacitor.

FIG. 4 shows a circuit diagram of a ferroelectric capacitor. Ferroelectric capacitors 61 and 62 are provided on bit lines BL1 and BL2, respectively. Also, in FIG.
Voltage related to ferroelectric capacitor (bit line BL when plate line PL shown in FIG. 4 is used as a reference potential)
1, a potential of BL2) and a polarization state (in the figure, represented by "charge" equivalent to the "polarization state"), showing a hysteresis characteristic.

In FIG. 3, it is assumed that a state in which polarization Z1 occurs corresponds to storage data "1" and a state in which polarization Z2 occurs corresponds to storage data "0". By checking which polarization state the ferroelectric capacitor is in, the data stored in the ferroelectric capacitor can be read. The storage data “1” is stored in the ferroelectric capacitor 61 shown in FIG.
1) Assume that storage data “0” is stored in the ferroelectric capacitor 62 (polarization Z2 in FIG. 3).

FIG. 5 is a timing chart for reading stored data. When reading the stored data of the ferroelectric capacitor, an H signal is applied to the word line WL (timing T52), and the switches 63 and 64 of FIG. 4 are closed. Then, the plate line PL is set to H (timing T54 to T56).

When the plate line PL is set to H, charges are discharged from the ferroelectric capacitors 61 and 62 toward the bit lines BL1 and BL2, and a current flows. The amount of the discharged electric charge depends on the ferroelectric capacitor 6
It differs depending on the polarization states of the first and second polarizations.

That is, the ferroelectric capacitor 61 emits a relatively large amount of electric charge, and the ferroelectric capacitor 62 emits a relatively small amount of electric charge. At a timing T58 in FIG. 5, the sense amplifier is turned on, and is divided into H and L according to the discharged charges. In this case, as shown in FIG. 5, the bit line BL1 goes high and the bit line BL2 goes low, so that the storage data "1" is stored in the ferroelectric capacitor 61 and the ferroelectric capacitor 6
It can be seen that the stored data “0” is stored in No. 2.

In the ferroelectric capacitor 61 in which a large amount of electric charge is released upon reading and the polarization state is inverted,
The stored data will be destroyed. For this reason,
Immediately after the reading, it is necessary to rewrite the stored data, that is, to reverse the polarization state again to return to the original state.

When the sense amplifier is turned on at a timing T58 in FIG. 5, the plate line PL is at L level, so that the polarization state of the ferroelectric capacitor 61 is inverted again to the original polarization state. (Rewrite). Thereafter, the plate line PL becomes H (timing T60 to T62), and the stored data is not destroyed (the polarization state is not inverted).
Is maintained in a polarized state. And the timing T
The word line W is set to L at 64 and the switch 63 of FIG.
Open 64.

The above-mentioned ferroelectric capacitors 61 and 62
Will be described based on the hysteresis characteristics of FIG. First, the ferroelectric capacitor 6
Regarding 1, the polarization state shifts from P1 to P2 in FIG. 3 from timing T54 to T56, and the polarization state reaches P4 at timing T58 at which rewriting is performed. Then, the control returns from P4 to P1 at timing T64.

As described above, in the ferroelectric capacitor 61 in which stored data is destroyed by reading, the polarization state goes around the hysteresis characteristic shown in FIG. 3 at the time of reading and rewriting.

On the other hand, in the ferroelectric capacitor 62, the polarization state shifts slightly from P3 in FIG. 3 to P2 along the broken line from timing T54 to T56, and returns to P3 at timing T58. . Then, at timing T60, the process shifts from P3 to P2 along the broken line, and returns to P3 at timing T62.

As described above, in the ferroelectric capacitor 62 in which the stored data is not destroyed by reading, the polarization state does not go around the hysteresis characteristic shown in FIG. Just do it.

By the way, a ferroelectric substance has a property (imprint effect) that when a certain polarization state is maintained for a long time, the polarization state is "hased" and a hysteresis characteristic is distorted. For this reason, if a long time elapses while a fixed storage data is stored, an imprint effect occurs in the ferroelectric capacitor. When the imprint effect occurs, the amount of charges emitted at the time of reading changes.

In particular, when storage data opposite to the storage data when the imprint effect occurs is newly written, the ability to retain the polarization state of the new storage data is affected by the effect of the customization of the original storage data. The new storage data cannot be read accurately. That is,
Over time, the function as a storage device deteriorates,
There is a possibility that it cannot be used.

As described above, in the ferroelectric capacitor 61 in which stored data is destroyed by reading, the polarization state goes around the hysteresis characteristic shown in FIG. 3 when reading and rewriting the stored data. Therefore, a fixed polarization state is not maintained for a long time, and the imprint effect is unlikely to occur.

On the other hand, as for the ferroelectric capacitor 62 whose stored data is not destroyed by reading,
At the time of reading, the polarization state does not go around the hysteresis characteristic shown in FIG. 3 but merely shifts between P3 and P2. For this reason, a fixed polarization state is maintained for a long time, and there is a possibility that an imprint effect due to the “habitation” may occur.

As a conventional technique for suppressing the occurrence of the imprint effect, there is a nonvolatile random access memory disclosed in Japanese Patent Application Laid-Open No. Hei 8-264665. This publication discloses that reading can be performed at a low voltage, and a device with less influence on imprint and film fatigue resistance can be obtained.

However, in this nonvolatile random access memory, the generation of the imprint effect of the ferroelectric material is limited to the dummy cell, and the generation of the imprint effect of the memory cell for storage is suppressed. I can't. That is, there are only a limited number of targets that can suppress the generation of the imprint effect, and the occurrence of the imprint effect in the semiconductor memory device cannot be reliably suppressed.

As another conventional technique for suppressing the occurrence of the imprint effect, there is a ferroelectric memory device disclosed in Japanese Patent Application Laid-Open No. 8-147983. In this ferroelectric memory device, the memory cell capacitor for storage is repeatedly operated until the capacitance characteristic does not change in the 1T1C type device, and the capacitance value of the dummy cell capacitor is determined according to the capacitance characteristic at that time. In this way, the effect of the imprint effect is reduced.

However, in this ferroelectric memory device, it is necessary to repeatedly operate the memory cell capacitor for storage until the capacitance characteristic does not change, and then determine the capacitance value of the dummy cell capacitor, which is easy and reliable. In addition, the occurrence of the imprint effect cannot be suppressed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device and an access method for the semiconductor memory device which can easily and surely suppress the occurrence of an imprint effect.

[0023]

According to a first aspect of the present invention, a semiconductor memory device includes a first state corresponding to a first data and a second state corresponding to a first data.
When the first data is stored or read in the semiconductor memory device that stores the first data or the second data by holding the second state corresponding to the data,
When the state is once inverted to the second state, and then returned to the first state, and the second data is stored or read,
The second state is once inverted to the first state and then returned to the second state.

According to a second aspect of the present invention, a semiconductor memory device stores first data or second data by holding a first state corresponding to first data or a second state corresponding to second data. In the storage device, when at least the first data is stored or read, apart from the storage processing or the read processing, the first state is once inverted to the second state as ancillary processing, and then returned to the first state. It is characterized by:

According to a third aspect of the present invention, there is provided a semiconductor memory device according to the first or second aspect.
The state is a first polarization state in which the polarizable region is polarized,
The second state is characterized in that the polarizable region is a second polarization state polarized in a direction opposite to the first polarization state.

According to a fourth aspect of the present invention, in the semiconductor memory device, the polarizable region is polarized to a first polarization state or to a second polarization state opposite to the first polarization state.
The first data corresponding to the first polarization state or the second data corresponding to the second polarization state is stored, and the second data is read out by inverting the second polarization state to the first polarization state. In the semiconductor memory device that reads out the second data and then returns the first polarization state to the second polarization state, at least when the first data is stored or read, separately from the storage processing or the read processing,
As an ancillary process, the first state is once inverted to the second state, and then returned to the first state.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the third or fourth aspect, the separable region is made of a ferroelectric material.

According to a sixth aspect of the present invention, there is provided an access method for a semiconductor memory device, wherein a first state corresponding to first data or a second state corresponding to second data is maintained.
In the method of accessing a semiconductor memory device for storing data or second data, when storing or reading out first data, the first state is once inverted to the second state, and then returned to the first state; When the second data is stored or read, the second state is once inverted to the first state and then returned to the second state.

According to a seventh aspect of the present invention, there is provided an access method for a semiconductor memory device, wherein the first state corresponding to the first data or the second state corresponding to the second data is maintained.
In the method of accessing a semiconductor memory device for storing data or second data, when storing or reading at least the first data, the first state is temporarily changed to the second state as ancillary processing, separately from the storage processing or the reading processing. It is characterized by returning to the first state after inversion.

[0030]

In the semiconductor memory device according to the first aspect, when the first data is stored or read, the first state is once inverted to the second state, and then returned to the first state; When storing or reading the second data, the second state is once inverted to the first state and then returned to the second state.

That is, when the first data or the second data is read, the state is once inverted and then returned to the original state. Therefore, the risk that the first state and the second state are held for a long time can be reduced, and the first state and the second state can be reduced.
It is possible to reliably suppress the occurrence of the imprint effect due to the customization of the state or the second state. Further, at the time of reading, it is only necessary to reverse the state once and then return to the original state, so that the occurrence of the imprint effect can be easily suppressed.

In the semiconductor memory device according to the second aspect, at least when the first data is stored or read, the first state is temporarily inverted to the second state as an ancillary process separately from the storage process or the read process. After the first
Return to the state.

Therefore, the risk of the first state being held for a long time can be reduced, and the occurrence of the imprint effect due to the habit of the first state can be reliably suppressed. After the first state is once inverted to the second state,
Since it is only necessary to return to the first state, it is possible to easily suppress the occurrence of the imprint effect. Further, since additional processing is not performed in conjunction with storage processing or read processing and only independent processing is performed independently of storage processing or read processing, control of processing is easy and efficient.

In the semiconductor memory device according to the third aspect, the first state is a first polarization state in which the polarizable region is polarized, and the second state is that the polarizable region has a direction opposite to the first polarization state. In the second polarization state.

Therefore, the risk that the first polarization state or the second polarization state is maintained for a long time can be reduced, and the imprint effect due to the first polarization state or the second polarization state can be easily generated. It can be suppressed reliably.

In the semiconductor memory device according to the fourth aspect, at least when the first data is stored or read, the first state is once inverted to the second state as an ancillary process separately from the storage process or the read process. After the first
Return to the state.

For this reason, the risk that the first state is held for a long time can be reduced, and the occurrence of the imprint effect due to the habit of the first state can be reliably suppressed. After the first state is once inverted to the second state,
Since it is only necessary to return to the first state, it is possible to easily suppress the occurrence of the imprint effect. Further, since additional processing is not performed in conjunction with storage processing or read processing and only independent processing is performed independently of storage processing or read processing, control of processing is easy and efficient.

In the semiconductor memory device according to the fifth aspect, the separable region is a ferroelectric.

Therefore, the danger that the first polarization state or the second polarization state of the separable region in the ferroelectric material is maintained for a long time can be reduced, and the first polarization state or the second polarization state can be reduced. The generation of the imprint effect can be easily and reliably suppressed.

According to a sixth aspect of the present invention, in storing or reading out the first data, the first state is once inverted to the second state, and then returned to the first state. When storing or reading the second data, the second state is once inverted to the first state and then returned to the second state.

That is, when the first data or the second data is read, the state is once inverted and then returned to the original state. Therefore, the risk that the first state and the second state are held for a long time can be reduced, and the first state and the second state can be reduced.
It is possible to reliably suppress the occurrence of the imprint effect due to the customization of the state or the second state. Further, at the time of reading, it is only necessary to reverse the state once and then return to the original state, so that the occurrence of the imprint effect can be easily suppressed.

In the access method of a semiconductor memory device according to the present invention, at least when the first data is stored or read, the first data is stored separately from the storage process or the read process.
As ancillary processing, the first state is once inverted to the second state, and then returned to the first state.

Therefore, the risk that the first state is maintained for a long time can be reduced, and the occurrence of the imprint effect due to the habit of the first state can be reliably suppressed. After the first state is once inverted to the second state,
Since it is only necessary to return to the first state, it is possible to easily suppress the occurrence of the imprint effect. Further, since the additional processing is not performed only in conjunction with the storage processing or the reading processing and is performed separately from the storage processing or the reading processing, the control of the processing is easy and efficient.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device and a method of accessing the semiconductor memory device according to the present invention will be described with reference to the drawings. In this embodiment, two transistors 2
A capacitor type ferroelectric memory is taken as an example.

FIG. 1 is a circuit diagram of the sense amplifier 2, the ferroelectric capacitors 61 and 62, and the like. Ferroelectric capacitor 6
The ferroelectric portions 1 and 62 are polarizable regions in the present embodiment. FIG. 2 is a timing chart at the time of reading stored data stored in the ferroelectric capacitors 61 and 62. FIG. 3 is a graph showing a hysteresis characteristic representing a relationship between a voltage and a polarization state of the ferroelectric capacitor.

In FIG. 3, it is assumed that the state where polarization Z1 occurs corresponds to storage data "1", and the state where polarization Z2 occurs corresponds to storage data "0". In the present embodiment, the state in which the polarization Z1 occurs is the first polarization state or the first state, and the storage data “1” is the first data. In the present embodiment, the state in which the polarization Z2 occurs is the second polarization state or the second state, and the stored data “0” is the second data.

By checking which polarization state the ferroelectric capacitor is in, the data stored in the ferroelectric capacitor can be read. It is assumed that storage data “1” is stored in the ferroelectric capacitor 61 shown in FIG. 1 (polarization Z1 in FIG. 3), and storage data “0” is stored in the ferroelectric capacitor 62 (FIG. 3). Polarization Z of 3
2).

When reading data from the ferroelectric capacitors 61 and 62, the control unit (not shown) controls the word line WL.
(Timing T2 in FIG. 2), and switches 63 and 64 in FIG. 1 are closed. Then, the control unit sets the plate line PL to H (timing T4 to T6).

By setting the plate line PL to H, charges are discharged from the ferroelectric capacitors 61 and 62 toward the bit lines BL1 and BL2, and a current flows. The amount of the discharged electric charge depends on the ferroelectric capacitor 6
It differs depending on the polarization states of the first and second polarizations. That is, a relatively large amount of charge is released from the ferroelectric capacitor 61,
Relatively little charge is released from the ferroelectric capacitor 62.

At timing T8 in FIG. 5, the control section outputs a sense amplifier signal. A signal is output from the AND circuit 21 in FIG. 1 based on the sense amplifier signal, and the switches 11 and 12 in the sense amplifier 2 are closed. As a result, the inverting circuits 23 and 24 connect the bit lines BL1 and BL
Bit line B according to the charge released toward
The voltages of L1 and BL2 are amplified and distributed to H and L.

In this case, since the bit line BL1 goes high and the bit line BL2 goes low as shown in FIG. 2, the storage data "1" is stored in the ferroelectric capacitor 61 and the ferroelectric capacitor It can be seen that the storage data “0” is stored in 62.

Since the storage data of the ferroelectric capacitor 61 whose polarization state has been inverted at the time of reading is destroyed, the storage data is rewritten immediately after reading, that is, the polarization state is inverted again. It is necessary to return to the state. When the sense amplifier is turned on at the timing T8 in FIG. 2, the plate line PL is at L level.
Here, the polarization state of 1 is inverted again, and returns to the original polarization state (rewrite).

In this embodiment, the ferroelectric capacitor 62
In order to suppress the occurrence of the imprint effect, the processes at timings T12, T13, and T14 are performed. The timings T12, T13, and T14 in the present embodiment are additional processing. Note that, in the present embodiment, the timing T for performing reading and rewriting of storage data is set.
4, T6 and T8 are read processing.

First, at the timing T12, the plate line PL is set to H, and the control section supplies a switching signal to the sense amplifier 2. By this switching signal, FIG.
The switches 11 and 12 shown in FIG.
Closes. As a result, the bit line BL1 becomes L and the bit line BL2 becomes H as shown in FIG.
In this case, the plate line PL is H and the bit line B
Since L1 is L, the polarization state of the ferroelectric capacitor 61 is inverted again.

Thereafter, at timing T14, the control unit changes the plate line PL to L. Plate line PL is L,
Since the bit line BL2 is H, the polarization state of the ferroelectric capacitor 62 is inverted here. Then, at timing T16, the switching signal is set to L. As a result, the bit line BL1 returns to H and the bit line BL2 returns to L.

Since the plate line PL is set to H at the timing T16, the polarization state of the ferroelectric capacitor 62 is inverted again. Subsequently, at a timing T18, the plate line PL is set to L, and the polarization state of the ferroelectric capacitor 61 is inverted again. Then, at timing T20, the word line W is set to L, and the switches 63 and 64 in FIG. 1 are opened.

The ferroelectric capacitors 61 and 62 described above
Will be described based on the hysteresis characteristics of FIG. First, the ferroelectric capacitor 6
Regarding 1, the polarization state shifts from P1 to P2 in FIG. 3 from timing T4 to T6 (FIG. 2), and the polarization state reaches P4 at timing T8 when rewriting is performed.

Then, at timing T12, the polarization state of the ferroelectric capacitor 61 changes from P4 through P1 to P2 again.
And reaches P3 at timing T14. After that, the processing shifts to P4 at timing T18, and P4 at timing T20.
Return to 1.

Next, the polarization state of the ferroelectric capacitor 62 will be described based on the hysteresis characteristics shown in FIG. From timing T4 to T6 (FIG. 2), the polarization state changes to P in FIG.
From 3, the state shifts slightly toward P2 along the broken line, and the polarization state returns to P3 at timing T8 (FIG. 2).

Then, the polarization state of the ferroelectric capacitor 62 reaches P4 from P3 at timing T14, and reaches P2 via P1 at timing T16. Thereafter, the process returns to P3 at timing T18.

As described above, in the present embodiment, the polarization state of the ferroelectric capacitor 61 makes the hysteresis characteristic at least one round (two rounds in the present embodiment),
The polarization state of the ferroelectric capacitor 62 also has a hysteresis characteristic of at least one round (one round in the present embodiment).

For this reason, the risk that the polarization state of the ferroelectric capacitor 62 is maintained for a long time can be reduced, and the occurrence of the imprint effect due to the habit of the polarization state of the ferroelectric capacitor 62 can be reliably suppressed. can do. Further, once the polarization state of the ferroelectric capacitor 62 is
Since it is only necessary to return to the original polarization state after the inversion, the occurrence of the imprint effect can be easily suppressed.

Further, the polarization state of the ferroelectric capacitor 62 is inverted in conjunction with the conventional reading and rewriting of the stored data, and only the inversion processing is performed independently of the reading and rewriting. Since it is not performed, the control of the process is easy and efficient.

In the present embodiment, a two-transistor, two-capacitor type ferroelectric memory has been described as an example. However, the present invention can be applied to other types of semiconductor memories, for example, a one-transistor, one-capacitor type ferroelectric memory. . Further, in the present embodiment, a ferroelectric memory has been illustrated, but the present invention can be applied to, for example, a ferroelectric transistor. Further, the present invention can be applied to other semiconductor memories that do not use a ferroelectric.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of ferroelectric capacitors 61 and 62, a sense amplifier 2, and the like.

FIG. 2 is a timing chart when reading stored data stored in ferroelectric capacitors 61 and 62.

FIG. 3 is a diagram showing a hysteresis characteristic representing a relationship between a voltage and a polarization state regarding a ferroelectric capacitor.

FIG. 4 is a circuit diagram of a ferroelectric capacitor.

FIG. 5 is a conventional timing chart when reading stored data stored in ferroelectric capacitors 61 and 62.

[Explanation of symbols]

 2 ····· Sense amplifiers 11, 12, 13, 14 ··· Switches 21 and 22 ··· AND circuits 23 and 24 ··· Inverting circuits 61 and 62 ··· Dielectric capacitor

Claims (7)

[Claims] 1. By maintaining a first state corresponding to first data or a second state corresponding to second data,
In the semiconductor memory device storing the first data or the second data, when storing or reading out the first data, the first state is once inverted to the second state, and then returned to the first state; 2. When storing or reading data, the semiconductor memory device inverts the second state once to the first state and then returns to the second state. 2. A method according to claim 1, wherein the first state corresponding to the first data or the second state corresponding to the second data is held.
In a semiconductor memory device for storing first data or second data, when storing or reading at least the first data, the first state is temporarily inverted to the second state as ancillary processing separately from the storage processing or the reading processing After returning to the first state, the semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein the first state is a first polarization state in which the polarizable region is polarized, and the second state is that the polarizable region is the first polarization state. A second polarization state polarized in a direction opposite to the state. 4. Polarizing the polarizable region to a first polarization state,
Alternatively, the first polarization state is polarized to a second polarization state opposite to the first polarization state, so that the first data corresponding to the first polarization state or the second data corresponding to the second polarization state is stored. As a read process, the second polarization state is changed to the first polarization state.
In a semiconductor memory device for inverting the polarization state to read the second data and reading the second data, and then returning the first polarization state to the second polarization state, at least storing or reading the first data Alternatively, separately from the read processing, the first state is once inverted to the second state and then returned to the first state as ancillary processing. 5. The semiconductor device according to claim 3, wherein the separable region is a ferroelectric material. 6. By holding a first state corresponding to the first data or a second state corresponding to the second data,
In the method for accessing a semiconductor memory device for storing first data or second data, when storing or reading the first data, the first state is once inverted to the second state, and then returned to the first state; When storing or reading the second data, the method inverts the second state to the first state, and then returns to the second state. 7. Holding a first state corresponding to the first data or a second state corresponding to the second data,
In the method of accessing a semiconductor memory device for storing first data or second data, when storing or reading at least the first data, the first state is temporarily stored in the second state as ancillary processing separately from the storage processing or the reading processing. A method for accessing a semiconductor memory device, comprising: inverting a state; and then returning to a first state.