FR3048548B1 - Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant - Google Patents

Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant Download PDF

Info

Publication number
FR3048548B1
FR3048548B1 FR1651747A FR1651747A FR3048548B1 FR 3048548 B1 FR3048548 B1 FR 3048548B1 FR 1651747 A FR1651747 A FR 1651747A FR 1651747 A FR1651747 A FR 1651747A FR 3048548 B1 FR3048548 B1 FR 3048548B1
Authority
FR
France
Prior art keywords
substrate
donor substrate
implantation
insulation
type structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1651747A
Other languages
English (en)
Other versions
FR3048548A1 (fr
Inventor
Ludovic Ecarnot
Nadia Ben Mohamed
Carine Duret
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1651747A priority Critical patent/FR3048548B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to CN201780014686.1A priority patent/CN108701627B/zh
Priority to JP2018545988A priority patent/JP6965260B2/ja
Priority to US16/081,816 priority patent/US10777447B2/en
Priority to TW106106821A priority patent/TWI724114B/zh
Priority to PCT/FR2017/050471 priority patent/WO2017149253A1/fr
Priority to SG11201807344RA priority patent/SG11201807344RA/en
Publication of FR3048548A1 publication Critical patent/FR3048548A1/fr
Application granted granted Critical
Publication of FR3048548B1 publication Critical patent/FR3048548B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Recrystallisation Techniques (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'invention concerne un procédé de détermination d'une énergie convenable d'implantation d'au moins deux espèces atomiques dans un substrat donneur (30) pour créer une zone de fragilisation (31) définissant une couche (32) monocristalline semi-conductrice à transférer sur un substrat receveur (10), comprenant les étapes suivantes : (i) formation d'une couche diélectrique sur le substrat donneur (30) et/ou du substrat receveur (10), (ii) co-implantation desdites espèces dans le substrat donneur (30), (iii) collage du substrat donneur (30) sur le substrat receveur (10), (iv) détachement du substrat donneur (30) le long de la zone de fragilisation (31) de sorte à transférer la couche (32) monocristalline semi-conductrice et récupérer un reliquat (34) du substrat donneur, (v) inspection de la couronne périphérique du reliquat (34) du substrat donneur ou du substrat receveur (10) sur lequel la couche monocristalline semi-conductrice (32) a été transférée à l'étape (iv), (vi) si ladite couronne présente des zones transférées sur le substrat receveur, détermination du fait que l'énergie d'implantation de l'étape (ii) est trop élevée, (vii) si ladite couronne ne présente pas de zones transférées sur le substrat receveur, détermination du fait que l'énergie d'implantation de l'étape (ii) est convenable.
FR1651747A 2016-03-02 2016-03-02 Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant Active FR3048548B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR1651747A FR3048548B1 (fr) 2016-03-02 2016-03-02 Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant
JP2018545988A JP6965260B2 (ja) 2016-03-02 2017-03-02 ドナー基板への注入のための適切なエネルギーの決定方法、およびセミコンダクタ・オン・インシュレータ（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ−ｏｎ−ｉｎｓｕｌａｔｏｒ）構造体の組立方法
US16/081,816 US10777447B2 (en) 2016-03-02 2017-03-02 Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor-on-insulator type
TW106106821A TWI724114B (zh) 2016-03-02 2017-03-02 用於決定供體基材中適當佈植能量的方法及半導體覆絕緣體型結構的製造方法
CN201780014686.1A CN108701627B (zh) 2016-03-02 2017-03-02 用于确定供体基板中的合适注入能量的方法和用于制造绝缘体上半导体结构的工艺
PCT/FR2017/050471 WO2017149253A1 (fr) 2016-03-02 2017-03-02 Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant
SG11201807344RA SG11201807344RA (en) 2016-03-02 2017-03-02 Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor–on–insulator type

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1651747 2016-03-02
FR1651747A FR3048548B1 (fr) 2016-03-02 2016-03-02 Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant

Publications (2)

Publication Number Publication Date
FR3048548A1 FR3048548A1 (fr) 2017-09-08
FR3048548B1 true FR3048548B1 (fr) 2018-03-02

Family

ID=56322049

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1651747A Active FR3048548B1 (fr) 2016-03-02 2016-03-02 Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant

Country Status (7)

Country Link
US (1) US10777447B2 (fr)
JP (1) JP6965260B2 (fr)
CN (1) CN108701627B (fr)
FR (1) FR3048548B1 (fr)
SG (1) SG11201807344RA (fr)
TW (1) TWI724114B (fr)
WO (1) WO2017149253A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016081367A1 (fr) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited Substrat de silicium sur isolant de grande résistivité comprenant une couche de piégeage de charge formée par co-implantation he-n2
EP3378094B1 (fr) 2015-11-20 2021-09-15 Globalwafers Co., Ltd. Procédé de fabrication consistant à lisser une surface de semi-conducteur
FR3063176A1 (fr) * 2017-02-17 2018-08-24 Soitec Masquage d'une zone au bord d'un substrat donneur lors d'une etape d'implantation ionique
CN112262467B (zh) 2018-06-08 2024-08-09 环球晶圆股份有限公司 将硅薄层移转的方法
FR3091620B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
FR2835097B1 (fr) * 2002-01-23 2005-10-14 Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil
EP1427001A1 (fr) * 2002-12-06 2004-06-09 S.O.I. Tec Silicon on Insulator Technologies S.A. Méthode de recyclage d'une surface d'un substrat par amincissement localisé
JP4492054B2 (ja) * 2003-08-28 2010-06-30 株式会社Ｓｕｍｃｏ 剥離ウェーハの再生処理方法及び再生されたウェーハ
CN101027768B (zh) * 2004-09-21 2010-11-03 S.O.I.Tec绝缘体上硅技术公司 根据避免气泡形成和限制粗糙度的条件来进行共注入步骤的薄层转移方法
FR2880988B1 (fr) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
EP1777735A3 (fr) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Procédé de recyclage d'une plaquette donneuse épitaxiée
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
US7575988B2 (en) * 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate
JP5155536B2 (ja) * 2006-07-28 2013-03-06 一般財団法人電力中央研究所 ＳｉＣ結晶の質を向上させる方法およびＳｉＣ半導体素子の製造方法
EP2015354A1 (fr) * 2007-07-11 2009-01-14 S.O.I.Tec Silicon on Insulator Technologies Procédé pour le recyclage d'un substrat, procédé de fabrication de tranches stratifiées et substrat donneur recyclé approprié
FR2920912B1 (fr) * 2007-09-12 2010-08-27 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure par transfert de couche
FR2926672B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie
FR2971365B1 (fr) * 2011-02-08 2013-02-22 Soitec Silicon On Insulator Méthode de recyclage d'un substrat source

Also Published As

Publication number Publication date
TW201735124A (zh) 2017-10-01
JP6965260B2 (ja) 2021-11-10
WO2017149253A1 (fr) 2017-09-08
FR3048548A1 (fr) 2017-09-08
US10777447B2 (en) 2020-09-15
TWI724114B (zh) 2021-04-11
JP2019511112A (ja) 2019-04-18
US20190074215A1 (en) 2019-03-07
CN108701627A (zh) 2018-10-23
CN108701627B (zh) 2023-08-15
SG11201807344RA (en) 2018-09-27

Similar Documents

Publication Publication Date Title
FR3048548B1 (fr) Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant
US8048775B2 (en) Process of forming ultra thin wafers having an edge support ring
KR101160316B1 (ko) 점진적인 트리밍 방법
TWI264772B (en) Manufacturing method of semiconductor wafer and wafer
WO2009153422A8 (fr) Traitement de surface par plasma d'azote dans un procédé de collage direct
RU2018113434A (ru) Способ изготовления составной подложки из sic
JP6511516B2 (ja) ゲルマニウム・オン・インシュレータ基板の製造方法
CN103258778B (zh) 带有空腔的衬底的制备方法
SG166738A1 (en) Method for manufacturing soi substrate and soi substrate
US11177155B2 (en) Direct bond method providing thermal expansion matched devices
FR3103962B1 (fr) Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic cristallin
FR2977069A1 (fr) Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
Jourdain et al. Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications
CN114300344A (zh) 一种利用载盘进行SiC晶圆加工的工艺
US20160218178A1 (en) Process for assembling two wafers and corresponding device
FR3099637B1 (fr) procédé de fabrication d’unE structure composite comprenant une couche mince en Sic monocristallin sur un substrat support en sic polycristallin
US9721907B2 (en) Wafer edge shape for thin wafer processing
WO2016196216A8 (fr) Procédés pour le traitement de plaquettes à semi-conducteurs ayant une finition polycristalline
WO2015074480A1 (fr) Procédé de préparation de substrat semi-conducteur à bords lisses
FR3104322B1 (fr) Procédé de formation d'un substrat de manipulation pour une structure composite ciblant des applications rf
FR3085538B1 (fr) Tranche soi et son procede de production
JP2017139266A (ja) 複合基板、半導体装置、およびこれらの製造方法
FR3127843B1 (fr) ProcÉdÉ de transfert d’une couche de SiC monocristallin sur un support en SiC polycristallin utilisant une couche intermÉdiaire de SiC polycristallin
US20150243548A1 (en) Control of FET Back-Channel Interface Characteristics
CN110459501A (zh) 一种用于减薄圆片的加固拿持结构及其制备方法

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20170908

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 9