FR2920912B1 - Procede de fabrication d'une structure par transfert de couche - Google Patents
Procede de fabrication d'une structure par transfert de coucheInfo
- Publication number
- FR2920912B1 FR2920912B1 FR0757511A FR0757511A FR2920912B1 FR 2920912 B1 FR2920912 B1 FR 2920912B1 FR 0757511 A FR0757511 A FR 0757511A FR 0757511 A FR0757511 A FR 0757511A FR 2920912 B1 FR2920912 B1 FR 2920912B1
- Authority
- FR
- France
- Prior art keywords
- substrate
- donor substrate
- recipient
- manufacturing
- increase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 13
- 230000003313 weakening effect Effects 0.000 abstract 2
- 241000700159 Rattus Species 0.000 abstract 1
- 230000010070 molecular adhesion Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
La présente invention concerne un procédé de fabrication d'une structure semiconductrice par transfert d'une couche (32) d'un substrat donneur (30) vers un substrat receveur (10), comprenant les étapes de :(a) création d'une zone de fragilisation (31) dans le substrat donneur (30) de manière à définir la couche (32),(b) traitement de la surface du substrat donneur (30) et/ou du substrat receveur (10), de manière à augmenter l'énergie de collage entre les deux substrats(c) collage par adhésion moléculaire du substrat donneur (30) sur le substrat receveur (10)(d) détachement du substrat donneur (30) selon la zone de fragilisation (31).Ce procédé est remarquable en ce que lors de l'étape (b), on contrôle le traitement de la surface du substrat de telle sorte que l'augmentation de l'énergie de collage entre le substrat donneur et le substrat receveur est, dans une région périphérique de ces substrats, inférieure à l'augmentation de l'énergie de collage dans la région centrale desdits substrats.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0757511A FR2920912B1 (fr) | 2007-09-12 | 2007-09-12 | Procede de fabrication d'une structure par transfert de couche |
EP08803985A EP2195836A1 (fr) | 2007-09-12 | 2008-09-11 | Procédé de production de structure par transfert de couche |
CN2008801062027A CN101803002B (zh) | 2007-09-12 | 2008-09-11 | 通过层转移制造结构的方法 |
KR1020107007669A KR101172585B1 (ko) | 2007-09-12 | 2008-09-11 | 층 전사에 의한 구조체 제조 방법 |
PCT/EP2008/062018 WO2009034113A1 (fr) | 2007-09-12 | 2008-09-11 | Procédé de production de structure par transfert de couche |
JP2010524479A JP5231555B2 (ja) | 2007-09-12 | 2008-09-11 | 層転写により構造を製造する方法 |
US12/675,927 US8420500B2 (en) | 2007-09-12 | 2008-09-11 | Method of producing a structure by layer transfer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0757511A FR2920912B1 (fr) | 2007-09-12 | 2007-09-12 | Procede de fabrication d'une structure par transfert de couche |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2920912A1 FR2920912A1 (fr) | 2009-03-13 |
FR2920912B1 true FR2920912B1 (fr) | 2010-08-27 |
Family
ID=39092009
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0757511A Active FR2920912B1 (fr) | 2007-09-12 | 2007-09-12 | Procede de fabrication d'une structure par transfert de couche |
Country Status (7)
Country | Link |
---|---|
US (1) | US8420500B2 (fr) |
EP (1) | EP2195836A1 (fr) |
JP (1) | JP5231555B2 (fr) |
KR (1) | KR101172585B1 (fr) |
CN (1) | CN101803002B (fr) |
FR (1) | FR2920912B1 (fr) |
WO (1) | WO2009034113A1 (fr) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5478166B2 (ja) * | 2008-09-11 | 2014-04-23 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US8852391B2 (en) * | 2010-06-21 | 2014-10-07 | Brewer Science Inc. | Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate |
JP5859742B2 (ja) * | 2011-04-28 | 2016-02-16 | 京セラ株式会社 | 複合基板 |
JP5976999B2 (ja) * | 2011-05-30 | 2016-08-24 | 京セラ株式会社 | 複合基板 |
US8709914B2 (en) * | 2011-06-14 | 2014-04-29 | International Business Machines Corporation | Method for controlled layer transfer |
FR3032555B1 (fr) * | 2015-02-10 | 2018-01-19 | Soitec | Procede de report d'une couche utile |
FR3048548B1 (fr) | 2016-03-02 | 2018-03-02 | Soitec | Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant |
US10504716B2 (en) * | 2018-03-15 | 2019-12-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for manufacturing semiconductor device and manufacturing method of the same |
JP6705472B2 (ja) | 2018-06-18 | 2020-06-03 | Tdk株式会社 | 非可逆回路素子及びこれを用いた通信装置 |
CN110183221B (zh) * | 2019-05-05 | 2021-11-30 | 南京中电熊猫磁电科技有限公司 | 超低温度磁导率稳定性的锰锌软磁铁氧体材料的制备方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2058132T3 (es) * | 1986-12-19 | 1994-11-01 | Applied Materials Inc | Reactor para ataque en plasma intensificado por un campo magnetico. |
US5298465A (en) * | 1990-08-16 | 1994-03-29 | Applied Materials, Inc. | Plasma etching system |
US5423918A (en) * | 1993-09-21 | 1995-06-13 | Applied Materials, Inc. | Method for reducing particulate contamination during plasma processing of semiconductor devices |
JP3294934B2 (ja) | 1994-03-11 | 2002-06-24 | キヤノン株式会社 | 半導体基板の作製方法及び半導体基板 |
FR2842649B1 (fr) * | 2002-07-17 | 2005-06-24 | Soitec Silicon On Insulator | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
JP3996557B2 (ja) * | 2003-07-09 | 2007-10-24 | 直江津電子工業株式会社 | 半導体接合ウエーハの製造方法 |
JP2005347302A (ja) * | 2004-05-31 | 2005-12-15 | Canon Inc | 基板の製造方法 |
KR100539266B1 (ko) * | 2004-06-02 | 2005-12-27 | 삼성전자주식회사 | 호 절편 형태의 한정부를 가지는 플라즈마 공정 장비 |
KR100553713B1 (ko) * | 2004-06-03 | 2006-02-24 | 삼성전자주식회사 | 플라즈마 식각 장치 및 이 장치를 이용한 포토 마스크의제조 방법 |
JP4520820B2 (ja) * | 2004-10-27 | 2010-08-11 | 株式会社日立ハイテクノロジーズ | 試料処理装置及び試料処理システム |
US7919391B2 (en) * | 2004-12-24 | 2011-04-05 | S.O.I.Tec Silicon On Insulator Technologies | Methods for preparing a bonding surface of a semiconductor wafer |
KR101174871B1 (ko) * | 2005-06-18 | 2012-08-17 | 삼성디스플레이 주식회사 | 유기 반도체의 패터닝 방법 |
US7601271B2 (en) * | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
US7781309B2 (en) * | 2005-12-22 | 2010-08-24 | Sumco Corporation | Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method |
JP2007251080A (ja) * | 2006-03-20 | 2007-09-27 | Fujifilm Corp | プラスチック基板の固定方法、回路基板およびその製造方法 |
-
2007
- 2007-09-12 FR FR0757511A patent/FR2920912B1/fr active Active
-
2008
- 2008-09-11 JP JP2010524479A patent/JP5231555B2/ja active Active
- 2008-09-11 US US12/675,927 patent/US8420500B2/en active Active
- 2008-09-11 CN CN2008801062027A patent/CN101803002B/zh active Active
- 2008-09-11 EP EP08803985A patent/EP2195836A1/fr not_active Withdrawn
- 2008-09-11 WO PCT/EP2008/062018 patent/WO2009034113A1/fr active Application Filing
- 2008-09-11 KR KR1020107007669A patent/KR101172585B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP5231555B2 (ja) | 2013-07-10 |
CN101803002B (zh) | 2013-01-09 |
US8420500B2 (en) | 2013-04-16 |
KR101172585B1 (ko) | 2012-08-08 |
CN101803002A (zh) | 2010-08-11 |
FR2920912A1 (fr) | 2009-03-13 |
JP2010539696A (ja) | 2010-12-16 |
WO2009034113A1 (fr) | 2009-03-19 |
EP2195836A1 (fr) | 2010-06-16 |
KR20100068424A (ko) | 2010-06-23 |
US20100304507A1 (en) | 2010-12-02 |
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Legal Events
Date | Code | Title | Description |
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CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
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Year of fee payment: 10 |
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