FR2989516B1 - Procede de fabrication d'une structure soi mettant en oeuvre deux rta - Google Patents

Procede de fabrication d'une structure soi mettant en oeuvre deux rta

Info

Publication number
FR2989516B1
FR2989516B1 FR1253318A FR1253318A FR2989516B1 FR 2989516 B1 FR2989516 B1 FR 2989516B1 FR 1253318 A FR1253318 A FR 1253318A FR 1253318 A FR1253318 A FR 1253318A FR 2989516 B1 FR2989516 B1 FR 2989516B1
Authority
FR
France
Prior art keywords
tws
atr
manufacturing
sel structure
sel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1253318A
Other languages
English (en)
Other versions
FR2989516A1 (fr
Inventor
Sebastien Kerdiles
Carole David
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1253318A priority Critical patent/FR2989516B1/fr
Priority to US13/827,618 priority patent/US8691662B2/en
Publication of FR2989516A1 publication Critical patent/FR2989516A1/fr
Application granted granted Critical
Publication of FR2989516B1 publication Critical patent/FR2989516B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
FR1253318A 2012-04-11 2012-04-11 Procede de fabrication d'une structure soi mettant en oeuvre deux rta Active FR2989516B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1253318A FR2989516B1 (fr) 2012-04-11 2012-04-11 Procede de fabrication d'une structure soi mettant en oeuvre deux rta
US13/827,618 US8691662B2 (en) 2012-04-11 2013-03-14 Process for fabricating a silicon-on-insulator structure employing two rapid thermal annealing processes, and related structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1253318A FR2989516B1 (fr) 2012-04-11 2012-04-11 Procede de fabrication d'une structure soi mettant en oeuvre deux rta

Publications (2)

Publication Number Publication Date
FR2989516A1 FR2989516A1 (fr) 2013-10-18
FR2989516B1 true FR2989516B1 (fr) 2014-04-18

Family

ID=46197542

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1253318A Active FR2989516B1 (fr) 2012-04-11 2012-04-11 Procede de fabrication d'une structure soi mettant en oeuvre deux rta

Country Status (2)

Country Link
US (1) US8691662B2 (fr)
FR (1) FR2989516B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110400773B (zh) * 2018-04-24 2022-06-07 沈阳硅基科技有限公司 一种采用快速热处理工艺制备soi硅片的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2896619B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees
FR2903809B1 (fr) * 2006-07-13 2008-10-17 Soitec Silicon On Insulator Traitement thermique de stabilisation d'interface e collage.
FR2938118B1 (fr) 2008-10-30 2011-04-22 Soitec Silicon On Insulator Procede de fabrication d'un empilement de couches minces semi-conductrices

Also Published As

Publication number Publication date
US8691662B2 (en) 2014-04-08
US20130273712A1 (en) 2013-10-17
FR2989516A1 (fr) 2013-10-18

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