FR3027451B1 - Substrat et procede de fabrication d'un substrat - Google Patents
Substrat et procede de fabrication d'un substratInfo
- Publication number
- FR3027451B1 FR3027451B1 FR1460110A FR1460110A FR3027451B1 FR 3027451 B1 FR3027451 B1 FR 3027451B1 FR 1460110 A FR1460110 A FR 1460110A FR 1460110 A FR1460110 A FR 1460110A FR 3027451 B1 FR3027451 B1 FR 3027451B1
- Authority
- FR
- France
- Prior art keywords
- substrate
- manufacturing
- manufacturing substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1460110A FR3027451B1 (fr) | 2014-10-21 | 2014-10-21 | Substrat et procede de fabrication d'un substrat |
PCT/EP2015/074181 WO2016062674A1 (fr) | 2014-10-21 | 2015-10-19 | Substrat et procédé de production d'un substrat |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1460110A FR3027451B1 (fr) | 2014-10-21 | 2014-10-21 | Substrat et procede de fabrication d'un substrat |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3027451A1 FR3027451A1 (fr) | 2016-04-22 |
FR3027451B1 true FR3027451B1 (fr) | 2016-11-04 |
Family
ID=52007194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1460110A Active FR3027451B1 (fr) | 2014-10-21 | 2014-10-21 | Substrat et procede de fabrication d'un substrat |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR3027451B1 (fr) |
WO (1) | WO2016062674A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110085550A (zh) * | 2018-01-26 | 2019-08-02 | 沈阳硅基科技有限公司 | 一种半导体产品用绝缘层结构及其制备方法 |
FR3085536A1 (fr) * | 2018-09-03 | 2020-03-06 | Soitec | Dispositif cfet et procede de fabrication d'un tel dispositif |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1858071A1 (fr) * | 2006-05-18 | 2007-11-21 | S.O.I.TEC. Silicon on Insulator Technologies S.A. | Procédé de fabrication d'une plaquette de type semi-conducteur sur isolant, et plaquette de type semi-conducteur sur isolant |
EP2095415B1 (fr) * | 2006-12-26 | 2010-10-27 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de production d'une structure semiconducteur sur isolant |
FR2953640B1 (fr) * | 2009-12-04 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante |
-
2014
- 2014-10-21 FR FR1460110A patent/FR3027451B1/fr active Active
-
2015
- 2015-10-19 WO PCT/EP2015/074181 patent/WO2016062674A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2016062674A1 (fr) | 2016-04-28 |
FR3027451A1 (fr) | 2016-04-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20160422 |
|
PLFP | Fee payment |
Year of fee payment: 3 |
|
PLFP | Fee payment |
Year of fee payment: 4 |