FR2871172B1 - Support d'epitaxie hybride et son procede de fabrication - Google Patents

Support d'epitaxie hybride et son procede de fabrication

Info

Publication number
FR2871172B1
FR2871172B1 FR0405992A FR0405992A FR2871172B1 FR 2871172 B1 FR2871172 B1 FR 2871172B1 FR 0405992 A FR0405992 A FR 0405992A FR 0405992 A FR0405992 A FR 0405992A FR 2871172 B1 FR2871172 B1 FR 2871172B1
Authority
FR
France
Prior art keywords
epitaxis
hybrid
manufacturing
support
same
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0405992A
Other languages
English (en)
Other versions
FR2871172A1 (fr
Inventor
Bruce Faure
Hacene Lahreche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0405992A priority Critical patent/FR2871172B1/fr
Priority to US10/915,765 priority patent/US20050269671A1/en
Priority to JP2007514028A priority patent/JP2008501229A/ja
Priority to PCT/FR2005/001353 priority patent/WO2006000691A1/fr
Priority to EP05775231A priority patent/EP1766676A1/fr
Priority to CNA2005800235453A priority patent/CN1985368A/zh
Priority to TW094118461A priority patent/TW200614377A/zh
Publication of FR2871172A1 publication Critical patent/FR2871172A1/fr
Application granted granted Critical
Publication of FR2871172B1 publication Critical patent/FR2871172B1/fr
Priority to US11/541,192 priority patent/US9011598B2/en
Priority to PCT/EP2006/070107 priority patent/WO2007071771A1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
FR0405992A 2004-06-03 2004-06-03 Support d'epitaxie hybride et son procede de fabrication Expired - Fee Related FR2871172B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR0405992A FR2871172B1 (fr) 2004-06-03 2004-06-03 Support d'epitaxie hybride et son procede de fabrication
US10/915,765 US20050269671A1 (en) 2004-06-03 2004-08-10 Support for hybrid epitaxy and method of fabrication
PCT/FR2005/001353 WO2006000691A1 (fr) 2004-06-03 2005-06-02 Support d'epitaxie hybride et son procede de fabrication
EP05775231A EP1766676A1 (fr) 2004-06-03 2005-06-02 Support d'epitaxie hybride et son procede de fabrication
JP2007514028A JP2008501229A (ja) 2004-06-03 2005-06-02 ハイブリッドエピタキシー用支持体およびその製造方法
CNA2005800235453A CN1985368A (zh) 2004-06-03 2005-06-02 混合外延支撑件及其制作方法
TW094118461A TW200614377A (en) 2004-06-03 2005-06-03 A support for hybrid epitaxy, and a method of fabricating it
US11/541,192 US9011598B2 (en) 2004-06-03 2006-09-28 Method for making a composite substrate and composite substrate according to the method
PCT/EP2006/070107 WO2007071771A1 (fr) 2004-06-03 2006-12-21 Procede de fabrication d'un substrat composite et substrat composite obtenu par ce procede

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0405992A FR2871172B1 (fr) 2004-06-03 2004-06-03 Support d'epitaxie hybride et son procede de fabrication

Publications (2)

Publication Number Publication Date
FR2871172A1 FR2871172A1 (fr) 2005-12-09
FR2871172B1 true FR2871172B1 (fr) 2006-09-22

Family

ID=34946854

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0405992A Expired - Fee Related FR2871172B1 (fr) 2004-06-03 2004-06-03 Support d'epitaxie hybride et son procede de fabrication

Country Status (7)

Country Link
US (1) US20050269671A1 (fr)
EP (1) EP1766676A1 (fr)
JP (1) JP2008501229A (fr)
CN (1) CN1985368A (fr)
FR (1) FR2871172B1 (fr)
TW (1) TW200614377A (fr)
WO (1) WO2006000691A1 (fr)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US9011598B2 (en) 2004-06-03 2015-04-21 Soitec Method for making a composite substrate and composite substrate according to the method
US7772601B2 (en) * 2005-02-04 2010-08-10 Seoul Opto Device Co., Ltd. Light emitting device having a plurality of light emitting cells and method of fabricating the same
US7491615B2 (en) * 2005-09-23 2009-02-17 United Microelectronics Corp. Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors
WO2007074551A1 (fr) * 2005-12-27 2007-07-05 Shin-Etsu Chemical Co., Ltd. Procede de production de tranches soi et tranches soi ainsi produites
FR2896618B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
TW200802544A (en) * 2006-04-25 2008-01-01 Osram Opto Semiconductors Gmbh Composite substrate and method for making the same
FR2903808B1 (fr) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
EP2128891B1 (fr) * 2007-02-28 2015-09-02 Shin-Etsu Chemical Co., Ltd. Procédé de fabrication d'un substrat laminé
FR2913528B1 (fr) * 2007-03-06 2009-07-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche d'oxyde enterree pour la realisation de composants electroniques ou analogues.
US20090115052A1 (en) * 2007-05-25 2009-05-07 Astralux, Inc. Hybrid silicon/non-silicon electronic device with heat spreader
US7696058B2 (en) * 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5459900B2 (ja) * 2007-12-25 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8679942B2 (en) 2008-11-26 2014-03-25 Soitec Strain engineered composite semiconductor substrates and methods of forming same
SG171714A1 (en) * 2008-12-19 2011-07-28 Soitec Silicon On Insulator Strain engineered composite semiconductor substrates and methods of forming same
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
JP2011077102A (ja) * 2009-09-29 2011-04-14 Toyoda Gosei Co Ltd ウエハ、ｉｉｉ族窒化物系化合物半導体素子、及びそれらの製造方法
CN102055053B (zh) * 2009-11-04 2013-09-04 中国科学院半导体研究所 一种基于键合技术制作微波传输线的方法
FR2953640B1 (fr) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
US8187901B2 (en) 2009-12-07 2012-05-29 Micron Technology, Inc. Epitaxial formation support structures and associated methods
EP2532773A4 (fr) * 2010-02-05 2013-12-11 Sumitomo Electric Industries Procédé de production de substrat en carbure de silicium
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
JP2012054451A (ja) * 2010-09-02 2012-03-15 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法および半導体基板洗浄液
FR2967812B1 (fr) * 2010-11-19 2016-06-10 S O I Tec Silicon On Insulator Tech Dispositif electronique pour applications radiofrequence ou de puissance et procede de fabrication d'un tel dispositif
US9257339B2 (en) * 2012-05-04 2016-02-09 Silicon Genesis Corporation Techniques for forming optoelectronic devices
JP5876386B2 (ja) * 2012-07-19 2016-03-02 日本電信電話株式会社 窒化物半導体装置の製造方法
CN102945795B (zh) * 2012-11-09 2015-09-30 湖南红太阳光电科技有限公司 一种宽禁带半导体柔性衬底的制备方法
CN103904001B (zh) * 2014-03-20 2017-01-04 上海华力微电子有限公司 一种用于氮掺杂碳化硅薄膜的离线监控方法
US10355203B2 (en) * 2016-03-14 2019-07-16 Toshiba Memory Corporation Semiconductor memory device with variable resistance elements
KR102403038B1 (ko) * 2016-08-23 2022-05-27 큐로미스, 인크 가공된 기판과 통합된 전자 전력 디바이스
KR102404060B1 (ko) * 2018-01-11 2022-06-02 삼성전자주식회사 캐패시터를 갖는 반도체 소자 및 그 형성 방법
CN109273526A (zh) * 2018-10-24 2019-01-25 深圳市华讯方舟微电子科技有限公司 一种高性能晶体管及其制造方法
FR3114911B1 (fr) * 2020-10-06 2024-02-09 Soitec Silicon On Insulator Procédé de fabrication d’un substrat pour la croissance épitaxiale d’une couche d’un alliage III-N à base de gallium
FR3114910A1 (fr) * 2020-10-06 2022-04-08 Soitec Procédé de fabrication d’un substrat pour la croissance épitaxiale d’une couche d’un alliage III-N à base de gallium
CN113097124B (zh) * 2021-04-02 2023-12-05 中国科学院上海微系统与信息技术研究所 异质集成GaN薄膜及GaN器件的制备方法
CN113658849A (zh) * 2021-07-06 2021-11-16 华为技术有限公司 复合衬底及其制备方法、半导体器件、电子设备
CN115896947B (zh) * 2023-01-30 2023-05-16 北京大学 一种在陶瓷衬底上生长单晶iii族氮化物的方法
CN116598203A (zh) * 2023-06-20 2023-08-15 中国科学院上海微系统与信息技术研究所 一种氮化镓hemt器件及其制备方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6533874B1 (en) * 1996-12-03 2003-03-18 Advanced Technology Materials, Inc. GaN-based devices using thick (Ga, Al, In)N base layers
JPH10297996A (ja) * 1997-04-26 1998-11-10 Ion Kogaku Kenkyusho:Kk 炭化珪素薄膜の形成方法
JP2961522B2 (ja) * 1997-06-11 1999-10-12 日本ピラー工業株式会社 半導体電子素子用基板およびその製造方法
FR2774214B1 (fr) * 1998-01-28 2002-02-08 Commissariat Energie Atomique PROCEDE DE REALISATION D'UNE STRUCTURE DE TYPE SEMI-CONDUCTEUR SUR ISOLANT ET EN PARTICULIER SiCOI
TW417315B (en) * 1998-06-18 2001-01-01 Sumitomo Electric Industries GaN single crystal substrate and its manufacture method of the same
JP3385972B2 (ja) * 1998-07-10 2003-03-10 信越半導体株式会社 貼り合わせウェーハの製造方法および貼り合わせウェーハ
US6328796B1 (en) * 1999-02-01 2001-12-11 The United States Of America As Represented By The Secretary Of The Navy Single-crystal material on non-single-crystalline substrate
JP2000226299A (ja) * 1999-02-04 2000-08-15 Denso Corp 単結晶炭化珪素薄膜の製造方法および単結晶炭化珪素薄膜
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
FR2840731B3 (fr) * 2002-06-11 2004-07-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
FR2840730B1 (fr) * 2002-06-11 2005-05-27 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees
FR2834123B1 (fr) * 2001-12-21 2005-02-04 Soitec Silicon On Insulator Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report
FR2835097B1 (fr) * 2002-01-23 2005-10-14 Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil
JP2004063730A (ja) * 2002-07-29 2004-02-26 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法

Also Published As

Publication number Publication date
US20050269671A1 (en) 2005-12-08
FR2871172A1 (fr) 2005-12-09
JP2008501229A (ja) 2008-01-17
TW200614377A (en) 2006-05-01
CN1985368A (zh) 2007-06-20
WO2006000691A1 (fr) 2006-01-05
EP1766676A1 (fr) 2007-03-28

Similar Documents

Publication Publication Date Title
FR2871172B1 (fr) Support d'epitaxie hybride et son procede de fabrication
FR2873492B1 (fr) Nanocomposite photoactif et son procede de fabrication
DE60324888D1 (de) und Herstellungsverfahren
FR2868003B1 (fr) Element de construction pour prototypage rapide et son procede de fabrication
FR2841631B1 (fr) Structure de raccord de tuyau et son procede de fabrication
DE60310339D1 (de) Querträger und Herstellungsverfahren
FR2857660B1 (fr) Structure composite thermostructurale a gradient de composition et son procede de fabrication
DE60319810D1 (de) Anschwemmfiltermedien und herstellungs- und verwendungsverfahren
FR2802707B1 (fr) Accumulateur au lithium et son procede de fabrication
FR2885995B1 (fr) Plaque vitroceramique et son procede de fabrication
DE602005025091D1 (de) Piezooszillator und herstellungsverfahren dafür
FR2838429B1 (fr) Plaque vitroceramique et son procede de fabrication
DE60218767D1 (de) Reissverschluss und Herstellungsverfahren
DE60239896D1 (de) Velourskunstleder und seine herstellung
FR2812362B1 (fr) Support antivibratoire hydraulique et son procede de fabrication
FR2837217B1 (fr) Revetement composite de mosi2-si3n4 et son procede de fabrication
FR2893423B1 (fr) Ebauche d'oculaire avec insert et son procede de fabrication
FR2836243B1 (fr) Ecran de retroprojection et son procede de fabrication
DE60322190D1 (de) Halbleiteranordnung und entsprechendes Herstellungsverfahren
FR2866531B1 (fr) Element tubulaire et son procede de fabrication
FR2789464B1 (fr) Support antivibratoire et son procede de fabrication
FR2872836B1 (fr) Geocomposite de drainage et son procede de fabrication
FR2851804B1 (fr) Bielle anti-vibratoire et son procede de fabrication
FR2883711B1 (fr) Piece d'ornement et son procede de fabrication
FR2852146B1 (fr) Imageur x a conversion directe et son procede de fabrication

Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090228