ATE518241T1 - Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer - Google Patents
Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender waferInfo
- Publication number
- ATE518241T1 ATE518241T1 AT07290094T AT07290094T ATE518241T1 AT E518241 T1 ATE518241 T1 AT E518241T1 AT 07290094 T AT07290094 T AT 07290094T AT 07290094 T AT07290094 T AT 07290094T AT E518241 T1 ATE518241 T1 AT E518241T1
- Authority
- AT
- Austria
- Prior art keywords
- donor substrate
- silicon
- insulator
- wafer
- initial donor
- Prior art date
Links
- 239000012212 insulator Substances 0.000 title abstract 4
- 229910052710 silicon Inorganic materials 0.000 title abstract 4
- 239000010703 silicon Substances 0.000 title abstract 4
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 9
- 235000012431 wafers Nutrition 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 2
- 238000007669 thermal treatment Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/8305—Miscellaneous [e.g., treated surfaces, etc.]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20070290094 EP1950803B1 (de) | 2007-01-24 | 2007-01-24 | Herstellungsverfahren für Wafer aus Silizium auf Isolator und entsprechender Wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE518241T1 true ATE518241T1 (de) | 2011-08-15 |
Family
ID=38157805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT07290094T ATE518241T1 (de) | 2007-01-24 | 2007-01-24 | Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer |
Country Status (7)
Country | Link |
---|---|
US (1) | US7736994B2 (de) |
EP (2) | EP2264755A3 (de) |
JP (1) | JP4817342B2 (de) |
KR (1) | KR101302426B1 (de) |
CN (1) | CN101558487B (de) |
AT (1) | ATE518241T1 (de) |
WO (1) | WO2008090439A1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8017429B2 (en) * | 2008-02-19 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing photoelectric conversion device |
CN102763225B (zh) | 2009-12-09 | 2016-01-20 | 速力斯公司 | 使用半导体晶片的高效率光伏背结背触点太阳能电池结构和制造方法 |
EP2601687A4 (de) | 2010-08-05 | 2018-03-07 | Solexel, Inc. | Rückseitenverstärkung und vernetzungsmittel für solarzellen |
FR2987166B1 (fr) | 2012-02-16 | 2017-05-12 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
KR20140140053A (ko) | 2012-02-26 | 2014-12-08 | 솔렉셀, 인크. | 레이저 분할 및 디바이스 층 전사를 위한 시스템 및 방법 |
FR2999801B1 (fr) | 2012-12-14 | 2014-12-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure |
US8946054B2 (en) | 2013-04-19 | 2015-02-03 | International Business Machines Corporation | Crack control for substrate separation |
FR3076069B1 (fr) * | 2017-12-22 | 2021-11-26 | Commissariat Energie Atomique | Procede de transfert d'une couche utile |
FR3076070B1 (fr) * | 2017-12-22 | 2019-12-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile |
DE102018221582A1 (de) | 2018-12-13 | 2020-06-18 | Siltronic Ag | Verfahren zur Herstellung einer Halbleiterscheibe und Halbleiterscheibe |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10114176A (ja) | 1996-10-11 | 1998-05-06 | Kunio Kuramochi | 図示式野球スコアブック |
KR100232886B1 (ko) * | 1996-11-23 | 1999-12-01 | 김영환 | Soi 웨이퍼 제조방법 |
JP3932369B2 (ja) | 1998-04-09 | 2007-06-20 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
JPH11307747A (ja) | 1998-04-17 | 1999-11-05 | Nec Corp | Soi基板およびその製造方法 |
JP3500063B2 (ja) | 1998-04-23 | 2004-02-23 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JP4476390B2 (ja) * | 1998-09-04 | 2010-06-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
DE60041309D1 (de) * | 1999-03-16 | 2009-02-26 | Shinetsu Handotai Kk | Herstellungsverfahren für siliziumwafer und siliziumwafer |
FR2817394B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
US6448152B1 (en) * | 2001-02-20 | 2002-09-10 | Silicon Genesis Corporation | Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer |
US6737337B1 (en) * | 2001-04-27 | 2004-05-18 | Advanced Micro Devices, Inc. | Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device |
US20030029957A1 (en) | 2001-08-13 | 2003-02-13 | Smith Ronald D. | System and method for manufacturing an ignition coil |
JP2003068744A (ja) * | 2001-08-30 | 2003-03-07 | Shin Etsu Handotai Co Ltd | シリコンウエーハの製造方法及びシリコンウエーハ並びにsoiウエーハ |
US7153757B2 (en) * | 2002-08-29 | 2006-12-26 | Analog Devices, Inc. | Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure |
JP2004247610A (ja) * | 2003-02-14 | 2004-09-02 | Canon Inc | 基板の製造方法 |
US7563319B2 (en) * | 2003-02-14 | 2009-07-21 | Sumitomo Mitsubishi Silicon Corporation | Manufacturing method of silicon wafer |
FR2855909B1 (fr) * | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
US7052978B2 (en) * | 2003-08-28 | 2006-05-30 | Intel Corporation | Arrangements incorporating laser-induced cleaving |
EP1662549B1 (de) * | 2003-09-01 | 2015-07-29 | SUMCO Corporation | Verfahren zur herstellung eines gebondeten wafers |
EP1659623B1 (de) * | 2004-11-19 | 2008-04-16 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Verfahren zur Herstellung eines Germanium-On-Insulator-Wafers (GeOI) |
FR2881573B1 (fr) * | 2005-01-31 | 2008-07-11 | Soitec Silicon On Insulator | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
US20070117350A1 (en) * | 2005-08-03 | 2007-05-24 | Memc Electronic Materials, Inc. | Strained silicon on insulator (ssoi) with layer transfer from oxidized donor |
-
2007
- 2007-01-24 EP EP20100290492 patent/EP2264755A3/de not_active Withdrawn
- 2007-01-24 EP EP20070290094 patent/EP1950803B1/de active Active
- 2007-01-24 AT AT07290094T patent/ATE518241T1/de not_active IP Right Cessation
- 2007-09-05 US US11/850,481 patent/US7736994B2/en active Active
-
2008
- 2008-01-16 JP JP2009546830A patent/JP4817342B2/ja active Active
- 2008-01-16 WO PCT/IB2008/000131 patent/WO2008090439A1/en active Application Filing
- 2008-01-16 CN CN2008800011140A patent/CN101558487B/zh active Active
- 2008-01-16 KR KR1020097011182A patent/KR101302426B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP1950803B1 (de) | 2011-07-27 |
US7736994B2 (en) | 2010-06-15 |
KR101302426B1 (ko) | 2013-09-10 |
EP2264755A2 (de) | 2010-12-22 |
EP1950803A1 (de) | 2008-07-30 |
US20080176380A1 (en) | 2008-07-24 |
EP2264755A3 (de) | 2011-11-23 |
JP4817342B2 (ja) | 2011-11-16 |
CN101558487B (zh) | 2012-05-30 |
KR20090108689A (ko) | 2009-10-16 |
CN101558487A (zh) | 2009-10-14 |
WO2008090439A1 (en) | 2008-07-31 |
JP2010517286A (ja) | 2010-05-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |