FR2881573B1 - Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes - Google Patents
Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunesInfo
- Publication number
- FR2881573B1 FR2881573B1 FR0500936A FR0500936A FR2881573B1 FR 2881573 B1 FR2881573 B1 FR 2881573B1 FR 0500936 A FR0500936 A FR 0500936A FR 0500936 A FR0500936 A FR 0500936A FR 2881573 B1 FR2881573 B1 FR 2881573B1
- Authority
- FR
- France
- Prior art keywords
- amas
- gaps
- transferring
- substrate
- layer formed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- TYKASZBHFXBROF-UHFFFAOYSA-N (2,5-dioxopyrrolidin-1-yl) 2-(2,5-dioxopyrrol-1-yl)acetate Chemical compound O=C1CCC(=O)N1OC(=O)CN1C(=O)C=CC1=O TYKASZBHFXBROF-UHFFFAOYSA-N 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
- A47L9/00—Details or accessories of suction cleaners, e.g. mechanical means for controlling the suction or for effecting pulsating action; Storing devices specially adapted to suction cleaners or parts thereof; Carrying-vehicles specially adapted for suction cleaners
- A47L9/24—Hoses or pipes; Hose or pipe couplings
- A47L9/242—Hose or pipe couplings
- A47L9/246—Hose or pipe couplings with electrical connectors
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0500936A FR2881573B1 (fr) | 2005-01-31 | 2005-01-31 | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
US11/128,560 US7285471B2 (en) | 2005-01-31 | 2005-05-13 | Process for transfer of a thin layer formed in a substrate with vacancy clusters |
CNB2006100019925A CN100524620C (zh) | 2005-01-31 | 2006-01-25 | 半导体衬底及其制造和循环利用的方法 |
KR1020060008946A KR100796831B1 (ko) | 2005-01-31 | 2006-01-27 | 빈 자리 클러스터를 가지는 기판에서 형성된 박층 이송방법 |
SG200600599A SG124408A1 (en) | 2005-01-31 | 2006-01-27 | Process for transfer of a thin layer formed in a substrate with vacancy clusters |
TW095103237A TWI305661B (en) | 2005-01-31 | 2006-01-27 | Process for transfer of a thin layer formed in a substrate with vacancy clusters |
JP2006022763A JP5025957B2 (ja) | 2005-01-31 | 2006-01-31 | 欠陥クラスタを有する基板内に形成された薄い層を転写する方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0500936A FR2881573B1 (fr) | 2005-01-31 | 2005-01-31 | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2881573A1 FR2881573A1 (fr) | 2006-08-04 |
FR2881573B1 true FR2881573B1 (fr) | 2008-07-11 |
Family
ID=34979525
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0500936A Active FR2881573B1 (fr) | 2005-01-31 | 2005-01-31 | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
Country Status (7)
Country | Link |
---|---|
US (1) | US7285471B2 (fr) |
JP (1) | JP5025957B2 (fr) |
KR (1) | KR100796831B1 (fr) |
CN (1) | CN100524620C (fr) |
FR (1) | FR2881573B1 (fr) |
SG (1) | SG124408A1 (fr) |
TW (1) | TWI305661B (fr) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5314838B2 (ja) * | 2006-07-14 | 2013-10-16 | 信越半導体株式会社 | 剥離ウェーハを再利用する方法 |
WO2008050176A1 (fr) * | 2006-10-27 | 2008-05-02 | S.O.I.Tec Silicon On Insulator Technologies | Procédé optimisé de transfert d'une couche mince formée dans un substrat avec groupes de trous |
US8124499B2 (en) * | 2006-11-06 | 2012-02-28 | Silicon Genesis Corporation | Method and structure for thick layer transfer using a linear accelerator |
JP5249511B2 (ja) * | 2006-11-22 | 2013-07-31 | 信越化学工業株式会社 | Soq基板およびsoq基板の製造方法 |
FR2911430B1 (fr) * | 2007-01-15 | 2009-04-17 | Soitec Silicon On Insulator | "procede de fabrication d'un substrat hybride" |
EP2264755A3 (fr) | 2007-01-24 | 2011-11-23 | S.O.I.TEC Silicon on Insulator Technologies S.A. | Procédé de fabrication de plaquettes silicium sur isolant et plaquette correspondante |
FR2912259B1 (fr) * | 2007-02-01 | 2009-06-05 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat du type "silicium sur isolant". |
EP1986229A1 (fr) * | 2007-04-27 | 2008-10-29 | S.O.I.T.E.C. Silicon on Insulator Technologies | Procédé de fabrication de galettes de matériau composé et galette de matériau composé correspondante |
WO2009106915A1 (fr) * | 2008-02-26 | 2009-09-03 | S.O.I.Tec Silicon On On Insulator Technologies | Procédé d'élimination ou de réduction de la quantité de défauts cristallins dans une couche semi-conductrice d'une structure composite |
WO2009115859A1 (fr) * | 2008-03-19 | 2009-09-24 | S.O.I. Tec Silicon On Insulator Technologies | Substrats pour circuits optiques monolithiques et circuits électroniques |
FR2941324B1 (fr) * | 2009-01-22 | 2011-04-29 | Soitec Silicon On Insulator | Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant. |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
SG181071A1 (en) | 2009-12-15 | 2012-07-30 | Soitec Silicon On Insulator | Process for recycling a substrate. |
CN112771670A (zh) * | 2017-09-24 | 2021-05-07 | 宏大3D有限公司 | 3d半导体器件、配置和方法 |
JP7518766B2 (ja) * | 2017-12-21 | 2024-07-18 | グローバルウェーハズ カンパニー リミテッド | Llsリング/コアパターンを改善する単結晶シリコンインゴットの処理の方法 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2857456B2 (ja) * | 1990-01-19 | 1999-02-17 | 株式会社リコー | 半導体膜の製造方法 |
JPH05259012A (ja) * | 1992-03-10 | 1993-10-08 | Nec Corp | 半導体基板およびその製造方法 |
DE19637182A1 (de) * | 1996-09-12 | 1998-03-19 | Wacker Siltronic Halbleitermat | Verfahren zur Herstellung von Halbleiterscheiben aus Silicium mit geringer Defektdichte |
KR100232886B1 (ko) * | 1996-11-23 | 1999-12-01 | 김영환 | Soi 웨이퍼 제조방법 |
KR19980060508A (ko) * | 1996-12-31 | 1998-10-07 | 김영환 | 접합형 SOI(Silicon-On-Insulator) 기판의 제조 방법 |
US6245430B1 (en) | 1997-12-12 | 2001-06-12 | Sumitomo Sitix Corporation | Silicon single crystal wafer and manufacturing method for it |
JP3407629B2 (ja) * | 1997-12-17 | 2003-05-19 | 信越半導体株式会社 | シリコン単結晶ウエーハの熱処理方法ならびにシリコン単結晶ウエーハ |
EP1052687B1 (fr) | 1998-02-02 | 2016-06-29 | Nippon Steel & Sumitomo Metal Corporation | Procede de fabrication d'un substrat soi. |
JP3500063B2 (ja) * | 1998-04-23 | 2004-02-23 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
JP3697106B2 (ja) | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
US6224668B1 (en) | 1998-06-02 | 2001-05-01 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI substrate and SOI substrate |
JP2000012864A (ja) * | 1998-06-22 | 2000-01-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP4228419B2 (ja) * | 1998-07-29 | 2009-02-25 | 信越半導体株式会社 | Soiウエーハの製造方法およびsoiウエーハ |
WO2000013211A2 (fr) | 1998-09-02 | 2000-03-09 | Memc Electronic Materials, Inc. | Structure silicium sur isolant obtenue a partir d'un silicium monocristallin a faible taux de defauts |
US6387829B1 (en) * | 1999-06-18 | 2002-05-14 | Silicon Wafer Technologies, Inc. | Separation process for silicon-on-insulator wafer fabrication |
FR2797713B1 (fr) * | 1999-08-20 | 2002-08-02 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
US6489241B1 (en) * | 1999-09-17 | 2002-12-03 | Applied Materials, Inc. | Apparatus and method for surface finishing a silicon film |
EP1158581B1 (fr) | 1999-10-14 | 2016-04-27 | Shin-Etsu Handotai Co., Ltd. | Procede de fabrication d'une tranche de soi, et tranche de soi |
JP3994602B2 (ja) | 1999-11-12 | 2007-10-24 | 信越半導体株式会社 | シリコン単結晶ウエーハおよびその製造方法並びにsoiウエーハ |
DE19960823B4 (de) * | 1999-12-16 | 2007-04-12 | Siltronic Ag | Verfahren zur Herstellung einer epitaxierten Halbleiterscheibe und deren Verwendung |
JP4276764B2 (ja) * | 2000-03-27 | 2009-06-10 | シルトロニック・ジャパン株式会社 | シリコン単結晶基板及びその製造方法 |
JP2001278692A (ja) * | 2000-03-29 | 2001-10-10 | Shin Etsu Handotai Co Ltd | シリコンウエーハおよびシリコン単結晶の製造方法 |
JP2002110688A (ja) * | 2000-09-29 | 2002-04-12 | Canon Inc | Soiの熱処理方法及び製造方法 |
US6743495B2 (en) * | 2001-03-30 | 2004-06-01 | Memc Electronic Materials, Inc. | Thermal annealing process for producing silicon wafers with improved surface characteristics |
JP2003204048A (ja) | 2002-01-09 | 2003-07-18 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
US6995075B1 (en) * | 2002-07-12 | 2006-02-07 | Silicon Wafer Technologies | Process for forming a fragile layer inside of a single crystalline substrate |
JP4192530B2 (ja) * | 2002-08-27 | 2008-12-10 | 株式会社Sumco | パーティクルモニター用シリコン単結晶ウェーハの製造方法 |
KR100473855B1 (ko) * | 2002-09-12 | 2005-03-10 | 주식회사 실트론 | 에스오아이 웨이퍼의 제조 방법 |
US20040060899A1 (en) * | 2002-10-01 | 2004-04-01 | Applied Materials, Inc. | Apparatuses and methods for treating a silicon film |
TWI265217B (en) | 2002-11-14 | 2006-11-01 | Komatsu Denshi Kinzoku Kk | Method and device for manufacturing silicon wafer, method for manufacturing silicon single crystal, and device for pulling up silicon single crystal |
TW200428637A (en) | 2003-01-23 | 2004-12-16 | Shinetsu Handotai Kk | SOI wafer and production method thereof |
US7018909B2 (en) | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
US7566482B2 (en) | 2003-09-30 | 2009-07-28 | International Business Machines Corporation | SOI by oxidation of porous silicon |
US7148124B1 (en) * | 2004-11-18 | 2006-12-12 | Alexander Yuri Usenko | Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers |
-
2005
- 2005-01-31 FR FR0500936A patent/FR2881573B1/fr active Active
- 2005-05-13 US US11/128,560 patent/US7285471B2/en active Active
-
2006
- 2006-01-25 CN CNB2006100019925A patent/CN100524620C/zh active Active
- 2006-01-27 TW TW095103237A patent/TWI305661B/zh active
- 2006-01-27 SG SG200600599A patent/SG124408A1/en unknown
- 2006-01-27 KR KR1020060008946A patent/KR100796831B1/ko active IP Right Grant
- 2006-01-31 JP JP2006022763A patent/JP5025957B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
CN100524620C (zh) | 2009-08-05 |
CN1828830A (zh) | 2006-09-06 |
US20060172508A1 (en) | 2006-08-03 |
SG124408A1 (en) | 2006-08-30 |
TW200723364A (en) | 2007-06-16 |
FR2881573A1 (fr) | 2006-08-04 |
JP2006261648A (ja) | 2006-09-28 |
US7285471B2 (en) | 2007-10-23 |
JP5025957B2 (ja) | 2012-09-12 |
TWI305661B (en) | 2009-01-21 |
KR20060088052A (ko) | 2006-08-03 |
KR100796831B1 (ko) | 2008-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2881573B1 (fr) | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes | |
FR2925221B1 (fr) | Procede de transfert d'une couche mince | |
FR2889887B1 (fr) | Procede de report d'une couche mince sur un support | |
FR2905707B1 (fr) | Procede pour deposer sur un substrat une couche mince d'alliage metallique et alliage metallique sous forme de couche mince. | |
FR2897982B1 (fr) | Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat | |
FR2889202B1 (fr) | Procede de depot d'une couche anti-rayure | |
EP1894234A4 (fr) | Procede pour rigidite de substrat et dispositif resultant pour traitements a transfert de couche | |
FR2905801B1 (fr) | Procede de transfert d'une couche a haute temperature | |
EP1981085A4 (fr) | Substrat tft, substrat tft reflechissant et leur procede de fabrication | |
FR2855908B1 (fr) | Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince | |
EP1983499A4 (fr) | Substrat tft reflechissant et procede de fabrication de substrat tft reflechissant | |
EP1933293A4 (fr) | Substrat pour tft et procede de fabrication d'un substrat pour tft | |
EP1891694A4 (fr) | Appareil electrochimique a substrat protege par une couche barriere | |
EP2184727A4 (fr) | Substrat ayant une couche barrière, élément d'afficheur et procédé de fabrication d'un élément d'afficheur | |
TWI373106B (en) | Microelectronic substrate including embedded components and spacer layer and method of forming same | |
FR2895562B1 (fr) | Procede de relaxation d'une couche mince contrainte | |
FR2920589B1 (fr) | "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure" | |
FR2950062B1 (fr) | Solution et procede d'activation de la surface d'un substrat semi-conducteur | |
FR2915625B1 (fr) | Procede de transfert d'une couche epitaxiale | |
FR2933534B1 (fr) | Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat | |
FR2896338B1 (fr) | Procede de realisation d'une couche monocristalline sur une couche dielectrique | |
FR2847076B1 (fr) | Procede de detachement d'une couche mince a temperature moderee apres co-implantation | |
FR2865420B1 (fr) | Procede de nettoyage d'un substrat | |
TWI348221B (en) | Thin film transistor array substrate structures and fabrication method thereof | |
EP1953590A4 (fr) | Procédé de fabrication d'une nervure écran et substrat pour support d'affichage électrophorétique et support d'affichage électrophorétique |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
|
PLFP | Fee payment |
Year of fee payment: 12 |
|
PLFP | Fee payment |
Year of fee payment: 13 |
|
PLFP | Fee payment |
Year of fee payment: 14 |
|
PLFP | Fee payment |
Year of fee payment: 16 |
|
PLFP | Fee payment |
Year of fee payment: 17 |
|
PLFP | Fee payment |
Year of fee payment: 18 |
|
PLFP | Fee payment |
Year of fee payment: 19 |
|
PLFP | Fee payment |
Year of fee payment: 20 |