FR2855909B1 - Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat - Google Patents
Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substratInfo
- Publication number
- FR2855909B1 FR2855909B1 FR0306845A FR0306845A FR2855909B1 FR 2855909 B1 FR2855909 B1 FR 2855909B1 FR 0306845 A FR0306845 A FR 0306845A FR 0306845 A FR0306845 A FR 0306845A FR 2855909 B1 FR2855909 B1 FR 2855909B1
- Authority
- FR
- France
- Prior art keywords
- structures
- substrate
- pair
- useful layer
- concurrent production
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0306845A FR2855909B1 (fr) | 2003-06-06 | 2003-06-06 | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
US10/686,084 US7115481B2 (en) | 2003-06-06 | 2003-10-14 | Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate |
JP2006508351A JP4625913B2 (ja) | 2003-06-06 | 2004-06-03 | 有用層で被覆された一対の基板の同時製造方法 |
PCT/FR2004/001368 WO2005004232A1 (fr) | 2003-06-06 | 2004-06-03 | Procede d'obtention concomitante d'une paire de substrats recouverts d'une couche utile |
EP04767237A EP1631983A1 (fr) | 2003-06-06 | 2004-06-03 | Procede d'obtention concomitante d'une paire de substrats recouverts d'une couche utile |
CNB2004800118243A CN100358124C (zh) | 2003-06-06 | 2004-06-03 | 用于同时得到一对由有用层覆盖的衬底的方法 |
KR1020057022437A KR100751150B1 (ko) | 2003-06-06 | 2004-06-03 | 이송층에 의해 덮혀진 한 쌍의 기판을 동시에 얻는 방법 |
US11/509,047 US7407867B2 (en) | 2003-06-06 | 2006-08-24 | Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0306845A FR2855909B1 (fr) | 2003-06-06 | 2003-06-06 | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2855909A1 FR2855909A1 (fr) | 2004-12-10 |
FR2855909B1 true FR2855909B1 (fr) | 2005-08-26 |
Family
ID=33443190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0306845A Expired - Fee Related FR2855909B1 (fr) | 2003-06-06 | 2003-06-06 | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
Country Status (7)
Country | Link |
---|---|
US (2) | US7115481B2 (fr) |
EP (1) | EP1631983A1 (fr) |
JP (1) | JP4625913B2 (fr) |
KR (1) | KR100751150B1 (fr) |
CN (1) | CN100358124C (fr) |
FR (1) | FR2855909B1 (fr) |
WO (1) | WO2005004232A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8951887B2 (en) | 2011-06-23 | 2015-02-10 | Soitec | Process for fabricating a semiconductor structure employing a temporary bond |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2892228B1 (fr) * | 2005-10-18 | 2008-01-25 | Soitec Silicon On Insulator | Procede de recyclage d'une plaquette donneuse epitaxiee |
US20090325362A1 (en) * | 2003-01-07 | 2009-12-31 | Nabil Chhaimi | Method of recycling an epitaxied donor wafer |
FR2855910B1 (fr) * | 2003-06-06 | 2005-07-15 | Commissariat Energie Atomique | Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque |
US20060194400A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | Method for fabricating a semiconductor device |
JP2006210660A (ja) * | 2005-01-28 | 2006-08-10 | Hitachi Cable Ltd | 半導体基板の製造方法 |
US7262112B2 (en) * | 2005-06-27 | 2007-08-28 | The Regents Of The University Of California | Method for producing dislocation-free strained crystalline films |
EP1777735A3 (fr) * | 2005-10-18 | 2009-08-19 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de recyclage d'une plaquette donneuse épitaxiée |
FR2896618B1 (fr) | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite |
FR2896619B1 (fr) * | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite a proprietes electriques ameliorees |
IL174844A (en) | 2006-04-06 | 2011-02-28 | Semi Conductor Devices An Elbit Systems Rafael Partnership | Unipolar semiconductor photodetector with suppressed dark current and method for producing the same |
EP1950803B1 (fr) | 2007-01-24 | 2011-07-27 | S.O.I.TEC Silicon on Insulator Technologies S.A. | Procédé de fabrication de plaquettes silicium sur isolant, et plaquette correspondante |
EP1986229A1 (fr) * | 2007-04-27 | 2008-10-29 | S.O.I.T.E.C. Silicon on Insulator Technologies | Procédé de fabrication de galettes de matériau composé et galette de matériau composé correspondante |
US7795114B2 (en) * | 2007-08-10 | 2010-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing methods of SOI substrate and semiconductor device |
US7781308B2 (en) * | 2007-12-03 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US7820527B2 (en) * | 2008-02-20 | 2010-10-26 | Varian Semiconductor Equipment Associates, Inc. | Cleave initiation using varying ion implant dose |
JP2009212387A (ja) * | 2008-03-05 | 2009-09-17 | Semiconductor Energy Lab Co Ltd | 半導体基板の製造方法 |
FR2929758B1 (fr) * | 2008-04-07 | 2011-02-11 | Commissariat Energie Atomique | Procede de transfert a l'aide d'un substrat ferroelectrique |
FR2934924B1 (fr) * | 2008-08-06 | 2011-04-22 | Soitec Silicon On Insulator | Procede de multi implantation dans un substrat. |
EP2157602A1 (fr) * | 2008-08-20 | 2010-02-24 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. | Procédé de fabrication de plusieurs wafers de fabrication |
JP5611571B2 (ja) * | 2008-11-27 | 2014-10-22 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法及び半導体装置の作製方法 |
JP5404135B2 (ja) * | 2009-03-31 | 2014-01-29 | 株式会社ブリヂストン | 支持基板、貼り合わせ基板、支持基板の製造方法、及び貼り合わせ基板の製造方法 |
FR2944914B1 (fr) * | 2009-04-22 | 2011-05-20 | Commissariat Energie Atomique | Procede de transfert d'au moins une couche micro-technologique |
FR2940852A1 (fr) * | 2009-04-22 | 2010-07-09 | Commissariat Energie Atomique | Procede de transfert d'une couche depuis un substrat de depart vers un substrat final, par double fragilisation |
US8546238B2 (en) | 2009-04-22 | 2013-10-01 | Commissariat A L'energie Atomique Et Aux Energies | Method for transferring at least one micro-technological layer |
US8513090B2 (en) * | 2009-07-16 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate, and semiconductor device |
US20110108854A1 (en) * | 2009-11-10 | 2011-05-12 | Chien-Min Sung | Substantially lattice matched semiconductor materials and associated methods |
US8921239B2 (en) * | 2009-12-15 | 2014-12-30 | Soitec | Process for recycling a substrate |
CN102194827A (zh) * | 2010-03-16 | 2011-09-21 | 北京大学 | 一种基于高介电常数材料的抗辐照soi器件及制备方法 |
CN102820251A (zh) * | 2011-06-08 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | 一种基于键合工艺的高k介质埋层的soi材料制备方法 |
JPWO2013105634A1 (ja) * | 2012-01-12 | 2015-05-11 | 信越化学工業株式会社 | 熱酸化異種複合基板及びその製造方法 |
US10543662B2 (en) | 2012-02-08 | 2020-01-28 | Corning Incorporated | Device modified substrate article and methods for making |
FR2992464B1 (fr) * | 2012-06-26 | 2015-04-03 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
US10014177B2 (en) | 2012-12-13 | 2018-07-03 | Corning Incorporated | Methods for processing electronic devices |
TWI617437B (zh) | 2012-12-13 | 2018-03-11 | 康寧公司 | 促進控制薄片與載體間接合之處理 |
US10086584B2 (en) | 2012-12-13 | 2018-10-02 | Corning Incorporated | Glass articles and methods for controlled bonding of glass sheets with carriers |
US9340443B2 (en) | 2012-12-13 | 2016-05-17 | Corning Incorporated | Bulk annealing of glass sheets |
US10510576B2 (en) | 2013-10-14 | 2019-12-17 | Corning Incorporated | Carrier-bonding methods and articles for semiconductor and interposer processing |
KR102353030B1 (ko) | 2014-01-27 | 2022-01-19 | 코닝 인코포레이티드 | 얇은 시트와 캐리어의 제어된 결합을 위한 물품 및 방법 |
EP3129221A1 (fr) | 2014-04-09 | 2017-02-15 | Corning Incorporated | Article de substrat modifié de dispositif et procédés de fabrication |
FR3029538B1 (fr) * | 2014-12-04 | 2019-04-26 | Soitec | Procede de transfert de couche |
EP3297824A1 (fr) | 2015-05-19 | 2018-03-28 | Corning Incorporated | Articles et procédés pour lier des feuilles minces à des supports |
KR102524620B1 (ko) | 2015-06-26 | 2023-04-21 | 코닝 인코포레이티드 | 시트 및 캐리어를 포함하는 방법들 및 물품들 |
FR3051979B1 (fr) * | 2016-05-25 | 2018-05-18 | Soitec | Procede de guerison de defauts dans une couche obtenue par implantation puis detachement d'un substrat |
TW202216444A (zh) | 2016-08-30 | 2022-05-01 | 美商康寧公司 | 用於片材接合的矽氧烷電漿聚合物 |
TWI810161B (zh) | 2016-08-31 | 2023-08-01 | 美商康寧公司 | 具以可控制式黏結的薄片之製品及製作其之方法 |
US11331692B2 (en) | 2017-12-15 | 2022-05-17 | Corning Incorporated | Methods for treating a substrate and method for making articles comprising bonded sheets |
CN110078017B (zh) * | 2018-01-26 | 2021-11-05 | 沈阳硅基科技有限公司 | 一种贯穿空腔结构硅片的加工方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107213A (en) * | 1996-02-01 | 2000-08-22 | Sony Corporation | Method for making thin film semiconductor |
JPH10135500A (ja) * | 1996-03-18 | 1998-05-22 | Sony Corp | 薄膜半導体、太陽電池および発光素子の製造方法 |
DE69728022T2 (de) | 1996-12-18 | 2004-08-12 | Canon K.K. | Vefahren zum Herstellen eines Halbleiterartikels unter Verwendung eines Substrates mit einer porösen Halbleiterschicht |
CA2233096C (fr) * | 1997-03-26 | 2003-01-07 | Canon Kabushiki Kaisha | Substrat et methode de production |
JP3697052B2 (ja) * | 1997-03-26 | 2005-09-21 | キヤノン株式会社 | 基板の製造方法及び半導体膜の製造方法 |
US6150239A (en) * | 1997-05-31 | 2000-11-21 | Max Planck Society | Method for the transfer of thin layers monocrystalline material onto a desirable substrate |
JP3324469B2 (ja) * | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
FR2777115B1 (fr) * | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US20020089016A1 (en) * | 1998-07-10 | 2002-07-11 | Jean-Pierre Joly | Thin layer semi-conductor structure comprising a heat distribution layer |
AU2481101A (en) | 1999-07-19 | 2001-02-05 | Maschinenfabrik Bernard Krone Gmbh | Harvesting equipment for stalk plants |
FR2797714B1 (fr) | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
JP3975634B2 (ja) * | 2000-01-25 | 2007-09-12 | 信越半導体株式会社 | 半導体ウェハの製作法 |
FR2840731B3 (fr) * | 2002-06-11 | 2004-07-30 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
FR2817394B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
US6420243B1 (en) * | 2000-12-04 | 2002-07-16 | Motorola, Inc. | Method for producing SOI wafers by delamination |
-
2003
- 2003-06-06 FR FR0306845A patent/FR2855909B1/fr not_active Expired - Fee Related
- 2003-10-14 US US10/686,084 patent/US7115481B2/en not_active Expired - Fee Related
-
2004
- 2004-06-03 CN CNB2004800118243A patent/CN100358124C/zh not_active Expired - Fee Related
- 2004-06-03 EP EP04767237A patent/EP1631983A1/fr not_active Withdrawn
- 2004-06-03 JP JP2006508351A patent/JP4625913B2/ja not_active Expired - Fee Related
- 2004-06-03 KR KR1020057022437A patent/KR100751150B1/ko not_active IP Right Cessation
- 2004-06-03 WO PCT/FR2004/001368 patent/WO2005004232A1/fr active Application Filing
-
2006
- 2006-08-24 US US11/509,047 patent/US7407867B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8951887B2 (en) | 2011-06-23 | 2015-02-10 | Soitec | Process for fabricating a semiconductor structure employing a temporary bond |
Also Published As
Publication number | Publication date |
---|---|
CN100358124C (zh) | 2007-12-26 |
US20060286770A1 (en) | 2006-12-21 |
US7407867B2 (en) | 2008-08-05 |
US7115481B2 (en) | 2006-10-03 |
EP1631983A1 (fr) | 2006-03-08 |
CN1781188A (zh) | 2006-05-31 |
US20040248378A1 (en) | 2004-12-09 |
FR2855909A1 (fr) | 2004-12-10 |
KR100751150B1 (ko) | 2007-08-22 |
WO2005004232A1 (fr) | 2005-01-13 |
JP4625913B2 (ja) | 2011-02-02 |
JP2006527478A (ja) | 2006-11-30 |
KR20060017615A (ko) | 2006-02-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2855909B1 (fr) | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat | |
FR2855908B1 (fr) | Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince | |
FR2856677B1 (fr) | Substrat revetu d'une couche dielectrique et procede pour sa fabrication | |
FR2851372B1 (fr) | Procede de fabrication d'un substrat a couche isolante enterree | |
FR2822167B1 (fr) | Procede de metallisation d'une piece substrat | |
FR2867310B1 (fr) | Technique d'amelioration de la qualite d'une couche mince prelevee | |
FR2889887B1 (fr) | Procede de report d'une couche mince sur un support | |
FR2890984B1 (fr) | Procede d'electrodeposition destine au revetement d'une surface d'un substrat par un metal. | |
FR2874606B1 (fr) | Procede de transfert d'une molecule organique fonctionnelle sur un substrat transparent | |
FR2918793B1 (fr) | Procede de fabrication d'un substrat semiconducteur-sur- isolant pour la microelectronique et l'optoelectronique. | |
FR2842651B1 (fr) | Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support | |
MA26237A1 (fr) | Composition aqueuse pour l'hydrophobation d'un substrat. | |
FR2865420B1 (fr) | Procede de nettoyage d'un substrat | |
FR2830856B1 (fr) | Precurseur de revetement et procede pour revetir un substrat d'une couche refractaire | |
FR2893608B1 (fr) | Procede de marquage d'une face d'un substrat de type verrier, un tel substrat et moyen de marquage pour le procede | |
FR2912258B1 (fr) | "procede de fabrication d'un substrat du type silicium sur isolant" | |
FR2852445B1 (fr) | Procede de realisation de substrats ou composants sur substrats avec transfert de couche utile, pour la microelectronique, l'optoelectronique ou l'optique | |
FR2868202B1 (fr) | Procede de preparation d'une couche de dioxyde de silicium par oxydation a haute temperature sur un substrat presentant au moins en surface du germanium ou un alliage sicicium- germanium. | |
FR2821862B1 (fr) | Procede de gravure de couches deposees sur des substrats transparents du type substrat verrier | |
FI20021247A (fi) | Hyvin viskoosinen päällystysaine huokoiselle substraateille | |
FR2867199B1 (fr) | Procede pour l'obtention d'un substrat mettalique comportant un revetement protecteur | |
NO20026107L (no) | Fremgangsmåte for dannelse av en sjiktstruktur på et substrat | |
FR2845078B1 (fr) | PROCEDE DE FABRICATION D'UN SUBSTRAT EN NITRURE D'ALUMINIUM AlN | |
FR2837839B1 (fr) | Procede de fabrication du revetement d'un substrat metallique | |
FR2842649B1 (fr) | Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name |
Owner name: COMMISSARIAT A L ENERGIE ATOMIQUE, FR Effective date: 20120423 Owner name: SOITEC, FR Effective date: 20120423 |
|
ST | Notification of lapse |
Effective date: 20150227 |