FR2838865B1 - Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee - Google Patents

Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee

Info

Publication number
FR2838865B1
FR2838865B1 FR0205054A FR0205054A FR2838865B1 FR 2838865 B1 FR2838865 B1 FR 2838865B1 FR 0205054 A FR0205054 A FR 0205054A FR 0205054 A FR0205054 A FR 0205054A FR 2838865 B1 FR2838865 B1 FR 2838865B1
Authority
FR
France
Prior art keywords
producing
substrate
high resistivity
useful layer
resistivity support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0205054A
Other languages
English (en)
Other versions
FR2838865A1 (fr
Inventor
Bruno Ghyselen
Hubert Moriceau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0205054A priority Critical patent/FR2838865B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/IB2003/002237 priority patent/WO2003092041A2/fr
Priority to EP03727798.5A priority patent/EP1497854B1/fr
Priority to KR1020047017132A priority patent/KR100797212B1/ko
Priority to JP2004500314A priority patent/JP2005524228A/ja
Priority to AU2003232998A priority patent/AU2003232998A1/en
Publication of FR2838865A1 publication Critical patent/FR2838865A1/fr
Priority to US10/968,695 priority patent/US7268060B2/en
Application granted granted Critical
Publication of FR2838865B1 publication Critical patent/FR2838865B1/fr
Priority to US11/831,217 priority patent/US7586154B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
FR0205054A 2002-04-23 2002-04-23 Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee Expired - Lifetime FR2838865B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0205054A FR2838865B1 (fr) 2002-04-23 2002-04-23 Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
EP03727798.5A EP1497854B1 (fr) 2002-04-23 2003-04-23 Procede pour fabriquer un substrat presentant une couche utile sur un support a haute resistivite
KR1020047017132A KR100797212B1 (ko) 2002-04-23 2003-04-23 고 저항성 지지체 상에 유용층을 구비한 기판의 제조 방법
JP2004500314A JP2005524228A (ja) 2002-04-23 2003-04-23 高抵抗支持体上に有用層を有する基板の製造方法
PCT/IB2003/002237 WO2003092041A2 (fr) 2002-04-23 2003-04-23 Procede pour fabriquer un substrat presentant une couche utile sur un support a haute resistivite
AU2003232998A AU2003232998A1 (en) 2002-04-23 2003-04-23 Method for fabricating a soi substrate a high resistivity support substrate
US10/968,695 US7268060B2 (en) 2002-04-23 2004-10-18 Method for fabricating a substrate with useful layer on high resistivity support
US11/831,217 US7586154B2 (en) 2002-04-23 2007-07-31 Method for fabricating a substrate with useful layer on high resistivity support

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0205054A FR2838865B1 (fr) 2002-04-23 2002-04-23 Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee

Publications (2)

Publication Number Publication Date
FR2838865A1 FR2838865A1 (fr) 2003-10-24
FR2838865B1 true FR2838865B1 (fr) 2005-10-14

Family

ID=28686280

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0205054A Expired - Lifetime FR2838865B1 (fr) 2002-04-23 2002-04-23 Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee

Country Status (7)

Country Link
US (2) US7268060B2 (fr)
EP (1) EP1497854B1 (fr)
JP (1) JP2005524228A (fr)
KR (1) KR100797212B1 (fr)
AU (1) AU2003232998A1 (fr)
FR (1) FR2838865B1 (fr)
WO (1) WO2003092041A2 (fr)

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FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
WO2004061943A1 (fr) * 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouche apres separation d'une couche mince de celle-ci
US20090325362A1 (en) * 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
FR2857953B1 (fr) * 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
US20060138601A1 (en) * 2004-12-27 2006-06-29 Memc Electronic Materials, Inc. Internally gettered heteroepitaxial semiconductor wafers and methods of manufacturing such wafers
FR2896618B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
EP1835533B1 (fr) * 2006-03-14 2020-06-03 Soitec Méthode de fabrication de plaquettes composites et procédé de recyclage d'un substrat donneur usagé
US20090061593A1 (en) * 2007-08-28 2009-03-05 Kishor Purushottam Gadkaree Semiconductor Wafer Re-Use in an Exfoliation Process Using Heat Treatment
FR2929755B1 (fr) * 2008-04-03 2011-04-22 Commissariat Energie Atomique Procede de traitement d'un substrat semi-conducteur par activation thermique d'elements legers
FR2929758B1 (fr) * 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
JP5532680B2 (ja) * 2009-05-27 2014-06-25 信越半導体株式会社 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
KR20130029110A (ko) * 2010-06-30 2013-03-21 코닝 인코포레이티드 절연체 기판상의 실리콘 마감을 위한 방법
WO2012088710A1 (fr) * 2010-12-27 2012-07-05 上海新傲科技股份有限公司 Procédé de préparation d'un substrat à semi-conducteur doté d'une couche enterrée isolante faisant appel à un processus de getterisation
FR2973159B1 (fr) 2011-03-22 2013-04-19 Soitec Silicon On Insulator Procede de fabrication d'un substrat de base
FR2973158B1 (fr) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
FR2983342B1 (fr) * 2011-11-30 2016-05-20 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue
US8536035B2 (en) 2012-02-01 2013-09-17 International Business Machines Corporation Silicon-on-insulator substrate and method of forming
JP6232993B2 (ja) * 2013-12-12 2017-11-22 日立化成株式会社 半導体基板の製造方法、半導体基板、太陽電池素子の製造方法及び太陽電池素子
JP6179530B2 (ja) * 2015-01-23 2017-08-16 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
FR3037438B1 (fr) 2015-06-09 2017-06-16 Soitec Silicon On Insulator Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
FR3051968B1 (fr) * 2016-05-25 2018-06-01 Soitec Procede de fabrication d'un substrat semi-conducteur a haute resistivite
FR3058561B1 (fr) 2016-11-04 2018-11-02 Soitec Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif
FR3062238A1 (fr) 2017-01-26 2018-07-27 Soitec Support pour une structure semi-conductrice
FR3064820B1 (fr) 2017-03-31 2019-11-29 Soitec Procede d'ajustement de l'etat de contrainte d'un film piezoelectrique
JP7230297B2 (ja) 2018-07-05 2023-03-01 ソイテック 集積された高周波デバイスのための基板及びそれを製造するための方法
FR3098642B1 (fr) 2019-07-12 2021-06-11 Soitec Silicon On Insulator procédé de fabrication d'une structure comprenant une couche mince reportée sur un support muni d’une couche de piégeage de charges
FR3121548B1 (fr) 2021-03-30 2024-02-16 Soitec Silicon On Insulator Procede de preparation d’un substrat avance, notamment pour des applications photoniques
JP2023535319A (ja) 2020-07-28 2023-08-17 ソイテック 電荷トラップ層が設けられたキャリア基板に薄層を転写するプロセス
FR3113184B1 (fr) 2020-07-28 2022-09-16 Soitec Silicon On Insulator Procede de preparation d’un substrat support, et procede de report d’une couche mince sur ce substrat support
FR3119929B1 (fr) * 2021-02-15 2023-11-03 Soitec Silicon On Insulator Procede de fabrication d’une structure adaptee pour les applications radiofrequences, et substrat support pour ladite structure
FR3129029B1 (fr) 2021-11-09 2023-09-29 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
FR3129028B1 (fr) 2021-11-09 2023-11-10 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
FR3137493A1 (fr) 2022-06-29 2024-01-05 Soitec Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques
FR3137490A1 (fr) 2022-07-04 2024-01-05 Soitec Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques

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JPS5856343A (ja) * 1981-09-29 1983-04-04 Fujitsu Ltd 半導体装置の製造方法
JPS5887833A (ja) * 1981-11-20 1983-05-25 Hitachi Ltd 半導体装置の製造方法
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JPH08293589A (ja) * 1995-04-21 1996-11-05 Hitachi Ltd 半導体基板および半導体装置
JPH10135164A (ja) * 1996-10-29 1998-05-22 Komatsu Electron Metals Co Ltd 半導体ウェハの製造方法
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JP2000031439A (ja) * 1998-07-13 2000-01-28 Fuji Electric Co Ltd Ｓｏｉ基板およびその製造方法
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JP2002009081A (ja) * 2000-06-26 2002-01-11 Toshiba Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US20070269663A1 (en) 2007-11-22
AU2003232998A8 (en) 2003-11-10
JP2005524228A (ja) 2005-08-11
US20050112845A1 (en) 2005-05-26
EP1497854A2 (fr) 2005-01-19
KR100797212B1 (ko) 2008-01-23
EP1497854B1 (fr) 2019-08-07
KR20040102169A (ko) 2004-12-03
AU2003232998A1 (en) 2003-11-10
US7268060B2 (en) 2007-09-11
WO2003092041A2 (fr) 2003-11-06
WO2003092041A3 (fr) 2003-12-24
FR2838865A1 (fr) 2003-10-24
WO2003092041B1 (fr) 2004-04-01
US7586154B2 (en) 2009-09-08

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