FR2797999B1 - Procede de fabrication d'une capacite integree sur un substrat de silicium - Google Patents

Procede de fabrication d'une capacite integree sur un substrat de silicium

Info

Publication number
FR2797999B1
FR2797999B1 FR9911139A FR9911139A FR2797999B1 FR 2797999 B1 FR2797999 B1 FR 2797999B1 FR 9911139 A FR9911139 A FR 9911139A FR 9911139 A FR9911139 A FR 9911139A FR 2797999 B1 FR2797999 B1 FR 2797999B1
Authority
FR
France
Prior art keywords
manufacturing
silicon substrate
integrated capacity
capacity
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9911139A
Other languages
English (en)
Other versions
FR2797999A1 (fr
Inventor
Philippe Delpech
Jean Claude Oberlin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR9911139A priority Critical patent/FR2797999B1/fr
Priority to US09/644,027 priority patent/US6391802B1/en
Publication of FR2797999A1 publication Critical patent/FR2797999A1/fr
Application granted granted Critical
Publication of FR2797999B1 publication Critical patent/FR2797999B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR9911139A 1999-08-31 1999-08-31 Procede de fabrication d'une capacite integree sur un substrat de silicium Expired - Fee Related FR2797999B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9911139A FR2797999B1 (fr) 1999-08-31 1999-08-31 Procede de fabrication d'une capacite integree sur un substrat de silicium
US09/644,027 US6391802B1 (en) 1999-08-31 2000-08-22 Method of manufacturing an integrated capacitor onto a silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9911139A FR2797999B1 (fr) 1999-08-31 1999-08-31 Procede de fabrication d'une capacite integree sur un substrat de silicium

Publications (2)

Publication Number Publication Date
FR2797999A1 FR2797999A1 (fr) 2001-03-02
FR2797999B1 true FR2797999B1 (fr) 2003-08-08

Family

ID=9549576

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9911139A Expired - Fee Related FR2797999B1 (fr) 1999-08-31 1999-08-31 Procede de fabrication d'une capacite integree sur un substrat de silicium

Country Status (2)

Country Link
US (1) US6391802B1 (fr)
FR (1) FR2797999B1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617209B1 (en) * 2002-02-22 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6890807B2 (en) * 2003-05-06 2005-05-10 Intel Corporation Method for making a semiconductor device having a metal gate electrode
US6806146B1 (en) * 2003-05-20 2004-10-19 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6939815B2 (en) * 2003-08-28 2005-09-06 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7037845B2 (en) * 2003-08-28 2006-05-02 Intel Corporation Selective etch process for making a semiconductor device having a high-k gate dielectric
US6974764B2 (en) * 2003-11-06 2005-12-13 Intel Corporation Method for making a semiconductor device having a metal gate electrode
US7129182B2 (en) * 2003-11-06 2006-10-31 Intel Corporation Method for etching a thin metal layer
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes
US7160767B2 (en) * 2003-12-18 2007-01-09 Intel Corporation Method for making a semiconductor device that includes a metal gate electrode
US20110032027A1 (en) * 2009-08-05 2011-02-10 Texas Instruments Incorporated Switched bandgap reference circuit for retention mode
US10316412B2 (en) 2012-04-18 2019-06-11 Veeco Instruments Inc. Wafter carrier for chemical vapor deposition systems
US10167571B2 (en) 2013-03-15 2019-01-01 Veeco Instruments Inc. Wafer carrier having provisions for improving heating uniformity in chemical vapor deposition systems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5366910A (en) * 1992-09-29 1994-11-22 Hyundai Electronics Industries Co., Ltd. Process for the production of thin film transistors using on SOG film
US5479316A (en) * 1993-08-24 1995-12-26 Analog Devices, Inc. Integrated circuit metal-oxide-metal capacitor and method of making same
US5468687A (en) * 1994-07-27 1995-11-21 International Business Machines Corporation Method of making TA2 O5 thin film by low temperature ozone plasma annealing (oxidation)
US5948216A (en) * 1996-05-17 1999-09-07 Lucent Technologies Inc. Method for making thin film tantalum oxide layers with enhanced dielectric properties and capacitors employing such layers
US6096597A (en) * 1997-01-31 2000-08-01 Texas Instruments Incorporated Method for fabricating an integrated circuit structure
US6461982B2 (en) * 1997-02-27 2002-10-08 Micron Technology, Inc. Methods for forming a dielectric film
US6204203B1 (en) * 1998-10-14 2001-03-20 Applied Materials, Inc. Post deposition treatment of dielectric films for interface control

Also Published As

Publication number Publication date
FR2797999A1 (fr) 2001-03-02
US6391802B1 (en) 2002-05-21

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Legal Events

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Effective date: 20090430