FR2797716B1 - Dispositif a semiconducteur sur un substrat soi - Google Patents

Dispositif a semiconducteur sur un substrat soi

Info

Publication number
FR2797716B1
FR2797716B1 FR0000042A FR0000042A FR2797716B1 FR 2797716 B1 FR2797716 B1 FR 2797716B1 FR 0000042 A FR0000042 A FR 0000042A FR 0000042 A FR0000042 A FR 0000042A FR 2797716 B1 FR2797716 B1 FR 2797716B1
Authority
FR
France
Prior art keywords
semiconductor device
soi substrate
soi
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0000042A
Other languages
English (en)
Other versions
FR2797716A1 (fr
Inventor
Takuji Matsumoto
Takashi Ipposhi
Yasuo Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2797716A1 publication Critical patent/FR2797716A1/fr
Application granted granted Critical
Publication of FR2797716B1 publication Critical patent/FR2797716B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
FR0000042A 1999-06-01 2000-01-04 Dispositif a semiconducteur sur un substrat soi Expired - Fee Related FR2797716B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11153904A JP2000340794A (ja) 1999-06-01 1999-06-01 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
FR2797716A1 FR2797716A1 (fr) 2001-02-23
FR2797716B1 true FR2797716B1 (fr) 2003-08-29

Family

ID=15572657

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0000042A Expired - Fee Related FR2797716B1 (fr) 1999-06-01 2000-01-04 Dispositif a semiconducteur sur un substrat soi

Country Status (3)

Country Link
US (1) US6249026B1 (fr)
JP (1) JP2000340794A (fr)
FR (1) FR2797716B1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338771B1 (ko) 1999-11-12 2002-05-30 윤종용 수소 어닐링 단계를 포함하는 공정이 간단한 트렌치소자분리방법
US6600173B2 (en) * 2000-08-30 2003-07-29 Cornell Research Foundation, Inc. Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US6596570B2 (en) * 2001-06-06 2003-07-22 International Business Machines Corporation SOI device with reduced junction capacitance
US6485992B1 (en) * 2001-07-03 2002-11-26 Memc Electronic Materials, Inc. Process for making wafers for ion implantation monitoring
JP5000057B2 (ja) * 2001-07-17 2012-08-15 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US7494901B2 (en) 2002-04-05 2009-02-24 Microng Technology, Inc. Methods of forming semiconductor-on-insulator constructions
JP4502632B2 (ja) * 2003-11-27 2010-07-14 京セラ株式会社 薄膜コンデンサ
JP4420196B2 (ja) * 2003-12-12 2010-02-24 三菱電機株式会社 誘電体分離型半導体装置およびその製造方法
US7384857B2 (en) * 2005-02-25 2008-06-10 Seiko Epson Corporation Method to fabricate completely isolated silicon regions
JP5003043B2 (ja) * 2005-10-26 2012-08-15 株式会社デンソー 半導体装置
US20080054361A1 (en) * 2006-08-30 2008-03-06 Infineon Technologies Ag Method and apparatus for reducing flicker noise in a semiconductor device
US7935632B2 (en) * 2007-11-06 2011-05-03 Chartered Semiconductor Manufacturing, Ltd. Reduced metal pipe formation in metal silicide contacts
KR20120133652A (ko) * 2011-05-31 2012-12-11 삼성전자주식회사 반도체 소자의 제조 방법
CN104217925B (zh) * 2013-06-05 2017-07-18 中国科学院微电子研究所 一种降低绝缘体上硅材料埋氧层中正电荷密度的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03149821A (ja) 1989-11-07 1991-06-26 Seiko Epson Corp 半導体装置の製造方法
JPH0547726A (ja) 1991-08-20 1993-02-26 Fujitsu Ltd 半導体装置の製造方法
JPH05217822A (ja) 1992-02-07 1993-08-27 Fujitsu Ltd シリコンオンインシュレータ基板の製造方法
TW297142B (fr) * 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
JPH08153880A (ja) * 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
JPH09246265A (ja) 1996-03-05 1997-09-19 Oki Electric Ind Co Ltd 半導体装置の素子分離膜及びその製造方法
JP3149821B2 (ja) 1997-06-27 2001-03-26 住友金属工業株式会社 連続鋳造方法

Also Published As

Publication number Publication date
US6249026B1 (en) 2001-06-19
JP2000340794A (ja) 2000-12-08
FR2797716A1 (fr) 2001-02-23

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Legal Events

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Effective date: 20130930