FR2933235B1 - Substrat bon marche et procede de fabrication associe - Google Patents

Substrat bon marche et procede de fabrication associe

Info

Publication number
FR2933235B1
FR2933235B1 FR0803701A FR0803701A FR2933235B1 FR 2933235 B1 FR2933235 B1 FR 2933235B1 FR 0803701 A FR0803701 A FR 0803701A FR 0803701 A FR0803701 A FR 0803701A FR 2933235 B1 FR2933235 B1 FR 2933235B1
Authority
FR
France
Prior art keywords
manufacturing
good
same
way substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0803701A
Other languages
English (en)
Other versions
FR2933235A1 (fr
Inventor
Bich Yen Nguyen
Carlos Mazure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0803701A priority Critical patent/FR2933235B1/fr
Priority to US12/469,436 priority patent/US8013417B2/en
Publication of FR2933235A1 publication Critical patent/FR2933235A1/fr
Application granted granted Critical
Publication of FR2933235B1 publication Critical patent/FR2933235B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24851—Intermediate layer is discontinuous or differential

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
FR0803701A 2008-06-30 2008-06-30 Substrat bon marche et procede de fabrication associe Active FR2933235B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0803701A FR2933235B1 (fr) 2008-06-30 2008-06-30 Substrat bon marche et procede de fabrication associe
US12/469,436 US8013417B2 (en) 2008-06-30 2009-05-20 Low cost substrates and method of forming such substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0803701A FR2933235B1 (fr) 2008-06-30 2008-06-30 Substrat bon marche et procede de fabrication associe

Publications (2)

Publication Number Publication Date
FR2933235A1 FR2933235A1 (fr) 2010-01-01
FR2933235B1 true FR2933235B1 (fr) 2010-11-26

Family

ID=40344771

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0803701A Active FR2933235B1 (fr) 2008-06-30 2008-06-30 Substrat bon marche et procede de fabrication associe

Country Status (2)

Country Link
US (1) US8013417B2 (fr)
FR (1) FR2933235B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11459725B2 (en) 2018-11-29 2022-10-04 Caterpillar Inc. Control system for a grading machine
US11459726B2 (en) 2018-11-29 2022-10-04 Caterpillar Inc. Control system for a grading machine
US11505913B2 (en) 2018-11-29 2022-11-22 Caterpillar Inc. Control system for a grading machine

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US5750000A (en) * 1990-08-03 1998-05-12 Canon Kabushiki Kaisha Semiconductor member, and process for preparing same and semiconductor device formed by use of same
DE4232844A1 (de) 1992-09-30 1994-03-31 Siemens Ag Belichtungsverfahren und Maske für die optische Projektionslithographie
US5399507A (en) * 1994-06-27 1995-03-21 Motorola, Inc. Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications
JP2647022B2 (ja) 1994-10-24 1997-08-27 日本電気株式会社 パターン形成方法
US5773151A (en) * 1995-06-30 1998-06-30 Harris Corporation Semi-insulating wafer
US6391744B1 (en) * 1997-03-19 2002-05-21 The United States Of America As Represented By The National Security Agency Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same
US6140163A (en) * 1997-07-11 2000-10-31 Advanced Micro Devices, Inc. Method and apparatus for upper level substrate isolation integrated with bulk silicon
US6063713A (en) * 1997-11-10 2000-05-16 Micron Technology, Inc. Methods for forming silicon nitride layers on silicon-comprising substrates
JP3523531B2 (ja) * 1999-06-18 2004-04-26 シャープ株式会社 半導体装置の製造方法
US6166411A (en) * 1999-10-25 2000-12-26 Advanced Micro Devices, Inc. Heat removal from SOI devices by using metal substrates
FR2810448B1 (fr) * 2000-06-16 2003-09-19 Soitec Silicon On Insulator Procede de fabrication de substrats et substrats obtenus par ce procede
JP4216483B2 (ja) * 2001-02-15 2009-01-28 株式会社東芝 半導体メモリ装置
US6645795B2 (en) * 2001-05-03 2003-11-11 International Business Machines Corporation Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator
US6912330B2 (en) * 2001-05-17 2005-06-28 Sioptical Inc. Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
US20020170487A1 (en) * 2001-05-18 2002-11-21 Raanan Zehavi Pre-coated silicon fixtures used in a high temperature process
US6547633B2 (en) * 2001-08-06 2003-04-15 Jill A. Haug Method of closing a stuffed toy
JP4322453B2 (ja) 2001-09-27 2009-09-02 株式会社東芝 半導体装置およびその製造方法
US6646307B1 (en) * 2002-02-21 2003-11-11 Advanced Micro Devices, Inc. MOSFET having a double gate
FR2838865B1 (fr) * 2002-04-23 2005-10-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
US6664598B1 (en) * 2002-09-05 2003-12-16 International Business Machines Corporation Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control
US6812527B2 (en) * 2002-09-05 2004-11-02 International Business Machines Corporation Method to control device threshold of SOI MOSFET's
US6835983B2 (en) * 2002-10-25 2004-12-28 International Business Machines Corporation Silicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness
US7176108B2 (en) * 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2847077B1 (fr) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
TWI265217B (en) * 2002-11-14 2006-11-01 Komatsu Denshi Kinzoku Kk Method and device for manufacturing silicon wafer, method for manufacturing silicon single crystal, and device for pulling up silicon single crystal
US6946373B2 (en) * 2002-11-20 2005-09-20 International Business Machines Corporation Relaxed, low-defect SGOI for strained Si CMOS applications
US7102206B2 (en) * 2003-01-20 2006-09-05 Matsushita Electric Industrial Co., Ltd. Semiconductor substrate, method for fabricating the same, and method for fabricating semiconductor device
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US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7018873B2 (en) * 2003-08-13 2006-03-28 International Business Machines Corporation Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate
FR2860341B1 (fr) * 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
US20070032040A1 (en) * 2003-09-26 2007-02-08 Dimitri Lederer Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
US7034362B2 (en) * 2003-10-17 2006-04-25 International Business Machines Corporation Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
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Also Published As

Publication number Publication date
FR2933235A1 (fr) 2010-01-01
US8013417B2 (en) 2011-09-06
US20090321872A1 (en) 2009-12-31

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