FR2912552B1 - Structure multicouche et son procede de fabrication. - Google Patents

Structure multicouche et son procede de fabrication.

Info

Publication number
FR2912552B1
FR2912552B1 FR0753260A FR0753260A FR2912552B1 FR 2912552 B1 FR2912552 B1 FR 2912552B1 FR 0753260 A FR0753260 A FR 0753260A FR 0753260 A FR0753260 A FR 0753260A FR 2912552 B1 FR2912552 B1 FR 2912552B1
Authority
FR
France
Prior art keywords
manufacturing
same
multilayer structure
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0753260A
Other languages
English (en)
Other versions
FR2912552A1 (fr
Inventor
Fabrice Letertre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0753260A priority Critical patent/FR2912552B1/fr
Priority to US11/899,340 priority patent/US7611974B2/en
Priority to EP08702336A priority patent/EP2111633A2/fr
Priority to PCT/IB2008/000201 priority patent/WO2008099246A2/fr
Priority to KR1020097014816A priority patent/KR101301771B1/ko
Priority to JP2009549858A priority patent/JP5380306B2/ja
Priority to CN2008800020084A priority patent/CN101584024B/zh
Publication of FR2912552A1 publication Critical patent/FR2912552A1/fr
Application granted granted Critical
Publication of FR2912552B1 publication Critical patent/FR2912552B1/fr
Priority to US12/564,147 priority patent/US7863650B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10P14/20—
    • H10P14/271—
    • H10P14/274—
    • H10P14/2905—
    • H10P14/3211—
    • H10P14/3216—
    • H10P14/3416—
    • H10P14/3421—
    • H10P90/1916—
    • H10W10/181—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V
FR0753260A 2007-02-14 2007-02-14 Structure multicouche et son procede de fabrication. Active FR2912552B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0753260A FR2912552B1 (fr) 2007-02-14 2007-02-14 Structure multicouche et son procede de fabrication.
US11/899,340 US7611974B2 (en) 2007-02-14 2007-09-05 Multilayer structure and fabrication thereof
PCT/IB2008/000201 WO2008099246A2 (fr) 2007-02-14 2008-01-28 Structure multicouche et son processus de fabrication
KR1020097014816A KR101301771B1 (ko) 2007-02-14 2008-01-28 다중층 구조 및 그 제조 프로세스
EP08702336A EP2111633A2 (fr) 2007-02-14 2008-01-28 Structure multicouche et son processus de fabrication
JP2009549858A JP5380306B2 (ja) 2007-02-14 2008-01-28 多層構造及びその製造プロセス
CN2008800020084A CN101584024B (zh) 2007-02-14 2008-01-28 多层结构及其制备工艺
US12/564,147 US7863650B2 (en) 2007-02-14 2009-09-22 Multilayer structure and fabrication thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0753260A FR2912552B1 (fr) 2007-02-14 2007-02-14 Structure multicouche et son procede de fabrication.

Publications (2)

Publication Number Publication Date
FR2912552A1 FR2912552A1 (fr) 2008-08-15
FR2912552B1 true FR2912552B1 (fr) 2009-05-22

Family

ID=38565526

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0753260A Active FR2912552B1 (fr) 2007-02-14 2007-02-14 Structure multicouche et son procede de fabrication.

Country Status (7)

Country Link
US (2) US7611974B2 (fr)
EP (1) EP2111633A2 (fr)
JP (1) JP5380306B2 (fr)
KR (1) KR101301771B1 (fr)
CN (1) CN101584024B (fr)
FR (1) FR2912552B1 (fr)
WO (1) WO2008099246A2 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2912552B1 (fr) 2007-02-14 2009-05-22 Soitec Silicon On Insulator Structure multicouche et son procede de fabrication.
US8299485B2 (en) 2008-03-19 2012-10-30 Soitec Substrates for monolithic optical circuits and electronic circuits
DE102009051520B4 (de) 2009-10-31 2016-11-03 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von Siliziumhalbleiterscheiben mit Schichtstrukturen zur Integration von III-V Halbleiterbauelementen
US9190269B2 (en) * 2010-03-10 2015-11-17 Purdue Research Foundation Silicon-on-insulator high power amplifiers
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
US9329336B2 (en) 2012-07-06 2016-05-03 Micron Technology, Inc. Method of forming a hermetically sealed fiber to chip connection
EP2685297B1 (fr) * 2012-07-13 2017-12-06 Huawei Technologies Co., Ltd. Procédé de fabrication d'un circuit photonique avec structures actives et passives
JP6087192B2 (ja) * 2013-04-03 2017-03-01 京セラ株式会社 発電システムおよび発電システムの制御方法ならびに燃料電池
US9698046B2 (en) 2015-01-07 2017-07-04 International Business Machines Corporation Fabrication of III-V-on-insulator platforms for semiconductor devices
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
TWI894863B (zh) * 2016-06-14 2025-08-21 美商克若密斯股份有限公司 用於功率及rf應用的工程基板結構
US10297445B2 (en) 2016-06-14 2019-05-21 QROMIS, Inc. Engineered substrate structure for power and RF applications
US10510582B2 (en) 2016-06-14 2019-12-17 QROMIS, Inc. Engineered substrate structure
EP4046195A4 (fr) * 2019-10-18 2023-11-08 Psiquantum Corp. Dispositif électro-optique fabriqué sur un substrat et comprenant une couche ferroélectrique à croissance épitaxiale sur le substrat
US12136682B2 (en) 2021-09-29 2024-11-05 International Business Machines Corporation Device integration using carrier wafer
US11677039B2 (en) 2021-11-18 2023-06-13 International Business Machines Corporation Vertical silicon and III-V photovoltaics integration with silicon electronics

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3914137A (en) * 1971-10-06 1975-10-21 Motorola Inc Method of manufacturing a light coupled monolithic circuit by selective epitaxial deposition
JPS5116928B2 (fr) * 1972-06-12 1976-05-28
JPS60210832A (ja) * 1984-04-04 1985-10-23 Agency Of Ind Science & Technol 化合物半導体結晶基板の製造方法
US4876210A (en) * 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
AU623601B2 (en) * 1987-08-08 1992-05-21 Canon Kabushiki Kaisha Method for growth of crystal
US5286985A (en) * 1988-11-04 1994-02-15 Texas Instruments Incorporated Interface circuit operable to perform level shifting between a first type of device and a second type of device
DE68915529T2 (de) * 1989-01-31 1994-12-01 Agfa Gevaert Nv Integration von GaAs auf Si-Unterlage.
FR2807909B1 (fr) 2000-04-12 2006-07-28 Centre Nat Rech Scient COUCHE MINCE SEMI-CONDUCTRICE DE GaInN, SON PROCEDE DE PREPARATION; DEL COMPRENANT CETTE COUCHE ET DISPOSITIF D'ECLAIRAGE COMPRENANT CETTE DEL
FR2810159B1 (fr) 2000-06-09 2005-04-08 Centre Nat Rech Scient Couche epaisse de nitrure de gallium ou de nitrure mixte de gallium et d'un autre metal, procede de preparation, et dispositif electronique ou optoelectronique comprenant une telle couche
US6677655B2 (en) 2000-08-04 2004-01-13 Amberwave Systems Corporation Silicon wafer with embedded optoelectronic material for monolithic OEIC
FR2832224B1 (fr) 2001-11-15 2004-01-16 Commissariat Energie Atomique Dispositif electronique monolithique multicouches et procede de realisation d'un tel dispositif
US20040012037A1 (en) * 2002-07-18 2004-01-22 Motorola, Inc. Hetero-integration of semiconductor materials on silicon
JP3966207B2 (ja) * 2003-03-28 2007-08-29 豊田合成株式会社 半導体結晶の製造方法及び半導体発光素子
JP2004335837A (ja) * 2003-05-09 2004-11-25 Matsushita Electric Ind Co Ltd 半導体基板の製造方法
EP1973155B1 (fr) * 2004-11-19 2011-07-06 S.O.I. TEC Silicon Procédé de fabrication d'une plaquette de type germanium sur isolant (GeOI)
FR2912552B1 (fr) 2007-02-14 2009-05-22 Soitec Silicon On Insulator Structure multicouche et son procede de fabrication.

Also Published As

Publication number Publication date
JP2010519741A (ja) 2010-06-03
KR20090110836A (ko) 2009-10-22
KR101301771B1 (ko) 2013-09-02
FR2912552A1 (fr) 2008-08-15
JP5380306B2 (ja) 2014-01-08
CN101584024A (zh) 2009-11-18
US20080191239A1 (en) 2008-08-14
WO2008099246A3 (fr) 2008-10-30
EP2111633A2 (fr) 2009-10-28
CN101584024B (zh) 2011-11-30
WO2008099246A2 (fr) 2008-08-21
US7611974B2 (en) 2009-11-03
US7863650B2 (en) 2011-01-04
US20100006857A1 (en) 2010-01-14

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