DE68915529T2 - Integration von GaAs auf Si-Unterlage. - Google Patents

Integration von GaAs auf Si-Unterlage.

Info

Publication number
DE68915529T2
DE68915529T2 DE68915529T DE68915529T DE68915529T2 DE 68915529 T2 DE68915529 T2 DE 68915529T2 DE 68915529 T DE68915529 T DE 68915529T DE 68915529 T DE68915529 T DE 68915529T DE 68915529 T2 DE68915529 T2 DE 68915529T2
Authority
DE
Germany
Prior art keywords
gaas
integration
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68915529T
Other languages
English (en)
Other versions
DE68915529D1 (de
Inventor
Piet Marie Demeester
Ann Marie Ackaert
Daele Peter Paul Van
Dirk Urbain Lootens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agfa Gevaert NV
Original Assignee
Agfa Gevaert NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agfa Gevaert NV filed Critical Agfa Gevaert NV
Publication of DE68915529D1 publication Critical patent/DE68915529D1/de
Application granted granted Critical
Publication of DE68915529T2 publication Critical patent/DE68915529T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)
  • Recrystallisation Techniques (AREA)
DE68915529T 1989-01-31 1989-01-31 Integration von GaAs auf Si-Unterlage. Expired - Fee Related DE68915529T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP89200205A EP0380815B1 (de) 1989-01-31 1989-01-31 Integration von GaAs auf Si-Unterlage

Publications (2)

Publication Number Publication Date
DE68915529D1 DE68915529D1 (de) 1994-06-30
DE68915529T2 true DE68915529T2 (de) 1994-12-01

Family

ID=8202308

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68915529T Expired - Fee Related DE68915529T2 (de) 1989-01-31 1989-01-31 Integration von GaAs auf Si-Unterlage.

Country Status (4)

Country Link
US (1) US5108947A (de)
EP (1) EP0380815B1 (de)
JP (1) JP2954958B2 (de)
DE (1) DE68915529T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256594A (en) * 1989-06-16 1993-10-26 Intel Corporation Masking technique for depositing gallium arsenide on silicon
US5212112A (en) * 1991-05-23 1993-05-18 At&T Bell Laboratories Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets
FR2682128B1 (fr) * 1991-10-08 1993-12-03 Thomson Csf Procede de croissance de couches heteroepitaxiales.
US5443685A (en) * 1993-11-01 1995-08-22 At&T Corp. Composition and method for off-axis growth sites on nonpolar substrates
GB0220438D0 (en) * 2002-09-03 2002-10-09 Univ Warwick Formation of lattice-turning semiconductor substrates
DE102005004582A1 (de) 2005-01-26 2006-07-27 Philipps-Universität Marburg III/V-Halbleiter
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
WO2008039534A2 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
FR2912552B1 (fr) * 2007-02-14 2009-05-22 Soitec Silicon On Insulator Structure multicouche et son procede de fabrication.
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US9508890B2 (en) * 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
KR101093588B1 (ko) 2007-09-07 2011-12-15 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 멀티-정션 솔라 셀
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
CN102160145B (zh) 2008-09-19 2013-08-21 台湾积体电路制造股份有限公司 通过外延层过成长的元件形成
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
JP5705207B2 (ja) 2009-04-02 2015-04-22 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． 結晶物質の非極性面から形成される装置とその製作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598823A (en) * 1979-01-20 1980-07-28 Tdk Corp Manufacture of single crystal element
JPS61189619A (ja) * 1985-02-18 1986-08-23 Sharp Corp 化合物半導体装置
JPS62213117A (ja) * 1986-03-13 1987-09-19 Oki Electric Ind Co Ltd 半導体素子の製造方法
US4774205A (en) * 1986-06-13 1988-09-27 Massachusetts Institute Of Technology Monolithic integration of silicon and gallium arsenide devices
JPS63108709A (ja) * 1986-10-25 1988-05-13 Toyota Central Res & Dev Lab Inc 半導体装置およびその製造方法
US4914053A (en) * 1987-09-08 1990-04-03 Texas Instruments Incorporated Heteroepitaxial selective-area growth through insulator windows
JPS6490518A (en) * 1987-10-01 1989-04-07 Mitsubishi Electric Corp Formation of gaas epitaxial layer
US4826784A (en) * 1987-11-13 1989-05-02 Kopin Corporation Selective OMCVD growth of compound semiconductor materials on silicon substrates
US4940672A (en) * 1989-03-17 1990-07-10 Kopin Corporation Method of making monolithic integrated III-V type laser devices and silicon devices on silicon

Also Published As

Publication number Publication date
DE68915529D1 (de) 1994-06-30
JP2954958B2 (ja) 1999-09-27
EP0380815A1 (de) 1990-08-08
EP0380815B1 (de) 1994-05-25
US5108947A (en) 1992-04-28
JPH03114222A (ja) 1991-05-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee