US20080187018A1 - Distributed feedback lasers formed via aspect ratio trapping - Google Patents

Distributed feedback lasers formed via aspect ratio trapping Download PDF

Info

Publication number
US20080187018A1
US20080187018A1 US11/875,177 US87517707A US2008187018A1 US 20080187018 A1 US20080187018 A1 US 20080187018A1 US 87517707 A US87517707 A US 87517707A US 2008187018 A1 US2008187018 A1 US 2008187018A1
Authority
US
United States
Prior art keywords
openings
plurality
diffraction grating
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/875,177
Inventor
Jizhong Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AmberWave Systems Corp
Original Assignee
AmberWave Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US85278106P priority Critical
Application filed by AmberWave Systems Corp filed Critical AmberWave Systems Corp
Priority to US11/875,177 priority patent/US20080187018A1/en
Assigned to AMBERWAVE SYSTEMS CORPORATION reassignment AMBERWAVE SYSTEMS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LI, JIZHONG
Publication of US20080187018A1 publication Critical patent/US20080187018A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647Lateral overgrowth
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223Buried stripe structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223Buried stripe structure
    • H01S5/2237Buried stripe structure with a non-planar active layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0207Substrates having a special shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/021Silicon based substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0218Substrates comprising semiconducting materials from different groups of the periodic system than the active layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223Buried stripe structure
    • H01S5/2232Buried stripe structure with inner confining structure between the active layer and the lower electrode
    • H01S5/2234Buried stripe structure with inner confining structure between the active layer and the lower electrode having a structured substrate surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave; Confining structures perpendicular to the optical axis, e.g. index- or gain-guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3202Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures grown on specifically orientated substrates, or using orientation dependent growth

Abstract

Structures including dielectric diffraction gratings. In some embodiments, laser devices include diffraction gratings defined by openings formed in a dielectric material.

Description

    RELATED APPLICATION
  • This application claims priority to U.S. Provisional Patent Application Ser. No. 60/852,781, filed Oct. 19, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
  • FIELD OF THE INVENTION
  • This invention relates generally to semiconductor processing and particularly to formation of light-emitting devices based on lattice-mismatched semiconductor structures.
  • BACKGROUND
  • Distributed feedback (DFB) lasers with stable longitudinal single-mode operation are critical for applications such as optical-information processing, interferometric measuring, holographic printing, optical gas sensing, atomic spectroscopy and medical diagnoses. Examples of various DFB lasers are shown and described in U.S. Pat. Nos. 5,295,150 and 5,953,361 and articles such as Japanese Journal of Applied Physics, Vol. 43, No. 4B, 2004, pp. 2019-2022, Japanese Journal of Applied Physics Vol. 44, No. 4B, 2005, pp. 2546-2548, and Journal of Crystal Growth 261 (2004) 349-354, incorporated herein by reference in their entireties.
  • In order to obtain a longitudinal single-mode output, a buried grating structure design is widely used to introduce a periodic refractive index change in the active region of the laser, i.e., the portion of the laser in which light is propagated. This grating structure selectively reflects a certain Bragg wavelength in the laser gain spectrum. By adjusting the grating pitch and the refractive index, single-mode lasing can be realized. Currently, commercial 0.7-2.0 micrometer (μm) DFB lasers are mainly fabricated by employing MOCVD-based two-step growth methods that have several technical challenges. Firstly, conventional holography and chemical wet etching are generally used for grating formation on GaAs or InP-based substrates or pre-growth layers. Since DFB performance characteristics are sensitive to grating pitch width, depth, surface morphology and shape profile, it is a technical challenge to meet specific wavelength requirements without comprehensive process optimization. Furthermore, epitaxial re-growth on a wafer surface having a grating disposed thereon is a common procedure to complete full DFB structure formation. It is well known that mass transport and grated surface oxidation (particularly for laser structures containing Al) are significant issues affecting device performance. Finally, conventional DFB lasers in the wavelength range of 700 nanometer (nm)-2000 nm are primarily fabricated using GaAs or InP as substrates. The costs of laser devices fabricated from non-silicon (Si) wafers are high due to the high cost of the wafers and the inherent low processing yields of laser devices.
  • SUMMARY OF THE INVENTION
  • Embodiments of the present invention include systems and methods for providing DFB laser structures on lattice-mismatched semiconductor substrates, e.g., Si, by employing aspect ratio trapping (ART) growth methods. The following benefits are provided by various embodiments.
  • Low-cost Si may be used as the substrate. Si-based device fabrication technology is more mature than that of III-V compound materials. In addition to significant wafer cost reduction, adapting large-wafer Si processing techniques for III-V laser device processing may enhance the DFB fabrication reliability and product yield, thus leading to better device performance and further reduction of fabrication cost. In addition, a Si substrate has better thermal conductivity and a higher physical hardness than conventional GaAs and InP materials. Using Si as a substrate therefore improves heat depletion control and device packaging.
  • Furthermore, it may be advantageous to use dielectric sidewalls defined by ART techniques for selective growth as well as for the grating media. In these embodiments, a dielectric mask has multiple functions. First, it enables trapping dislocation defects within a very thin transition layer. These defects are generated at an interface between different materials, e.g., a III-V/Si interface, due to lattice mismatch and thermal-expansion differences between Si and III-V compounds. By employing an ART-based surface engineering process, device-quality laser materials may be grown on lattice-mismatched, e.g., Si, substrates.
  • Second, since interface defects are trapped toward a bottom portion of the trench, the grating profile may be formed in an upper portion of epitaxial films, e.g., III-V materials, by utilizing a dielectric (e.g., oxide) pattern as an optical grating media. Since the first or second order grating pitch width for commonly used DFB lasers is on a submicron scale, ART masks have a good dimensional match to the grating pitch requirements for making DFB lasers.
  • Another benefit is that ART patterning can provide a large refractive index difference between the dielectric material, e.g., SiO2 (1.46), and the epitaxially grown material, e.g., GaAs (3.2). This refractive index difference is larger than the refractive index difference between conventionally used materials such as GaAs and AlGaAs, and leads to a high optical coupling constant. The simplified grating formation procedure, which avoids a re-growth process, is another significant benefit in comparison to conventional methods of forming DFB structures.
  • The use of well developed integrated circuit (IC) processes for forming the grating pattern allows for flexibility in grating geometry because selection of grating duty cycle and the variation of grating pitches can be realized in an initial photolithography process. This offers advantages over conventional post-growth holographic techniques.
  • The approaches described herein for realizing III-V/Si integration coupled with integration with conventional Si-based process enable a variety of other benefits as well, such as accommodating chip-scale integration of DFB lasers with other electronic devices.
  • In an aspect, the invention features a method of making a laser diode. The method includes forming a dielectric layer over a top surface of the substrate including a first semiconductor material. A plurality of openings are defined in the dielectric layer, with the openings extending to the top surface of the substrate. A second semiconductor material is formed in the openings. A plurality of layers are defined over the second semiconductor material and the dielectric layer to form the laser diode, with portions of the dielectric layer defining a diffraction grating.
  • One or more of the following features may be included. The diffraction grating may have a width and a spacing selected to provide a duty cycle ranging from 20% to 50%. Defining the plurality of openings may include reactive ion etching. Forming the second semiconductor material may include selective epitaxy. The first semiconductor material may include silicon and the second semiconductor material may include a III-V compound and/or a II-VI compound. The plurality of semiconductor layers may include a cladding layer, a grating layer, a graded spacer layer, a graded confining layer, a quantum well region, and/or a cap layer. The laser diode may be a distributed feedback laser diode.
  • A bottom contact layer may be defined over a bottom surface of the substrate. A bottom portion of the second semiconductor material may include lattice-mismatch defects and a top portion of the second semiconductor material may be substantially free of lattice-mismatch defects. Each of the openings may have a height sufficient for trapping a majority of the lattice-mismatch defects within the opening. Each of the plurality of openings may have a width less than or equal to a height thereof.
  • In another aspect, the invention features a semiconductor device. The semiconductor device includes a plurality of openings defined in a dielectric layer disposed above a crystalline substrate comprising a first semiconductor material. A diffraction grating defined by portions of the dielectric layer is disposed between the openings. A second crystalline material is disposed within each of the openings, the second crystalline material having a lattice mismatch with the substrate, and a majority of defects arising from lattice mismatch between the second material and the substrate exiting at a surface of the second material within each of the openings. A plurality of semiconductor layers are disposed above the second crystalline material and the diffraction grating, the plurality of semiconductor layers forming a laser diode.
  • One or more of the following features may be included. The first semiconductor material may include or consist essentially of silicon. The second crystalline material may include a III-V compound and/or a II-VI compound. The diffraction grating may provide a duty cycle ranging from 20% to 50%. The laser diode may be a distributed feedback laser.
  • In another aspect, the invention features a distributed feedback laser device including a dielectric diffraction grating disposed over a crystalline substrate and a plurality of layers disposed above the diffraction grating. The layers define a laser diode, and at least some of the layers comprise a III-V material lattice-mismatched to the crystalline substrate.
  • One or more of the following features may be included. The diffraction grating may include a dielectric layer defining a plurality of openings. A crystalline material may be disposed within the openings, the crystalline material having a lattice constant mismatched to a lattice constant of the crystalline substrate. A contact may be disposed on a bottom side of the crystalline substrate. An input electrode and an output electrode may be disposed on a single side of the crystalline substrate. A top portion of the crystalline material may be substantially free of defects. The crystalline substrate may include a group IV material.
  • In another aspect, the invention features a method of making a laser diode. The method includes forming a dielectric layer over a crystalline substrate including a first semiconductor material. A first diffraction grating is formed by defining a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength. A second diffraction grating is formed by defining a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength. A plurality of layers is defined over the first and second diffraction gratings to form the laser diode.
  • In yet another aspect, the invention features a distributed feedback laser device. The distributed feedback laser device includes a dielectric layer disposed over a crystalline substrate including a first semiconductor material. A first diffraction grating is defined by a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength. A second diffraction grating is defined by a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength. A plurality of layers disposed over the first and second diffraction gratings define a distributed feedback laser device active region.
  • BRIEF DESCRIPTION OF FIGURES
  • In the drawings, like reference characters generally refer to the same features throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the aspects of the invention.
  • FIGS. 1-4 are schematic cross-sectional view illustrating structures formed in accordance with an embodiment of the invention.
  • DETAILED DESCRIPTION
  • Referring to FIG. 1, a method for forming a relatively low defect or defect-free semiconductor material on a lattice-mismatched substrate is illustrated. A substrate 100 includes a first crystalline semiconductor material S1. The substrate 100 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. The substrate 100 may include or consist essentially of the first semiconductor material S1, such as a group IV element, e.g., germanium or silicon. In an embodiment, substrate 100 includes or consists essentially of n-type (100) silicon. The substrate 100 may include a material having a first conductivity type, e.g., n+Si.
  • A dielectric layer 110 is formed over the semiconductor substrate 100. The dielectric layer 110 may include or consist essentially of a dielectric material, such as silicon nitride or silicon dioxide. The dielectric layer 110 may be formed by any suitable technique, e.g., thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD). As discussed below, the dielectric layer may have a thickness t1 corresponding to a desired height h of crystalline material to be deposited in an opening formed through the dielectric layer. In some embodiments, the thickness t1 of the dielectric layer 110 may be in the range of, e.g., 25-1000 nm. In a preferred embodiment, the thickness t1 is 600 nm.
  • A mask (not shown), such as a photoresist mask, is formed over the substrate 100 and the dielectric layer 110. The mask is patterned to expose at least a portion of the dielectric layer 110. The exposed portion of the dielectric layer 110 is removed by, e.g., reactive ion etching (RIE) to define an opening 120. Opening 120 may be defined by at least one sidewall 130, and may extend to a top surface 135 of the substrate 100. The height h of the sidewall 130 corresponds to the thickness t1 of the dielectric layer 110, and may be at least equal to a predetermined distance H from a top surface 135 of the substrate.
  • The opening may be substantially rectangular in terms of cross-sectional profile, a top view, or both, and have a width w that is smaller than the length l (not shown) of the opening. For example, the width w of the opening may be less than about 500 nm, e.g., about 10-500 nm, and the length l of the opening may exceed each of w and H. The ratio of the height h of the opening to the width w of the opening 120 may be ≧0.5, e.g., ≧1. The opening sidewall 130 is configured to allow defects that arise within the material S2 to exit the material below the height h as described below. The opening sidewall 130 is not necessarily strictly vertical.
  • A second crystalline semiconductor material S2, i.e., crystalline material 140, is formed in the opening 120. The crystalline material 140 may include or consist essentially of a group IV element or compound, a III-V compound, or a II-VI compound. Examples of suitable group IV elements or compounds include germanium, silicon germanium, and silicon carbide. Examples of suitable III-V compounds include gallium antimonide, gallium arsenide, gallium nitride, gallium phosphide, aluminum antimonide, aluminum arsenide, aluminum nitride, aluminum phosphide, indium antimonide, indium arsenide, indium nitride, indium phosphide, and their ternary or quaternary compounds such as indium gallium arsenide, indium gallium nitride, indium gallium phosphide, etc. Examples of suitable II-VI compounds include zinc selenide, zinc sulfide, cadmium selenide, cadmium sulfide, and their ternary or quaternary compounds.
  • The crystalline material 140 may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen. The reactor chamber may be heated by, for example, RF-heating. The growth temperature in the chamber may range from about 300° C. to about 900° C., depending on the composition of the crystalline material. The growth system may also utilize low-energy plasma to enhance the layer growth kinetics.
  • The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif.; or an EPSILON single-wafer epitaxial reactor available from ASM International based in Bilthoven, The Netherlands.
  • In an exemplary process, a two-step growth technique is used to form high-quality crystalline material 140, consisting essentially of GaAs, in the opening 120. First, the substrate 100 and dielectric layer 110 are thermally annealed with hydrogen at approximately 800° C. for approximately 15 minutes to desorb a thin volatile oxide from that substrate surface 135 that may be produced during pre-epitaxy wafer preparation. Chamber pressure during annealing may be in the range of approximately 50-100 Torr, for example 75 Torr. After annealing, the chamber temperature is cooled down with hydrogen flow. In order to suppress anti-phase boundaries (APDs) on substrate surface 135, a pre-exposure to As for about 1 to 5 minutes is performed. This step helps ensure uniform coverage of the opening surface with an As—As monolayer. This pre-exposure is achieved by flowing AsH3 gas through the reactor at a temperature of approximately 460° C. Then, a gallium precursor, e.g., triethylgallium (TEG) or trimethylgallium (TMG), is introduced into the chamber together with AsH3 gas at a lower growth temperature, e.g., approximately 400° C. to 450° C. to promote the initial GaAs nucleation process on the As pre-layer surface. A slow growth rate of about 2 to 4 nm per minute with V/III ratio of about 50 may be used to obtain this initial GaAs buffer layer, with a thickness of the GaAs buffer layer being selected from a range of about 20 to 100 nm.
  • In one embodiment, a layer of n-type GaAs is grown above the buffer layer at a constant growth temperature of approximately 680° C. and a V/III ratio of approximately 80 to obtain relatively defect-free GaAs material inside the opening 120. The combined thickness t2 of the initial GaAs buffer layer and the n-type GaAs grown above the buffer layer may be less than or greater than the dielectric mask thickness t1. The top portion of the GaAs material may coalesce with GaAs formed in neighboring openings (not shown) to form an epitaxial layer. The width w2 of the crystalline material 140 extending over a top surface 160 of the dielectric layer 110 may be greater than the width w of the opening 120. The overall layer thickness t2 of the crystalline material 140 may be monitored by using pre-calibrated growth rates and in situ monitoring equipment, according to methods known in the art.
  • Dislocation defects 150 in the crystalline material 140 reach and terminate at the sidewalls of the opening 120 in the dielectric material 110 at or below the predetermined distance H from the surface 135 of the substrate, such that dislocations in the crystalline material 140 decrease in density with increasing distance from the bottom portion of the opening 120. Accordingly, the upper portion of the crystalline material has a substantially reduced number of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may thus be generally eliminated from the upper portion of the crystalline material.
  • The crystalline material 140 may be considered to have two portions: a lower portion for trapping dislocation defects and an upper portion which either (a) incorporates the laser or LED epitaxial layers or (b) serves as a template for the subsequent epitaxial growth of the laser or LED epitaxial layers. The height h of the crystalline material thus has two components: the height htrapping of the lower portion (where defects are concentrated) and the height hupper of the upper portion (which is largely free of defects). The height htrapping of the trapping portion may be selected from a range of about ½w≦htrapping≦2w, to ensure effective trapping of dislocation defects. The actual value of htrapping required may depend upon the type of dislocation defects encountered, which may depend on the materials used, and also upon the orientation of the opening sidewalls. In some instances, the height htrapping can be greater than that required for effective defect trapping, in order to ensure that the dislocation defects are trapped at a sufficient distance away from the upper portion, so that deleterious effects of dislocation defects upon device performance are not experienced. For example, htrapping may be, e.g., 10-100 nm greater than required for effective trapping of defects. For the upper portion, the height hupper may be selected from the range of approximately ½w≦hupper≦10 w.
  • Referring to FIGS. 2 a and 2 b, in an exemplary embodiment, the process described with respect to FIG. 1 is used to form a laser diode 200, e.g., a DFB laser diode that emits optical radiation at a wavelength less than 880 nm. The laser diode 200 is formed over the crystalline material 140. The laser diode 200 includes a plurality of openings 120 with dielectric layer 110 portions, i.e., ridges, disposed between the openings 120. The dielectric layer 110 is patterned to define a series of ridges defining a grid layer that forms a diffraction grating 210 of the laser structure 200.
  • The laser diode 200 includes a number of layers that may be formed by epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, MOCVD, APCVD, LPCVD, UHVCVD, MBE, or ALD.
  • More particularly, laser diode 200 comprises a substrate 100 that includes a semiconductor material of one conductivity type. The described embodiment has an n-type substrate, including n+ type Si. One of skill in the art will recognize that other embodiments are possible including, e.g., other material compositions and conductivity types. The substrate 100 has a top surface 220 and a bottom surface 230. The diffraction grating 210 is defined by dielectric layer 110 portions formed on the top substrate surface 220. The openings 120 of the diffraction grating 210 have a selected width and a spacing ratio (duty cycle) ranging from 20% to 50% and preferably from 35% to 40%. The duty cycle is a ratio of the width of a dielectric ridge to the grating pitch, with the grating pitch Λ being equal to a sum of the opening width w and the spacing d between openings 120 (with spacing d being equal to a width of a diffraction grating 210 ridge.) For example, the width w of each opening 120 may be 250 nm and a spacing d between openings 120 may be 200 nm. The grating pitch Λ determines the wavelength λ of the laser diode 200, such that λ=2neΛ/m, where ne is the effective refractive index of grating layer 270, and m is an integer greater than zero (1, first order; 2, second order, . . . ).
  • To use the substrate as an electrical contact medium, the electrical conductivity (i.e., doping) type of the material initially formed on the substrate, e.g., the initial III-V materials on Si, should be the same as that of the substrate. In one embodiment, crystalline material 140 may include a low temperature buffer layer such as n-type GaAs deposited onto the exposed top Si surface 220. The GaAs buffer layer has a thickness of about 15 nm to 30 nm with a preferred n-type doping level of about 2×1018/cm3.
  • A first cladding layer 268 including n-type Al0.6Ga0.4As is grown on the crystalline material 140 at an elevated temperature to a doping level of 0.2-2×1018/cm3, with a preferred thickness of between 0.2-0.8 μm. The combined thickness of the crystalline material 140 and the first cladding layer 268 disposed within the openings 120 is less than a height of the grid layer.
  • A grating layer 270 is grown on the first cladding layer 268. The grating layer 270 may include n-type Al0.4Ga0.6As. The grating layer 270 is n-type doped at a doping level of between 2×1016/cm3 to 5×1018/cm3 and preferably about 5×1017/cm3. The grating layer 270 has a thickness of between about 20 and 500 nm, preferably about 120 nm. Since the grating layer 270 is partially grown inside the openings 120 and continuously grown after coalescence over the dielectric grids 110, the top parts of the dielectric grids defined by dielectric layer 110 portions are surrounded by the grating layer 270.
  • A graded spacer layer 272 is grown on the grating layer 270. The graded spacer layer 272 includes AlGaAs, preferably Al0.6Ga0.4As at the surface of grating layer and Al0.4Ga0.6As away from the grating layer 270. The spacer layer 272 is n-doped with a doping level of between 2×1016/cm3 to 5×1018/cm3 and preferably about 5×1017/cm3. The spacer layer 272 has a thickness selected from a range of between about 20 and 500 nm, preferably about 100 nm.
  • A graded first confining layer 274, i.e., a first waveguide, of undoped Al0.60-0.20Ga0.40-0.80As is formed over the graded spacer layer 272. The graded first confining layer 274 has a thickness selected from a range of between about 20 and 400 nm, preferably about 120 nm.
  • An active layer (also referred to herein as active region), including a multi-quantum well region 280 is formed over graded first confining layer 274. Referring also to FIG. 3, the multi-quantum well region 280 includes a first quantum well layer 276 of undoped GaAs having a thickness of, e.g., about 3 to 7 nm. Disposed over the first quantum well layer 276 is a barrier layer 275 of Al0.05-0.60Ga0.40-0.95As, preferably Al0.25Ga0.75As. The barrier layer 275 has a thickness of between 5 and 100 nm, and preferably has a thickness of 40 nm. A second quantum well layer 278 of undoped GaAs is disposed over the barrier layer 275. The second quantum well layer 278 has a thickness of about 3-7 nm.
  • A graded second confining layer 282, i.e., a second waveguide, of undoped Al0.20-0.60Ga0.80-0.40As is formed over the second quantum well layer 278. The graded second confining layer 282 has a thickness of between about 20 and 400 nm and preferably 120 nm.
  • A second cladding layer 284 is formed over the graded second confining layer 282. The second cladding layer 284 is graded p-type, and includes Al0.4-0.6Ga0.6-0.4As as the second confining layer, with a higher content Al at the surface away from the graded second confining layer 282. The second cladding layer 284 is p-type doped with, e.g., carbon, zinc, or magnesium to a level of between 1×1017 cm−3 to 5×1018 cm−3, and has a thickness of between 300 nm and 3000 nm, preferably 1000 nm.
  • The illustrated configuration forms a single mode laser with the indicated optical field distribution 285.
  • A p+ type cap layer 286 of GaAs is grown over the second cladding layer 284. The cap layer 286 is doped to a level of between 5×1017 cm−3 to 5×1020 cm−3, and preferably about 1-3×1019 cm−3, and has a thickness of between 10 nm and 500 nm, preferably about 300 nm thick.
  • A pair of spaced parallel grooves 288 (see FIG. 2 a) is formed in the cap layer 286 by photolithography and etch steps. The grooves 288 extend between the ends of the laser diode 200. The grooves 288 are spaced apart at a distance of about 1 μm to 10 μm and preferably about 10 μm, and extend into the second cladding layer 284 by a sufficient extent to restrict lateral transverse modes. An encapsulating layer 290 of an insulating material, such as SiO2 or SiNx is deposited over cap layer 286 and the surface of the grooves 288. The encapsulating layer 290 has an opening 292 formed therethrough over a portion of the cap layer 286 disposed between the grooves 288. A conducting top contact layer (electrode) 294, e.g., a p-type contact layer is formed over the insulating layer 290 and extends through the opening 292 to contact the surface of the cap layer 286. The conducting top contact layer 294 may be formed by, e.g., deposition, sputtering, or evaporation. The conducting top contact layer 294 includes a material that makes good electrical contact to the material of the cap layer 286, e.g., a Ti/Pt/Au tri-layer.
  • In an embodiment, an electrically insulated diode (EID) structure may be added (not shown).
  • After thinning the backside of the substrate by conventional wafer thinning techniques, preferably to 100 μm, a conducting bottom contact layer (electrode) 296 is formed on the bottom surface 230 of the substrate 100 by, e.g., deposition or evaporation. The conducting bottom contact layer 296 is formed from a material that makes good electrical contact to the material of the substrate 100; in a preferred embodiment, the conducting bottom contact layer 296 includes a tri-layer of AuGe/Ni/Au with n-type conductivity.
  • Referring to FIG. 2 c, input and output electrical contacts (electrodes) may be also fabricated on a single side, i.e., the same side, of the substrate to improve electrical pumping efficiency and to reduce optical coupling loss at the III-V/Si interface. This can be realized by techniques known to one of skill in the field, such as by use of an etch-stop layer (not shown) inserted between the graded first confining layer (waveguide) 274 and graded spacer layer 272, which are disposed between the active region or multiple quantum well 280 and the grating layer 270, as shown in FIG. 2 c. For example, after the formation of the cap layer 286 and grooves 288, portions of overlying materials may be removed by deep trench etching to expose a region of graded spacer layer 272. A dielectric insulator 291 is deposited to protect a sidewall exposed by the removed portions of overlying material, as well as to cover an exposed portion of graded spacer layer 272. The dielectric insulator 291 may include the same material and formed in the same step as encapsulating layer 290.
  • A mask is defined by photolithography, and a bottom portion of the dielectric insulator 291 disposed over graded spacer layer 272 is removed by e.g., etching, to define an opening 292′, as well as opening 292 in the encapsulating layer 290.
  • Opening 292′ is masked by photolithographic methods, and electrode 294 is deposited. Then, electrode 294 is masked and an n-contact electrode 297 is defined by the formation of a thin film metal coating in opening 292′ directly on top of the exposed top surface of graded spacer layer 272. Thus, the electrodes 294, 297 are disposed on the same side of the substrate. Electrode 297 may be an output electrode and electrode 294 may be an input electrode, or vice versa.
  • The ends of the laser diode 200 are reflective, with at least one of the ends being partially transparent to allow radiation to be emitted from the device.
  • FIG. 4 is a schematic illustration of a two-section DFB laser. Structure 200′ has two diffraction gratings 210 and 210′ with different grating duty cycles based on the two different grating sections defined by dielectric layers 110, 111. Top contacts 294, 298 correspond to the two diffraction gratings 210, 210′, respectively. When laser 200′ is electrically pumped, one or two wavelengths λ1, λ2 of laser output, depending on current driving selecting, may be obtained from the same laser facet 277 that includes the emitting surfaces of graded first confining layer 274, multi-quantum well region 280, and graded second confining layer 282. Each of the laser outputs is longitudinal single mode.
  • Based on above description and techniques illustrated in FIGS. 2 a-2 c and 3, those familiar with the art can apply the concepts and mask design functionalities available using ART techniques to implement a variety of different multi-section DFB lasers or related optoelectronic structures such as sensors, modulators, etc.
  • The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims (25)

1. A method of making a laser diode, the method comprising the steps of:
forming a dielectric layer over a top surface of the substrate comprising a first semiconductor material;
defining a plurality of openings in the dielectric layer, the openings extending to the top surface of the substrate;
forming a second semiconductor material in the openings; and
defining a plurality of layers over the second semiconductor material and the dielectric layer to form the laser diode,
wherein portions of the dielectric layer define a diffraction grating.
2. The method of claim 1, wherein the diffraction grating has a width and a spacing selected to provide a duty cycle ranging from 20% to 50%.
3. The method of claim 1, wherein defining the plurality of openings comprises reactive ion etching.
4. The method of claim 1, wherein forming the second semiconductor material comprises selective epitaxy.
5. The method of claim 1, wherein the first semiconductor material comprises silicon and the second semiconductor material comprises at least one of a III-V compound or a II-VI compound.
6. The method of claim 1, wherein the plurality of semiconductor layers comprises at least one of a cladding layer, a grating layer, a graded spacer layer, a graded confining layer, a quantum well region, or a cap layer.
7. The method of claim 1, wherein the laser diode is a distributed feedback laser diode.
8. The method of claim 1, further comprising defining a bottom contact layer over a bottom surface of the substrate.
9. The method of claim 1, wherein a bottom portion of the second semiconductor material comprises lattice-mismatch defects and a top portion of the second semiconductor material is substantially free of lattice-mismatch defects.
10. The method of claim 9, wherein each of the openings has a height sufficient for trapping a majority of the lattice-mismatch defects within the opening.
11. The method of claim 1, wherein each of the plurality of openings has a width less than or equal to a height thereof.
12. A semiconductor device comprising:
a plurality of openings defined in a dielectric layer disposed above a crystalline substrate comprising a first semiconductor material;
a diffraction grating defined by portions of the dielectric layer disposed between the openings;
a second crystalline material disposed within each of the openings, the second crystalline material having a lattice mismatch with the substrate, and a majority of defects arising from lattice mismatch between the second material and the substrate exiting at a surface of the second material within each of the openings; and
a plurality of semiconductor layers disposed above the second crystalline material and the diffraction grating, the plurality of semiconductor layers forming a laser diode.
13. The device of claim 12 wherein the first semiconductor material comprises silicon.
14. The device of claim 12 wherein the second crystalline material comprises at least one of a III-V compound or a II-VI compound.
15. The device of claim 12 wherein the diffraction grating provides a duty cycle ranging from 20% to 50%.
16. The device of claim 12 wherein the laser diode is a distributed feedback laser.
17. A distributed feedback laser device comprising:
a dielectric diffraction grating disposed over a crystalline substrate; and
a plurality of layers disposed above the diffraction grating,
wherein the layers define a laser diode, and at least some of the layers comprise a III-V material lattice-mismatched to the crystalline substrate.
18. The device of claim 17 wherein the diffraction grating comprises a dielectric layer defining a plurality of openings.
19. The device of claim 18, further comprising a crystalline material disposed within the openings, the crystalline material having a lattice constant mismatched to a lattice constant of the crystalline substrate.
20. The device of claim 19, further comprising a contact disposed on a bottom side of the crystalline substrate.
21. The device of claim 19, further comprising an input electrode and an output electrode disposed on a single side of the crystalline substrate.
22. The device of claim 19, wherein a top portion of the crystalline material is substantially free of defects.
23. The device of claim 17, wherein the crystalline substrate comprises a group IV material.
24. A method of making a laser diode, the method comprising the steps of:
forming a dielectric layer over a crystalline substrate comprising a first semiconductor material;
forming a first diffraction grating by:
defining a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength;
forming a second diffraction grating by:
defining a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength; and
defining a plurality of layers over the first and second diffraction gratings to form the laser diode.
25. A distributed feedback laser device comprising:
a dielectric layer disposed over a crystalline substrate comprising a first semiconductor material;
a first diffraction grating defined by a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength;
a second diffraction grating defined by a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength; and
a plurality of layers disposed over the first and second diffraction gratings defining a distributed feedback laser device active region.
US11/875,177 2006-10-19 2007-10-19 Distributed feedback lasers formed via aspect ratio trapping Abandoned US20080187018A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US85278106P true 2006-10-19 2006-10-19
US11/875,177 US20080187018A1 (en) 2006-10-19 2007-10-19 Distributed feedback lasers formed via aspect ratio trapping

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/875,177 US20080187018A1 (en) 2006-10-19 2007-10-19 Distributed feedback lasers formed via aspect ratio trapping

Publications (1)

Publication Number Publication Date
US20080187018A1 true US20080187018A1 (en) 2008-08-07

Family

ID=39166803

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/875,177 Abandoned US20080187018A1 (en) 2006-10-19 2007-10-19 Distributed feedback lasers formed via aspect ratio trapping
US11/875,381 Active 2028-02-12 US8502263B2 (en) 2006-10-19 2007-10-19 Light-emitter-based devices with lattice-mismatched semiconductor structures
US13/903,735 Pending US20130252361A1 (en) 2006-10-19 2013-05-28 Light-Emitter-Based Devices with Lattice-Mismatched Semiconductor Structures

Family Applications After (2)

Application Number Title Priority Date Filing Date
US11/875,381 Active 2028-02-12 US8502263B2 (en) 2006-10-19 2007-10-19 Light-emitter-based devices with lattice-mismatched semiconductor structures
US13/903,735 Pending US20130252361A1 (en) 2006-10-19 2013-05-28 Light-Emitter-Based Devices with Lattice-Mismatched Semiconductor Structures

Country Status (2)

Country Link
US (3) US20080187018A1 (en)
WO (1) WO2008051503A2 (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US20080073641A1 (en) * 2006-09-27 2008-03-27 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US20080099785A1 (en) * 2006-09-07 2008-05-01 Amberwave Systems Coporation Defect Reduction Using Aspect Ratio Trapping
US20090098343A1 (en) * 2007-07-26 2009-04-16 Chantal Arena Epitaxial methods and templates grown by the methods
WO2010033813A2 (en) * 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US20110180806A1 (en) * 2010-01-28 2011-07-28 Intersil Americas Inc. Monolithic integration of gallium nitride and silicon devices and circuits, structure and method
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
US8344242B2 (en) 2007-09-07 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-junction solar cells
US8502263B2 (en) 2006-10-19 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitter-based devices with lattice-mismatched semiconductor structures
US8624103B2 (en) 2007-04-09 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8629446B2 (en) 2009-04-02 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US20140054755A1 (en) * 2012-08-21 2014-02-27 Micron Technology, Inc. Methods of forming semiconductor device structures, and related semiconductor device structures
US8822248B2 (en) 2008-06-03 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial growth of crystalline material
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
WO2015094219A1 (en) * 2013-12-18 2015-06-25 Intel Corporation Planar heterogeneous device
WO2015147851A1 (en) * 2014-03-28 2015-10-01 Intel Corporation Strain compensation in transistors
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US20160291248A1 (en) * 2013-12-20 2016-10-06 Huawei Technologies Co.,Ltd. Semiconductor device and method for producing semiconductor device
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US9984872B2 (en) 2008-09-19 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication and structures of crystalline material

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2595175B1 (en) * 2005-05-17 2019-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a lattice-mismatched semiconductor structure with reduced dislocation defect densities
JP5481067B2 (en) * 2005-07-26 2014-04-23 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. Solution for incorporation into an integrated circuit of an alternative active area materials
US7638842B2 (en) * 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US20090311483A1 (en) * 2006-04-04 2009-12-17 Technion Research & Development Foundation Ltd. Articles with Two Crystalline Materials and Method of Making Same
US20080070355A1 (en) * 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
US20090085055A1 (en) * 2007-09-27 2009-04-02 Hui Peng Method for Growing an Epitaxial Layer
WO2010110888A1 (en) * 2009-03-23 2010-09-30 The Board Of Trustees Of The Leland Stanford Junior University Quantum confinement solar cell fabriacated by atomic layer deposition
US20110062492A1 (en) * 2009-09-15 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology
JP2011166129A (en) * 2010-01-15 2011-08-25 Sumitomo Chemical Co Ltd Semiconductor substrate, electronic device, and method for producing semiconductor substrate
KR101805634B1 (en) * 2011-11-15 2017-12-08 삼성전자 주식회사 Semiconductor device comprising III-V group barrier and method of manufacturing the same
US9476143B2 (en) * 2012-02-15 2016-10-25 Imec Methods using mask structures for substantially defect-free epitaxial growth
US8841188B2 (en) * 2012-09-06 2014-09-23 International Business Machines Corporation Bulk finFET with controlled fin height and high-K liner
US8765563B2 (en) 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
FR2997558B1 (en) 2012-10-26 2015-12-18 Aledia opto-electric device and process for its manufacturing
US9859429B2 (en) * 2013-01-14 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of fabricating same
US9106048B2 (en) * 2013-02-11 2015-08-11 Oracle International Corporation Waveguide-coupled vertical cavity laser
WO2014144698A2 (en) * 2013-03-15 2014-09-18 Yale University Large-area, laterally-grown epitaxial semiconductor layers
US8753953B1 (en) * 2013-03-15 2014-06-17 International Business Machines Corporation Self aligned capacitor fabrication
FR3010828B1 (en) * 2013-09-13 2015-09-25 Commissariat Energie Atomique Method optimizes manufacturing material patterns iii-v semiconductor on a semiconductor substrate
US9064699B2 (en) 2013-09-30 2015-06-23 Samsung Electronics Co., Ltd. Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods
EP2869331A1 (en) * 2013-10-29 2015-05-06 IMEC vzw Episubstrates for selective area growth of group iii-v material and a method for fabricating a group iii-v material on a silicon substrate
US9177967B2 (en) * 2013-12-24 2015-11-03 Intel Corporation Heterogeneous semiconductor material integration techniques
WO2015160903A1 (en) 2014-04-16 2015-10-22 Yale University Nitrogen-polar semipolar gan layers and devices on sapphire substrates
WO2015160909A1 (en) 2014-04-16 2015-10-22 Yale University Method of obtaining planar semipolar gallium nitride surfaces
US9391140B2 (en) 2014-06-20 2016-07-12 Globalfoundries Inc. Raised fin structures and methods of fabrication
US9240447B1 (en) 2014-08-21 2016-01-19 International Business Machines Corporation finFETs containing improved strain benefit and self aligned trench isolation structures
CN106575670A (en) * 2014-09-18 2017-04-19 英特尔公司 Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices
US9401583B1 (en) * 2015-03-30 2016-07-26 International Business Machines Corporation Laser structure on silicon using aspect ratio trapping growth
KR20180008431A (en) 2015-05-19 2018-01-24 인텔 코포레이션 The semiconductor device having a raised doped crystalline structure
US9917414B2 (en) 2015-07-15 2018-03-13 International Business Machines Corporation Monolithic nanophotonic device on a semiconductor substrate
US9870940B2 (en) 2015-08-03 2018-01-16 Samsung Electronics Co., Ltd. Methods of forming nanosheets on lattice mismatched substrates
US9570297B1 (en) * 2015-12-09 2017-02-14 International Business Machines Corporation Elimination of defects in long aspect ratio trapping trench structures
US9437427B1 (en) 2015-12-30 2016-09-06 International Business Machines Corporation Controlled confined lateral III-V epitaxy
FR3053538B1 (en) * 2016-06-30 2018-08-17 Commissariat Energie Atomique Laser source semiconductor
US20190172911A1 (en) * 2016-09-30 2019-06-06 Intel Corporation Supperlatice channel included in a trench
EP3340403A1 (en) * 2016-12-23 2018-06-27 IMEC vzw Improvements in or relating to laser devices
US10163628B1 (en) * 2017-05-31 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Lattice-mismatched semiconductor substrates with defect reduction

Citations (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651179A (en) * 1983-01-21 1987-03-17 Rca Corporation Low resistance gallium arsenide field effect transistor
US4727047A (en) * 1980-04-10 1988-02-23 Massachusetts Institute Of Technology Method of producing sheets of crystalline material
US4826784A (en) * 1987-11-13 1989-05-02 Kopin Corporation Selective OMCVD growth of compound semiconductor materials on silicon substrates
US5032893A (en) * 1988-04-01 1991-07-16 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers
US5034337A (en) * 1989-02-10 1991-07-23 Texas Instruments Incorporated Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
US5091767A (en) * 1991-03-18 1992-02-25 At&T Bell Laboratories Article comprising a lattice-mismatched semiconductor heterostructure
US5091333A (en) * 1983-09-12 1992-02-25 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
US5093699A (en) * 1990-03-12 1992-03-03 Texas A & M University System Gate adjusted resonant tunnel diode device and method of manufacture
US5105247A (en) * 1990-08-03 1992-04-14 Cavanaugh Marion E Quantum field effect device with source extension region formed under a gate and between the source and drain regions
US5281283A (en) * 1987-03-26 1994-01-25 Canon Kabushiki Kaisha Group III-V compound crystal article using selective epitaxial growth
US5285086A (en) * 1990-08-02 1994-02-08 At&T Bell Laboratories Semiconductor devices with low dislocation defects
US5295150A (en) * 1992-12-11 1994-03-15 Eastman Kodak Company Distributed feedback-channeled substrate planar semiconductor laser
US5417180A (en) * 1991-10-24 1995-05-23 Rohm Co., Ltd. Method for forming SOI structure
US5427976A (en) * 1991-03-27 1995-06-27 Nec Corporation Method of producing a semiconductor on insulating substrate, and a method of forming a transistor thereon
US5432120A (en) * 1992-12-04 1995-07-11 Siemens Aktiengesellschaft Method for producing a laterally limited single-crystal region with selective epitaxy and the employment thereof for manufacturing a bipolar transistor as well as a MOS transistor
US5518953A (en) * 1991-09-24 1996-05-21 Rohm Co., Ltd. Method for manufacturing semiconductor device having grown layer on insulating layer
US5621227A (en) * 1995-07-18 1997-04-15 Discovery Semiconductors, Inc. Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxy
US5640022A (en) * 1993-08-27 1997-06-17 Sanyo Electric Co., Inc. Quantum effect device
US5710436A (en) * 1994-09-27 1998-01-20 Kabushiki Kaisha Toshiba Quantum effect device
US5717709A (en) * 1993-06-04 1998-02-10 Sharp Kabushiki Kaisha Semiconductor light-emitting device capable of having good stability in fundamental mode of oscillation, decreasing current leakage, and lowering oscillation threshold limit, and method of making the same
US5886385A (en) * 1996-08-22 1999-03-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6011271A (en) * 1994-04-28 2000-01-04 Fujitsu Limited Semiconductor device and method of fabricating the same
US6049098A (en) * 1995-04-27 2000-04-11 Nec Corporation Bipolar transistor having an emitter region formed of silicon carbide
US6191432B1 (en) * 1996-09-02 2001-02-20 Kabushiki Kaisha Toshiba Semiconductor device and memory device
US6228691B1 (en) * 1999-06-30 2001-05-08 Intel Corp. Silicon-on-insulator devices and method for producing the same
US6252261B1 (en) * 1998-09-30 2001-06-26 Nec Corporation GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor
US6348096B1 (en) * 1997-03-13 2002-02-19 Nec Corporation Method for manufacturing group III-V compound semiconductors
US20020030246A1 (en) * 2000-06-28 2002-03-14 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices not lattice matched to the substrate
US6362071B1 (en) * 2000-04-05 2002-03-26 Motorola, Inc. Method for forming a semiconductor device with an opening in a dielectric layer
US20020070383A1 (en) * 1999-03-31 2002-06-13 Naoki Shibata Group III nitride compound semiconductor device and method for producing the same
US6512252B1 (en) * 1999-11-15 2003-01-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US6521514B1 (en) * 1999-11-17 2003-02-18 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates
US20030045017A1 (en) * 2001-09-06 2003-03-06 Kazumasa Hiramatsu Method for fabricating III-V Group compound semiconductor
US20030064535A1 (en) * 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
US20030089899A1 (en) * 2000-08-22 2003-05-15 Lieber Charles M. Nanoscale wires and related devices
US6576532B1 (en) * 2001-11-30 2003-06-10 Motorola Inc. Semiconductor device and method therefor
US6579463B1 (en) * 2000-08-18 2003-06-17 The Regents Of The University Of Colorado Tunable nanomasks for pattern transfer and nanocluster array formation
US20040012037A1 (en) * 2002-07-18 2004-01-22 Motorola, Inc. Hetero-integration of semiconductor materials on silicon
US6686245B1 (en) * 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
US6710368B2 (en) * 2001-10-01 2004-03-23 Ken Scott Fisher Quantum tunneling transistor
US6720196B2 (en) * 2001-05-11 2004-04-13 Sanyo Electric Co., Ltd. Nitride-based semiconductor element and method of forming nitride-based semiconductor
US20040075105A1 (en) * 2002-08-23 2004-04-22 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US6727523B2 (en) * 1999-12-16 2004-04-27 Sony Corporation Method of manufacturing crystal of iii-v compounds of the nitride system, crystal substrate of iii-v compounds of the nitride system, crystal film of iii-v compounds of the nitride system, and method of manufacturing device
US20040105480A1 (en) * 2002-11-29 2004-06-03 Yakov Sidorin Tunable optical source
US20050003572A1 (en) * 2003-04-30 2005-01-06 Osram Opto Semiconductors Gmbh Method for fabricating a plurality of semiconductor chips
US6841808B2 (en) * 2000-06-23 2005-01-11 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing the same
US6841410B2 (en) * 2001-09-03 2005-01-11 Nec Corporation Method for forming group-III nitride semiconductor layer and group-III nitride semiconductor device
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6873009B2 (en) * 1999-05-13 2005-03-29 Hitachi, Ltd. Vertical semiconductor device with tunnel insulator in current path controlled by gate electrode
US20050073028A1 (en) * 2003-10-02 2005-04-07 Grant John M. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
US6887773B2 (en) * 2002-06-19 2005-05-03 Luxtera, Inc. Methods of incorporating germanium within CMOS process
US20050104156A1 (en) * 2003-11-13 2005-05-19 Texas Instruments Incorporated Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes
US6900070B2 (en) * 2002-04-15 2005-05-31 The Regents Of The University Of California Dislocation reduction in non-polar gallium nitride thin films
US20050118825A1 (en) * 2002-02-28 2005-06-02 Kazuki Nishijima Process for producing group III nitride compound semiconductor
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
US20050145941A1 (en) * 2004-01-07 2005-07-07 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US20050145954A1 (en) * 2004-01-05 2005-07-07 International Business Machines Corporation Structures and methods for making strained mosfets
US6917068B1 (en) * 2002-06-21 2005-07-12 Advanced Micro Devices, Inc. Semiconductor device having conductive structures formed near a gate electrode
US6921673B2 (en) * 2001-03-27 2005-07-26 Sony Corporation Nitride semiconductor device and method of manufacturing the same
US20050164475A1 (en) * 2004-01-23 2005-07-28 Martin Peckerar Technique for perfecting the active regions of wide bandgap semiconductor nitride devices
US6982204B2 (en) * 2002-07-16 2006-01-03 Cree, Inc. Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US20060019462A1 (en) * 2004-07-23 2006-01-26 International Business Machines Corporation Patterned strained semiconductor substrate and device
US6995456B2 (en) * 2004-03-12 2006-02-07 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
US6994751B2 (en) * 2001-02-27 2006-02-07 Sanyo Electric Co., Ltd. Nitride-based semiconductor element and method of forming nitride-based semiconductor
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6998684B2 (en) * 2004-03-31 2006-02-14 International Business Machines Corporation High mobility plane CMOS SOI
US7001804B2 (en) * 2004-01-30 2006-02-21 Atmel Germany Gmbh Method of producing active semiconductor layers of different thicknesses in an SOI wafer
US20060049409A1 (en) * 2002-12-18 2006-03-09 Rafferty Conor S Method for forming integrated circuit utilizing dual semiconductors
US7012314B2 (en) * 2002-12-18 2006-03-14 Agere Systems Inc. Semiconductor devices with reduced active region defects and unique contacting schemes
US7015497B1 (en) * 2002-08-27 2006-03-21 The Ohio State University Self-aligned and self-limited quantum dot nanoswitches and methods for making same
US7033936B1 (en) * 1999-08-17 2006-04-25 Imperial Innovations Limited Process for making island arrays
US7033436B2 (en) * 2001-04-12 2006-04-25 Sony Corporation Crystal growth method for nitride semiconductor and formation method for semiconductor device
US7041178B2 (en) * 2000-02-16 2006-05-09 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US20060128124A1 (en) * 2002-12-16 2006-06-15 Haskell Benjamin A Growth of reduced dislocation density non-polar gallium nitride by hydride vapor phase epitaxy
US20060131606A1 (en) * 2004-12-18 2006-06-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures employing seed layers and related fabrication methods
US20060145264A1 (en) * 2005-01-05 2006-07-06 Internaional Business Machines Corporation Stressed field effect transistors on hybrid orientation substrate
US20060160291A1 (en) * 2005-01-19 2006-07-20 Sharp Laboratories Of America, Inc. Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
US20070029643A1 (en) * 2003-03-21 2007-02-08 Johnson Mark A L Methods for nanoscale structures from optical lithography and subsequent lateral growth
US20070054465A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US7211864B2 (en) * 2003-09-15 2007-05-01 Seliskar John J Fully-depleted castellated gate MOSFET device and method of manufacture thereof
US20070105256A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated light emitting devices
US7224033B2 (en) * 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US20080001169A1 (en) * 2006-03-24 2008-01-03 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication

Family Cites Families (301)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322253A (en) 1980-04-30 1982-03-30 Rca Corporation Method of making selective crystalline silicon regions containing entrapped hydrogen by laser treatment
US4370510A (en) 1980-09-26 1983-01-25 California Institute Of Technology Gallium arsenide single crystal solar cell structure and method of making
US4482422A (en) * 1982-02-26 1984-11-13 Rca Corporation Method for growing a low defect monocrystalline layer on a mask
US4545109A (en) 1983-01-21 1985-10-08 Rca Corporation Method of making a gallium arsenide field effect transistor
US4557794A (en) * 1984-05-07 1985-12-10 Rca Corporation Method for forming a void-free monocrystalline epitaxial layer on a mask
US4860081A (en) 1984-06-28 1989-08-22 Gte Laboratories Incorporated Semiconductor integrated circuit structure with insulative partitions
US4551394A (en) 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs
DE3676019D1 (en) 1985-09-03 1991-01-17 Daido Steel Co Ltd Epitaxial gallium arsenide wafer-and process for their manufacture.
US4774205A (en) 1986-06-13 1988-09-27 Massachusetts Institute Of Technology Monolithic integration of silicon and gallium arsenide devices
JPH0571173B2 (en) 1986-09-25 1993-10-06 Mitsubishi Electric Corp
US5236546A (en) 1987-01-26 1993-08-17 Canon Kabushiki Kaisha Process for producing crystal article
US5269876A (en) 1987-01-26 1993-12-14 Canon Kabushiki Kaisha Process for producing crystal article
US5166767A (en) 1987-04-14 1992-11-24 National Semiconductor Corporation Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer
US4876210A (en) 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
US5079616A (en) 1988-02-11 1992-01-07 Gte Laboratories Incorporated Semiconductor structure
US5272105A (en) 1988-02-11 1993-12-21 Gte Laboratories Incorporated Method of manufacturing an heteroepitaxial semiconductor structure
GB2215514A (en) 1988-03-04 1989-09-20 Plessey Co Plc Terminating dislocations in semiconductor epitaxial layers
US5156995A (en) 1988-04-01 1992-10-20 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers
EP0352472A3 (en) 1988-07-25 1991-02-06 Texas Instruments Incorporated Heteroepitaxy of lattice-mismatched semiconductor materials
US5238869A (en) 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
JPH0262090A (en) * 1988-08-29 1990-03-01 Matsushita Electric Ind Co Ltd Manufacture of optical semiconductor device
US5061644A (en) 1988-12-22 1991-10-29 Honeywell Inc. Method for fabricating self-aligned semiconductor devices
DE68915529D1 (en) 1989-01-31 1994-06-30 Agfa Gevaert Nv Integration of GaAs on Si substrate.
US4948456A (en) 1989-06-09 1990-08-14 Delco Electronics Corporation Confined lateral selective epitaxial growth
US5098850A (en) 1989-06-16 1992-03-24 Canon Kabushiki Kaisha Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing solar battery by use of them
US5256594A (en) 1989-06-16 1993-10-26 Intel Corporation Masking technique for depositing gallium arsenide on silicon
US5170404A (en) * 1989-09-04 1992-12-08 Hitachi, Ltd. Semiconductor laser device suitable for optical communications systems drive
US5164359A (en) 1990-04-20 1992-11-17 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
JP3202223B2 (en) 1990-11-27 2001-08-27 日本電気株式会社 Manufacturing method of a transistor
US5403751A (en) 1990-11-29 1995-04-04 Canon Kabushiki Kaisha Process for producing a thin silicon solar cell
US5223043A (en) 1991-02-11 1993-06-29 The United States Of America As Represented By The United States Department Of Energy Current-matched high-efficiency, multijunction monolithic solar cells
US5269852A (en) 1991-05-27 1993-12-14 Canon Kabushiki Kaisha Crystalline solar cell and method for producing the same
JP2773487B2 (en) 1991-10-15 1998-07-09 日本電気株式会社 Tunnel transistor
US5406574A (en) * 1991-10-23 1995-04-11 Kabushiki Kaisha Toshiba Semiconductor laser device
JP3286920B2 (en) 1992-07-10 2002-05-27 富士通株式会社 A method of manufacturing a semiconductor device
JP3319472B2 (en) 1992-12-07 2002-09-03 富士通株式会社 Semiconductor device and manufacturing method thereof
US5407491A (en) 1993-04-08 1995-04-18 University Of Houston Tandem solar cell with improved tunnel junction
US5792679A (en) 1993-08-30 1998-08-11 Sharp Microelectronics Technology, Inc. Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5405453A (en) 1993-11-08 1995-04-11 Applied Solar Energy Corporation High efficiency multi-junction solar cell
US5489539A (en) 1994-01-10 1996-02-06 Hughes Aircraft Company Method of making quantum well structure with self-aligned gate
JPH0851109A (en) 1994-04-11 1996-02-20 Texas Instr Inc <Ti> Method for growing silicon epitaxialy in window of wafer patterned with oxide
US5825240A (en) 1994-11-30 1998-10-20 Massachusetts Institute Of Technology Resonant-tunneling transmission line technology
JP3835225B2 (en) 1995-02-23 2006-10-18 日亜化学工業株式会社 The nitride semiconductor light emitting device
US5528209A (en) 1995-04-27 1996-06-18 Hughes Aircraft Company Monolithic microwave integrated circuit and method
TW304310B (en) 1995-05-31 1997-05-01 Siemens Ag
WO1997023000A1 (en) 1995-12-15 1997-06-26 Philips Electronics N.V. SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER
TW314621B (en) 1995-12-20 1997-09-01 Toshiba Co Ltd
US5987590A (en) 1996-04-02 1999-11-16 Texas Instruments Incorporated PC circuits, systems and methods
MX9703533A (en) 1996-05-17 1998-10-31 Canon Kk Photovoltaic device and process for the production thereof.
JP3719618B2 (en) 1996-06-17 2005-11-24 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
US6229153B1 (en) 1996-06-21 2001-05-08 Wisconsin Alumni Research Corporation High peak current density resonant tunneling diode
JP3449516B2 (en) 1996-08-30 2003-09-22 株式会社リコー Semiconductor multilayer reflection mirror and the semiconductor multilayer reflection preventing film and the surface-emitting type semiconductor laser and a light receiving element
US5825049A (en) 1996-10-09 1998-10-20 Sandia Corporation Resonant tunneling device with two-dimensional quantum well emitter and base layers
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
US5853497A (en) 1996-12-12 1998-12-29 Hughes Electronics Corporation High efficiency multi-junction solar cells
JP3853905B2 (en) 1997-03-18 2006-12-06 株式会社東芝 Device using the quantum effect device and bl tunnel element
EP0874405A3 (en) 1997-03-25 2004-09-15 Mitsubishi Cable Industries, Ltd. GaN group crystal base member having low dislocation density, use thereof and manufacturing methods thereof
CN1131548C (en) 1997-04-04 2003-12-17 松下电器产业株式会社 Semiconductor device
US6153010A (en) 1997-04-11 2000-11-28 Nichia Chemical Industries Ltd. Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor device
DE19715572A1 (en) * 1997-04-15 1998-10-22 Telefunken Microelectron Selective epitaxy of III-V nitride semiconductor layers
US5998781A (en) 1997-04-30 1999-12-07 Sandia Corporation Apparatus for millimeter-wave signal generation
US5903170A (en) 1997-06-03 1999-05-11 The Regents Of The University Of Michigan Digital logic design using negative differential resistance diodes and field-effect transistors
US5883549A (en) 1997-06-20 1999-03-16 Hughes Electronics Corporation Bipolar junction transistor (BJT)--resonant tunneling diode (RTD) oscillator circuit and method
EP1016129B2 (en) 1997-06-24 2009-06-10 Massachusetts Institute Of Technology Controlling threading dislocation densities using graded layers and planarization
US5869845A (en) 1997-06-26 1999-02-09 Texas Instruments Incorporated Resonant tunneling memory
JP3930161B2 (en) 1997-08-29 2007-06-13 株式会社東芝 Nitride-based semiconductor device, light emitting device and a manufacturing method thereof
US6015979A (en) * 1997-08-29 2000-01-18 Kabushiki Kaisha Toshiba Nitride-based semiconductor element and method for manufacturing the same
EP1036412A1 (en) 1997-09-16 2000-09-20 Massachusetts Institute Of Technology CO-PLANAR Si AND Ge COMPOSITE SUBSTRATE AND METHOD OF PRODUCING SAME
TW393785B (en) * 1997-09-19 2000-06-11 Siemens Ag Method to produce many semiconductor-bodies
FR2769924B1 (en) 1997-10-20 2000-03-10 Centre Nat Rech Scient Process for producing an epitaxial layer of gallium nitride, epitaxial layer of gallium nitride and optoelectronic component provided with such layer
CN1175473C (en) 1997-10-30 2004-11-10 住友电气工业株式会社 GaN signale crystalline substrate and method of producing the same
JP3036495B2 (en) * 1997-11-07 2000-04-24 豊田合成株式会社 The method of manufacturing a gallium nitride-based compound semiconductor
JP3180743B2 (en) 1997-11-17 2001-06-25 日本電気株式会社 Nitride compound semiconductor light-emitting device and its manufacturing method
US6150242A (en) 1998-03-25 2000-11-21 Texas Instruments Incorporated Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode
JPH11274467A (en) 1998-03-26 1999-10-08 Murata Mfg Co Ltd Photo-electronic integrated-circuit device
US6500257B1 (en) 1998-04-17 2002-12-31 Agilent Technologies, Inc. Epitaxial material grown laterally within a trench and method for producing same
US6248948B1 (en) * 1998-05-15 2001-06-19 Canon Kabushiki Kaisha Solar cell module and method of producing the same
US6265289B1 (en) 1998-06-10 2001-07-24 North Carolina State University Methods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated thereby
JP4005701B2 (en) 1998-06-24 2007-11-14 シャープ株式会社 Forming methods and nitrogen compound semiconductor device of the nitrogen compound semiconductor film
WO2000004615A1 (en) 1998-07-14 2000-01-27 Fujitsu Limited Semiconductor laser, semiconductor device, and method for manufacturing the same
US7132691B1 (en) 1998-09-10 2006-11-07 Rohm Co., Ltd. Semiconductor light-emitting device and method for manufacturing the same
JP3868136B2 (en) 1999-01-20 2007-01-17 日亜化学工業株式会社 The gallium nitride-based compound semiconductor light-emitting device
JP3372226B2 (en) 1999-02-10 2003-01-27 日亜化学工業株式会社 Nitride semiconductor laser device
US7145167B1 (en) 2000-03-11 2006-12-05 International Business Machines Corporation High speed Ge channel heterostructures for field effect devices
JP3760663B2 (en) * 1999-03-31 2006-03-29 豊田合成株式会社 Method for producing Iii nitride compound semiconductor element
DE10017137A1 (en) 1999-04-14 2000-10-26 Siemens Ag Novel silicon structure, used for solar cells or LCD TFTs, comprises a crystalline textured silicon thin film over a biaxially textured lattice-matched diffusion barrier buffer layer on a thermal expansion-matched inert substrate
US6803598B1 (en) 1999-05-07 2004-10-12 University Of Delaware Si-based resonant interband tunneling diodes and method of making interband tunneling diodes
JP3587081B2 (en) 1999-05-10 2004-11-10 豊田合成株式会社 Iii Nitride semiconductor fabrication methods and iii-nitride semiconductor light emitting device
US6252287B1 (en) 1999-05-19 2001-06-26 Sandia Corporation InGaAsN/GaAs heterojunction for multi-junction solar cells
JP3555500B2 (en) 1999-05-21 2004-08-18 豊田合成株式会社 Iii nitride semiconductor and a manufacturing method thereof
US6214653B1 (en) 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
JP2001007447A (en) 1999-06-18 2001-01-12 Nichia Chem Ind Ltd Nitride semiconductor laser element
DE60045126D1 (en) 1999-06-25 2010-12-02 Massachusetts Inst Technology Oxidation of a germanium layer on a silicon layer deposited
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
JP2001102678A (en) 1999-09-29 2001-04-13 Toshiba Corp Gallium nitride compound semiconductor element
US6812053B1 (en) 1999-10-14 2004-11-02 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
JP2001189483A (en) 1999-10-18 2001-07-10 Sharp Corp Solar battery cell with bypass function, multi-junction laminating type solar battery cell with bypass function, and their manufacturing method
US6403451B1 (en) 2000-02-09 2002-06-11 Noerh Carolina State University Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts
US6849077B2 (en) 2000-02-11 2005-02-01 Evysio Medical Devices Ulc Stent delivery system and method of use
JP3512701B2 (en) 2000-03-10 2004-03-31 株式会社東芝 Semiconductor device and manufacturing method thereof
TW504754B (en) 2000-03-24 2002-10-01 Sumitomo Chemical Co Group III-V compound semiconductor and method of producing the same
US20050184302A1 (en) 2000-04-04 2005-08-25 Toshimasa Kobayashi Nitride semiconductor device and method of manufacturing the same
JP2001338988A (en) 2000-05-25 2001-12-07 Hitachi Ltd Semiconductor device and its manufacturing method
US6699419B1 (en) * 2000-06-05 2004-03-02 General Motors Corporation Method of forming a composite article with a textured surface and mold therefor
US6352071B1 (en) * 2000-06-20 2002-03-05 Seh America, Inc. Apparatus and method for reducing bow and warp in silicon wafers sliced by a wire saw
JP3882539B2 (en) * 2000-07-18 2007-02-21 ソニー株式会社 The semiconductor light emitting device and a method of manufacturing the same, and an image display device
US20020011612A1 (en) 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002118255A (en) 2000-07-31 2002-04-19 Toshiba Corp Semiconductor device and manufacturing method thereof
JP4269541B2 (en) 2000-08-01 2009-05-27 株式会社Sumco Method for manufacturing a forming method and a field effect transistor of the semiconductor substrate and the field effect transistor and a method of forming the SiGe layer and the strained Si layer using the same
US20060175601A1 (en) 2000-08-22 2006-08-10 President And Fellows Of Harvard College Nanoscale wires and related devices
US6407425B1 (en) 2000-09-21 2002-06-18 Texas Instruments Incorporated Programmable neuron MOSFET on SOI
US6456214B1 (en) 2000-09-27 2002-09-24 Raytheon Company High-speed comparator utilizing resonant tunneling diodes and associated method
JP4044276B2 (en) 2000-09-28 2008-02-06 株式会社東芝 Semiconductor device and manufacturing method thereof
US6555891B1 (en) * 2000-10-17 2003-04-29 International Business Machines Corporation SOI hybrid structure with selective epitaxial growth of silicon
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6720090B2 (en) 2001-01-02 2004-04-13 Eastman Kodak Company Organic light emitting diode devices with improved luminance efficiency
WO2002064864A1 (en) 2001-02-14 2002-08-22 Toyoda Gosei Co., Ltd. Production method for semiconductor crystal and semiconductor luminous element
JP4084541B2 (en) 2001-02-14 2008-04-30 株式会社豊田中央研究所 The method of manufacturing a semiconductor crystal and semiconductor light-emitting element
US6380590B1 (en) 2001-02-22 2002-04-30 Advanced Micro Devices, Inc. SOI chip having multiple threshold voltage MOSFETs by using multiple channel materials and method of fabricating same
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
JP2002270516A (en) * 2001-03-07 2002-09-20 Nec Corp Growing method of iii group nitride semiconductor, film thereof and semiconductor element using the same
US7205604B2 (en) 2001-03-13 2007-04-17 International Business Machines Corporation Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
JP4084544B2 (en) 2001-03-30 2008-04-30 株式会社豊田中央研究所 The method of manufacturing a semiconductor substrate and a semiconductor element
AU2002307008C1 (en) 2001-03-30 2008-10-30 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
GB0110112D0 (en) 2001-04-25 2001-06-20 Univ Glasgow Improved optoelectronic device
GB0111207D0 (en) 2001-05-08 2001-06-27 Btg Int Ltd A method to produce germanium layers
US6784074B2 (en) 2001-05-09 2004-08-31 Nsc-Nanosemiconductor Gmbh Defect-free semiconductor templates for epitaxial growth and method of making same
US20020168802A1 (en) 2001-05-14 2002-11-14 Hsu Sheng Teng SiGe/SOI CMOS and method of making the same
US7358578B2 (en) 2001-05-22 2008-04-15 Renesas Technology Corporation Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring
JP3515974B2 (en) 2001-06-13 2004-04-05 松下電器産業株式会社 Nitride semiconductor, manufacturing method thereof and a nitride semiconductor device
CN1259734C (en) 2001-06-13 2006-06-14 松下电器产业株式会社 Nitride semiconductor, production method therefor and nitride semiconductor element
US6566284B2 (en) 2001-08-07 2003-05-20 Hrl Laboratories, Llc Method of manufacture for 80 nanometer diameter resonant tunneling diode with improved peak-to-valley ratio and resonant tunneling diode therefrom
TW544930B (en) 2001-09-11 2003-08-01 Toyoda Gosei Kk Method for producing semiconductor crystal
JP2003163370A (en) 2001-09-11 2003-06-06 Toyoda Gosei Co Ltd Method of manufacturing semiconductor crystal
US7105865B2 (en) 2001-09-19 2006-09-12 Sumitomo Electric Industries, Ltd. AlxInyGa1−x−yN mixture crystal substrate
US6689650B2 (en) 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US20030070707A1 (en) 2001-10-12 2003-04-17 King Richard Roland Wide-bandgap, lattice-mismatched window layer for a solar energy conversion device
JP2003142728A (en) 2001-11-02 2003-05-16 Nobuhiko Sawaki Manufacturing method of semiconductor light emitting element
JP2003152220A (en) 2001-11-15 2003-05-23 Sharp Corp Manufacturing method for semiconductor light emitting element and the semiconductor light emitting element
US6835246B2 (en) 2001-11-16 2004-12-28 Saleem H. Zaidi Nanostructures for hetero-expitaxial growth on silicon substrates
WO2003054937A1 (en) 2001-12-20 2003-07-03 Matsushita Electric Industrial Co., Ltd. Method for making nitride semiconductor substrate and method for making nitride semiconductor device
US6744071B2 (en) 2002-01-28 2004-06-01 Nichia Corporation Nitride semiconductor element with a supporting substrate
KR100458288B1 (en) 2002-01-30 2004-11-26 한국과학기술원 Double-Gate FinFET
US6492216B1 (en) 2002-02-07 2002-12-10 Taiwan Semiconductor Manufacturing Company Method of forming a transistor with a strained channel
JP3782021B2 (en) 2002-02-22 2006-06-07 株式会社東芝 Semiconductor device, method of manufacturing a semiconductor device, a method of manufacturing a semiconductor substrate
US6635909B2 (en) 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US7208393B2 (en) 2002-04-15 2007-04-24 The Regents Of The University Of California Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy
US20060162768A1 (en) 2002-05-21 2006-07-27 Wanlass Mark W Low bandgap, monolithic, multi-bandgap, optoelectronic devices
US8067687B2 (en) 2002-05-21 2011-11-29 Alliance For Sustainable Energy, Llc High-efficiency, monolithic, multi-bandgap, tandem photovoltaic energy converters
US7217882B2 (en) 2002-05-24 2007-05-15 Cornell Research Foundation, Inc. Broad spectrum solar cell
CN2550906Y (en) 2002-05-27 2003-05-14 李映华 Stereo light double side junction light battery
FR2840452B1 (en) 2002-05-28 2005-10-14 Lumilog A method of making by epitaxy of a gallium nitride film separated from its substrate
TWI271877B (en) 2002-06-04 2007-01-21 Nitride Semiconductors Co Ltd Gallium nitride compound semiconductor device and manufacturing method
JP2004014856A (en) 2002-06-07 2004-01-15 Sharp Corp Method for manufacturing semiconductor substrate and semiconductor device
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7262117B1 (en) 2003-06-10 2007-08-28 Luxtera, Inc. Germanium integrated CMOS wafer and method for manufacturing the same
US6812495B2 (en) 2002-06-19 2004-11-02 Massachusetts Institute Of Technology Ge photodetectors
US6617643B1 (en) 2002-06-28 2003-09-09 Mcnc Low power tunneling metal-oxide-semiconductor (MOS) device
US7335908B2 (en) 2002-07-08 2008-02-26 Qunano Ab Nanostructures and methods for manufacturing the same
US7411233B2 (en) 2002-08-27 2008-08-12 E-Phocus, Inc Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure
US20040043584A1 (en) 2002-08-27 2004-03-04 Thomas Shawn G. Semiconductor device and method of making same
GB0220438D0 (en) 2002-09-03 2002-10-09 Univ Warwick Formation of lattice-turning semiconductor substrates
US7122733B2 (en) 2002-09-06 2006-10-17 The Boeing Company Multi-junction photovoltaic cell having buffer layers for the growth of single crystal boron compounds
US6830953B1 (en) 2002-09-17 2004-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Suppression of MOSFET gate leakage current
US6815241B2 (en) 2002-09-25 2004-11-09 Cao Group, Inc. GaN structures having low dislocation density and methods of manufacture
US6787864B2 (en) 2002-09-30 2004-09-07 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
JP4546021B2 (en) 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 Insulated gate field effect transistor and a semiconductor device
US6902991B2 (en) 2002-10-24 2005-06-07 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
US6709982B1 (en) 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6951819B2 (en) 2002-12-05 2005-10-04 Blue Photonics, Inc. High efficiency, monolithic multijunction solar cells containing lattice-mismatched materials and methods of forming same
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
JP2004200375A (en) * 2002-12-18 2004-07-15 Matsushita Electric Ind Co Ltd Semiconductor laser device and method of manufacturing the same
US7453129B2 (en) 2002-12-18 2008-11-18 Noble Peak Vision Corp. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
US7098487B2 (en) 2002-12-27 2006-08-29 General Electric Company Gallium nitride crystal and method of making same
KR100513316B1 (en) * 2003-01-21 2005-09-09 삼성전기주식회사 Manufacturing method of semiconductor device having high efficiency
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
JP2004235190A (en) * 2003-01-28 2004-08-19 Sony Corp Optical semiconductor device
WO2004073044A2 (en) 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Finfet device and method to make same
DE10320160A1 (en) 2003-02-14 2004-08-26 Osram Opto Semiconductors Gmbh Production of semiconductor bodies for e.g. optoelectronic components comprises forming a mask layer on the substrate or on an initial layer having windows to the substrate, back-etching, and further processing
US6815738B2 (en) 2003-02-28 2004-11-09 International Business Machines Corporation Multiple gate MOSFET structure with strained Si Fin body
JP4695824B2 (en) 2003-03-07 2011-06-08 信越半導体株式会社 A method of manufacturing a semiconductor wafer
JP4585510B2 (en) 2003-03-07 2010-11-24 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. Shallow trench isolation process
US6936851B2 (en) 2003-03-21 2005-08-30 Tien Yang Wang Semiconductor light-emitting device and method for manufacturing the same
US7061065B2 (en) 2003-03-31 2006-06-13 National Chung-Hsing University Light emitting diode and method for producing the same
US6900502B2 (en) 2003-04-03 2005-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel on insulator device
TWI231994B (en) 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US20050212051A1 (en) 2003-04-16 2005-09-29 Sarnoff Corporation Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6909186B2 (en) 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
US7445673B2 (en) 2004-05-18 2008-11-04 Lumilog Manufacturing gallium nitride substrates by lateral overgrowth through masks and devices fabricated thereof
US7088143B2 (en) 2003-05-22 2006-08-08 The Regents Of The University Of Michigan Dynamic circuits having improved noise tolerance and method for designing same
US6849487B2 (en) 2003-05-27 2005-02-01 Motorola, Inc. Method for forming an electronic structure using etch
TWI242232B (en) 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
JP4105044B2 (en) 2003-06-13 2008-06-18 株式会社東芝 Field-effect transistor
US6974733B2 (en) 2003-06-16 2005-12-13 Intel Corporation Double-gate transistor with enhanced carrier mobility
US6943407B2 (en) 2003-06-17 2005-09-13 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
JP2005011915A (en) 2003-06-18 2005-01-13 Hitachi Ltd Semiconductor device, semiconductor circuit module and its manufacturing method
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
KR100631832B1 (en) 2003-06-24 2006-10-09 삼성전기주식회사 A white light emitting device and a method of manufacturing the same
US7122392B2 (en) 2003-06-30 2006-10-17 Intel Corporation Methods of forming a high germanium concentration silicon germanium alloy by epitaxial lateral overgrowth and structures formed thereby
US20050017351A1 (en) 2003-06-30 2005-01-27 Ravi Kramadhati V. Silicon on diamond wafers and devices
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
JP2005051022A (en) 2003-07-28 2005-02-24 Seiko Epson Corp Semiconductor device and its manufacturing method
CN100536167C (en) 2003-08-05 2009-09-02 富士通微电子株式会社 Semiconductor device and preparation method thereof
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US6855583B1 (en) 2003-08-05 2005-02-15 Advanced Micro Devices, Inc. Method for forming tri-gate FinFET with mesa isolation
US7101742B2 (en) 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US20050035410A1 (en) 2003-08-15 2005-02-17 Yee-Chia Yeo Semiconductor diode with reduced leakage
US7355253B2 (en) 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6815278B1 (en) 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US6955969B2 (en) 2003-09-03 2005-10-18 Advanced Micro Devices, Inc. Method of growing as a channel region to reduce source/drain junction capacitance
US7078299B2 (en) 2003-09-03 2006-07-18 Advanced Micro Devices, Inc. Formation of finFET using a sidewall epitaxial layer
JP4439358B2 (en) 2003-09-05 2010-03-24 株式会社東芝 Field effect transistor and manufacturing method thereof
US20050054164A1 (en) 2003-09-09 2005-03-10 Advanced Micro Devices, Inc. Strained silicon MOSFETs having reduced diffusion of n-type dopants
US20060073681A1 (en) 2004-09-08 2006-04-06 Han Sang M Nanoheteroepitaxy of Ge on Si as a foundation for group III-V and II-VI integration
US7579263B2 (en) 2003-09-09 2009-08-25 Stc.Unm Threading-dislocation-free nanoheteroepitaxy of Ge on Si using self-directed touch-down of Ge through a thin SiO2 layer
US7138292B2 (en) 2003-09-10 2006-11-21 Lsi Logic Corporation Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide
US20050056827A1 (en) 2003-09-15 2005-03-17 Agency For Science, Technology And Research CMOS compatible low band offset double barrier resonant tunneling diode
EP1676322A2 (en) 2003-09-19 2006-07-05 Spinnaker Semiconductor, Inc. Schottky barrier integrated circuit
EP1519420A2 (en) 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US6831350B1 (en) 2003-10-02 2004-12-14 Freescale Semiconductor, Inc. Semiconductor structure with different lattice constant materials and method for forming the same
EP1676305A1 (en) 2003-10-03 2006-07-05 Spinnaker Semiconductor, Inc. Schottky-barrier mosfet manufacturing method using isotropic etch process
US6900491B2 (en) 2003-10-06 2005-05-31 Hewlett-Packard Development Company, L.P. Magnetic memory
US20050139860A1 (en) 2003-10-22 2005-06-30 Snyder John P. Dynamic schottky barrier MOSFET device and method of manufacture
US7009215B2 (en) * 2003-10-24 2006-03-07 General Electric Company Group III-nitride based resonant cavity light emitting devices fabricated on single crystal gallium nitride substrates
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US7057216B2 (en) 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7176522B2 (en) 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
JP2005191530A (en) 2003-12-03 2005-07-14 Sumitomo Electric Ind Ltd Light emitting device
JP4473710B2 (en) 2003-12-05 2010-06-02 株式会社東芝 Semiconductor device
US7198995B2 (en) 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
US6958286B2 (en) 2004-01-02 2005-10-25 International Business Machines Corporation Method of preventing surface roughening during hydrogen prebake of SiGe substrates
US7138302B2 (en) 2004-01-12 2006-11-21 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit channel region
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
US7118987B2 (en) 2004-01-29 2006-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of achieving improved STI gap fill with reduced stress
US7180134B2 (en) 2004-01-30 2007-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structures for planar and multiple-gate transistors formed on SOI
US6855982B1 (en) 2004-02-02 2005-02-15 Advanced Micro Devices, Inc. Self aligned double gate transistor having a strained channel region and process therefor
US7205210B2 (en) 2004-02-17 2007-04-17 Freescale Semiconductor, Inc. Semiconductor structure having strained semiconductor and method therefor
US7492022B2 (en) 2004-02-27 2009-02-17 University Of Iowa Research Foundation Non-magnetic semiconductor spin transistor
US6888181B1 (en) 2004-03-18 2005-05-03 United Microelectronics Corp. Triple gate device having strained-silicon channel
US20050211291A1 (en) 2004-03-23 2005-09-29 The Boeing Company Solar cell assembly
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7087965B2 (en) 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
US7084441B2 (en) 2004-05-20 2006-08-01 Cree, Inc. Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
US7125785B2 (en) 2004-06-14 2006-10-24 International Business Machines Corporation Mixed orientation and mixed material semiconductor-on-insulator wafer
US7807921B2 (en) 2004-06-15 2010-10-05 The Boeing Company Multijunction solar cell having a lattice mismatched GrIII-GrV-X layer and a composition-graded buffer layer
US7244958B2 (en) 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
US6991998B2 (en) 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US20060211210A1 (en) 2004-08-27 2006-09-21 Rensselaer Polytechnic Institute Material for selective deposition and etching
TWI442456B (en) 2004-08-31 2014-06-21 Sophia School Corp Light emitting element
US7002175B1 (en) 2004-10-08 2006-02-21 Agency For Science, Technology And Research Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration
US7846759B2 (en) 2004-10-21 2010-12-07 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
US20060105533A1 (en) 2004-11-16 2006-05-18 Chong Yung F Method for engineering hybrid orientation/material semiconductor substrate
JP2006196631A (en) 2005-01-13 2006-07-27 Hitachi Ltd Semiconductor device and its manufacturing method
US7344942B2 (en) 2005-01-26 2008-03-18 Micron Technology, Inc. Isolation regions for semiconductor devices and their formation
JP2006253181A (en) 2005-03-08 2006-09-21 Seiko Epson Corp Semiconductor device and its manufacturing method
KR100712753B1 (en) 2005-03-09 2007-04-30 주식회사 실트론 Compound semiconductor device and method for manufacturing the same
TWI246210B (en) * 2005-04-28 2005-12-21 Epitech Corp Ltd Lateral current blocking light emitting diode and method for manufacturing the same
EP2595175B1 (en) 2005-05-17 2019-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a lattice-mismatched semiconductor structure with reduced dislocation defect densities
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP2006332295A (en) 2005-05-26 2006-12-07 Matsushita Electric Ind Co Ltd Hetero-junction bipolar transistor and manufacturing method thereof
TW200703463A (en) 2005-05-31 2007-01-16 Univ California Defect reduction of non-polar and semi-polar III-nitrides with sidewall lateral epitaxial overgrowth (SLEO)
JP5481067B2 (en) 2005-07-26 2014-04-23 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. Solution for incorporation into an integrated circuit of an alternative active area materials
US7801406B2 (en) 2005-08-01 2010-09-21 Massachusetts Institute Of Technology Method of fabricating Ge or SiGe/Si waveguide or photonic crystal structures by selective growth
US7358107B2 (en) 2005-10-27 2008-04-15 Sharp Laboratories Of America, Inc. Method of fabricating a germanium photo detector on a high quality germanium epitaxial overgrowth layer
JP2009515344A (en) 2005-11-04 2009-04-09 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア High light extraction efficiency of the light emitting diode (of led)
US7629661B2 (en) 2006-02-10 2009-12-08 Noble Peak Vision Corp. Semiconductor devices with photoresponsive components and metal silicide light blocking structures
KR100790869B1 (en) 2006-02-16 2008-01-03 삼성전자주식회사 Single crystal substrate and fabrication method thereof
US7691698B2 (en) 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US20070267722A1 (en) 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US20080070355A1 (en) 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008039495A1 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US20080154197A1 (en) 2006-12-20 2008-06-26 Joel Brian Derrico System and method for regulating the temperature of a fluid injected into a patient
JP2008198656A (en) 2007-02-08 2008-08-28 Shin Etsu Chem Co Ltd Method of manufacturing semiconductor substrate
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
WO2008124154A2 (en) 2007-04-09 2008-10-16 Amberwave Systems Corporation Photovoltaics on silicon
KR20080102065A (en) 2007-05-18 2008-11-24 삼성전자주식회사 Method of forming a epitaxial silicon structure and method of forming a semiconductor device using the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
KR20090010284A (en) 2007-07-23 2009-01-30 엘지이노텍 주식회사 Semiconductor light emitting device and fabrication method thereof
DE112008002387T5 (en) 2007-09-07 2010-06-24 Amberwave Systems Corp. Multijunction solar cells
US7883990B2 (en) 2007-10-31 2011-02-08 International Business Machines Corporation High resistivity SOI base wafer using thermally annealed substrate
WO2009084238A1 (en) 2007-12-28 2009-07-09 Sumitomo Chemical Company, Limited Semiconductor substrate, method for manufacturing semiconductor substrate, and electronic device
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
CN102379046B (en) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 Devices formed from a non-polar plane of a crystalline material and method of making the same
JP3202223U (en) 2015-11-09 2016-01-28 株式会社千葉武道具 Kendo for Kote

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727047A (en) * 1980-04-10 1988-02-23 Massachusetts Institute Of Technology Method of producing sheets of crystalline material
US4651179A (en) * 1983-01-21 1987-03-17 Rca Corporation Low resistance gallium arsenide field effect transistor
US5091333A (en) * 1983-09-12 1992-02-25 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
US5281283A (en) * 1987-03-26 1994-01-25 Canon Kabushiki Kaisha Group III-V compound crystal article using selective epitaxial growth
US4826784A (en) * 1987-11-13 1989-05-02 Kopin Corporation Selective OMCVD growth of compound semiconductor materials on silicon substrates
US5032893A (en) * 1988-04-01 1991-07-16 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers
US5034337A (en) * 1989-02-10 1991-07-23 Texas Instruments Incorporated Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
US5093699A (en) * 1990-03-12 1992-03-03 Texas A & M University System Gate adjusted resonant tunnel diode device and method of manufacture
US5285086A (en) * 1990-08-02 1994-02-08 At&T Bell Laboratories Semiconductor devices with low dislocation defects
US5105247A (en) * 1990-08-03 1992-04-14 Cavanaugh Marion E Quantum field effect device with source extension region formed under a gate and between the source and drain regions
US5091767A (en) * 1991-03-18 1992-02-25 At&T Bell Laboratories Article comprising a lattice-mismatched semiconductor heterostructure
US5427976A (en) * 1991-03-27 1995-06-27 Nec Corporation Method of producing a semiconductor on insulating substrate, and a method of forming a transistor thereon
US5518953A (en) * 1991-09-24 1996-05-21 Rohm Co., Ltd. Method for manufacturing semiconductor device having grown layer on insulating layer
US5417180A (en) * 1991-10-24 1995-05-23 Rohm Co., Ltd. Method for forming SOI structure
US5432120A (en) * 1992-12-04 1995-07-11 Siemens Aktiengesellschaft Method for producing a laterally limited single-crystal region with selective epitaxy and the employment thereof for manufacturing a bipolar transistor as well as a MOS transistor
US5295150A (en) * 1992-12-11 1994-03-15 Eastman Kodak Company Distributed feedback-channeled substrate planar semiconductor laser
US5717709A (en) * 1993-06-04 1998-02-10 Sharp Kabushiki Kaisha Semiconductor light-emitting device capable of having good stability in fundamental mode of oscillation, decreasing current leakage, and lowering oscillation threshold limit, and method of making the same
US5640022A (en) * 1993-08-27 1997-06-17 Sanyo Electric Co., Inc. Quantum effect device
US6235547B1 (en) * 1994-04-28 2001-05-22 Fujitsu Limited Semiconductor device and method of fabricating the same
US6011271A (en) * 1994-04-28 2000-01-04 Fujitsu Limited Semiconductor device and method of fabricating the same
US5710436A (en) * 1994-09-27 1998-01-20 Kabushiki Kaisha Toshiba Quantum effect device
US6049098A (en) * 1995-04-27 2000-04-11 Nec Corporation Bipolar transistor having an emitter region formed of silicon carbide
US5621227A (en) * 1995-07-18 1997-04-15 Discovery Semiconductors, Inc. Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxy
US5886385A (en) * 1996-08-22 1999-03-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6191432B1 (en) * 1996-09-02 2001-02-20 Kabushiki Kaisha Toshiba Semiconductor device and memory device
US20020066403A1 (en) * 1997-03-13 2002-06-06 Nec Corporation Method for manufacturing group III-V compound semiconductors
US6348096B1 (en) * 1997-03-13 2002-02-19 Nec Corporation Method for manufacturing group III-V compound semiconductors
US6252261B1 (en) * 1998-09-30 2001-06-26 Nec Corporation GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor
US20020070383A1 (en) * 1999-03-31 2002-06-13 Naoki Shibata Group III nitride compound semiconductor device and method for producing the same
US6873009B2 (en) * 1999-05-13 2005-03-29 Hitachi, Ltd. Vertical semiconductor device with tunnel insulator in current path controlled by gate electrode
US6228691B1 (en) * 1999-06-30 2001-05-08 Intel Corp. Silicon-on-insulator devices and method for producing the same
US7033936B1 (en) * 1999-08-17 2006-04-25 Imperial Innovations Limited Process for making island arrays
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6512252B1 (en) * 1999-11-15 2003-01-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US7205586B2 (en) * 1999-11-15 2007-04-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device having SiGe channel region
US6753555B2 (en) * 1999-11-15 2004-06-22 Matsushita Electric Industrial Co., Ltd. DTMOS device having low threshold voltage
US6521514B1 (en) * 1999-11-17 2003-02-18 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates
US6727523B2 (en) * 1999-12-16 2004-04-27 Sony Corporation Method of manufacturing crystal of iii-v compounds of the nitride system, crystal substrate of iii-v compounds of the nitride system, crystal film of iii-v compounds of the nitride system, and method of manufacturing device
US7041178B2 (en) * 2000-02-16 2006-05-09 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6362071B1 (en) * 2000-04-05 2002-03-26 Motorola, Inc. Method for forming a semiconductor device with an opening in a dielectric layer
US6841808B2 (en) * 2000-06-23 2005-01-11 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method for producing the same
US20020030246A1 (en) * 2000-06-28 2002-03-14 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices not lattice matched to the substrate
US6579463B1 (en) * 2000-08-18 2003-06-17 The Regents Of The University Of Colorado Tunable nanomasks for pattern transfer and nanocluster array formation
US20030089899A1 (en) * 2000-08-22 2003-05-15 Lieber Charles M. Nanoscale wires and related devices
US6994751B2 (en) * 2001-02-27 2006-02-07 Sanyo Electric Co., Ltd. Nitride-based semiconductor element and method of forming nitride-based semiconductor
US6921673B2 (en) * 2001-03-27 2005-07-26 Sony Corporation Nitride semiconductor device and method of manufacturing the same
US7033436B2 (en) * 2001-04-12 2006-04-25 Sony Corporation Crystal growth method for nitride semiconductor and formation method for semiconductor device
US6720196B2 (en) * 2001-05-11 2004-04-13 Sanyo Electric Co., Ltd. Nitride-based semiconductor element and method of forming nitride-based semiconductor
US6841410B2 (en) * 2001-09-03 2005-01-11 Nec Corporation Method for forming group-III nitride semiconductor layer and group-III nitride semiconductor device
US20030045017A1 (en) * 2001-09-06 2003-03-06 Kazumasa Hiramatsu Method for fabricating III-V Group compound semiconductor
US20030064535A1 (en) * 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
US6710368B2 (en) * 2001-10-01 2004-03-23 Ken Scott Fisher Quantum tunneling transistor
US6576532B1 (en) * 2001-11-30 2003-06-10 Motorola Inc. Semiconductor device and method therefor
US20050118825A1 (en) * 2002-02-28 2005-06-02 Kazuki Nishijima Process for producing group III nitride compound semiconductor
US6900070B2 (en) * 2002-04-15 2005-05-31 The Regents Of The University Of California Dislocation reduction in non-polar gallium nitride thin films
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6887773B2 (en) * 2002-06-19 2005-05-03 Luxtera, Inc. Methods of incorporating germanium within CMOS process
US6917068B1 (en) * 2002-06-21 2005-07-12 Advanced Micro Devices, Inc. Semiconductor device having conductive structures formed near a gate electrode
US7012298B1 (en) * 2002-06-21 2006-03-14 Advanced Micro Devices, Inc. Non-volatile memory device
US6982204B2 (en) * 2002-07-16 2006-01-03 Cree, Inc. Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
US20040012037A1 (en) * 2002-07-18 2004-01-22 Motorola, Inc. Hetero-integration of semiconductor materials on silicon
US20060009012A1 (en) * 2002-08-23 2006-01-12 Amberwave Systems Corporation Methods of fabricating semiconductor heterostructures
US20040075105A1 (en) * 2002-08-23 2004-04-22 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US7049627B2 (en) * 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7015497B1 (en) * 2002-08-27 2006-03-21 The Ohio State University Self-aligned and self-limited quantum dot nanoswitches and methods for making same
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US20040105480A1 (en) * 2002-11-29 2004-06-03 Yakov Sidorin Tunable optical source
US20060128124A1 (en) * 2002-12-16 2006-06-15 Haskell Benjamin A Growth of reduced dislocation density non-polar gallium nitride by hydride vapor phase epitaxy
US20060049409A1 (en) * 2002-12-18 2006-03-09 Rafferty Conor S Method for forming integrated circuit utilizing dual semiconductors
US7012314B2 (en) * 2002-12-18 2006-03-14 Agere Systems Inc. Semiconductor devices with reduced active region defects and unique contacting schemes
US6686245B1 (en) * 2002-12-20 2004-02-03 Motorola, Inc. Vertical MOSFET with asymmetric gate structure
US20070029643A1 (en) * 2003-03-21 2007-02-08 Johnson Mark A L Methods for nanoscale structures from optical lithography and subsequent lateral growth
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US20050003572A1 (en) * 2003-04-30 2005-01-06 Osram Opto Semiconductors Gmbh Method for fabricating a plurality of semiconductor chips
US7211864B2 (en) * 2003-09-15 2007-05-01 Seliskar John J Fully-depleted castellated gate MOSFET device and method of manufacture thereof
US6919258B2 (en) * 2003-10-02 2005-07-19 Freescale Semiconductor, Inc. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
US7015517B2 (en) * 2003-10-02 2006-03-21 Freescale Semiconductor, Inc. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
US20050073028A1 (en) * 2003-10-02 2005-04-07 Grant John M. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
US20050104156A1 (en) * 2003-11-13 2005-05-19 Texas Instruments Incorporated Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes
US20050145954A1 (en) * 2004-01-05 2005-07-07 International Business Machines Corporation Structures and methods for making strained mosfets
US20050145941A1 (en) * 2004-01-07 2005-07-07 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US20050164475A1 (en) * 2004-01-23 2005-07-28 Martin Peckerar Technique for perfecting the active regions of wide bandgap semiconductor nitride devices
US7001804B2 (en) * 2004-01-30 2006-02-21 Atmel Germany Gmbh Method of producing active semiconductor layers of different thicknesses in an SOI wafer
US6995456B2 (en) * 2004-03-12 2006-02-07 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
US6998684B2 (en) * 2004-03-31 2006-02-14 International Business Machines Corporation High mobility plane CMOS SOI
US20060019462A1 (en) * 2004-07-23 2006-01-26 International Business Machines Corporation Patterned strained semiconductor substrate and device
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US20060131606A1 (en) * 2004-12-18 2006-06-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures employing seed layers and related fabrication methods
US20060145264A1 (en) * 2005-01-05 2006-07-06 Internaional Business Machines Corporation Stressed field effect transistors on hybrid orientation substrate
US20060160291A1 (en) * 2005-01-19 2006-07-20 Sharp Laboratories Of America, Inc. Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer
US7224033B2 (en) * 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US20070054465A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US20070105256A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated light emitting devices
US20070105274A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated semiconductor materials and devices
US20070105335A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated silicon and III-V electronics
US20080001169A1 (en) * 2006-03-24 2008-01-03 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication

Cited By (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987028B2 (en) 2005-05-17 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9431243B2 (en) 2005-05-17 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9219112B2 (en) 2005-05-17 2015-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8629477B2 (en) 2005-05-17 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8796734B2 (en) 2005-05-17 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8519436B2 (en) 2005-05-17 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US8878243B2 (en) 2006-03-24 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US10074536B2 (en) 2006-03-24 2018-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US20080099785A1 (en) * 2006-09-07 2008-05-01 Amberwave Systems Coporation Defect Reduction Using Aspect Ratio Trapping
US9318325B2 (en) 2006-09-07 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US9818819B2 (en) 2006-09-07 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US8847279B2 (en) 2006-09-07 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US8860160B2 (en) 2006-09-27 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US8216951B2 (en) 2006-09-27 2012-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US7799592B2 (en) 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US20080073641A1 (en) * 2006-09-27 2008-03-27 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US8629047B2 (en) 2006-09-27 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US9559712B2 (en) 2006-09-27 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US9105522B2 (en) 2006-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US8502263B2 (en) 2006-10-19 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light-emitter-based devices with lattice-mismatched semiconductor structures
US9040331B2 (en) 2007-04-09 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8624103B2 (en) 2007-04-09 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9853176B2 (en) 2007-04-09 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9449868B2 (en) 2007-04-09 2016-09-20 Taiwan Semiconductor Manufacutring Company, Ltd. Methods of forming semiconductor diodes by aspect ratio trapping with coalesced films
US9853118B2 (en) 2007-04-09 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US9231073B2 (en) 2007-04-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US9543472B2 (en) 2007-04-09 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
US9780190B2 (en) 2007-06-15 2017-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
US20090098343A1 (en) * 2007-07-26 2009-04-16 Chantal Arena Epitaxial methods and templates grown by the methods
US8574968B2 (en) * 2007-07-26 2013-11-05 Soitec Epitaxial methods and templates grown by the methods
US10002981B2 (en) 2007-09-07 2018-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-junction solar cells
US8344242B2 (en) 2007-09-07 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-junction solar cells
US8822248B2 (en) 2008-06-03 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial growth of crystalline material
US9365949B2 (en) 2008-06-03 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial growth of crystalline material
US9640395B2 (en) 2008-07-01 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8629045B2 (en) 2008-07-01 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US9356103B2 (en) 2008-07-01 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8994070B2 (en) 2008-07-01 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US9607846B2 (en) 2008-07-15 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US9287128B2 (en) 2008-07-15 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
WO2010033813A2 (en) * 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US9934967B2 (en) 2008-09-19 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Formation of devices by epitaxial layer overgrowth
US9984872B2 (en) 2008-09-19 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication and structures of crystalline material
WO2010033813A3 (en) * 2008-09-19 2010-06-03 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US8384196B2 (en) 2008-09-19 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of devices by epitaxial layer overgrowth
US20100216277A1 (en) * 2008-09-19 2010-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of Devices by Epitaxial Layer Overgrowth
US8034697B2 (en) 2008-09-19 2011-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of devices by epitaxial layer overgrowth
US9105549B2 (en) 2008-09-24 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US9455299B2 (en) 2008-09-24 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for semiconductor sensor structures with reduced dislocation defect densities
US8809106B2 (en) 2008-09-24 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for semiconductor sensor structures with reduced dislocation defect densities
US9029908B2 (en) 2009-01-09 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8765510B2 (en) 2009-01-09 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US9576951B2 (en) 2009-04-02 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US9299562B2 (en) 2009-04-02 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US8629446B2 (en) 2009-04-02 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US8242510B2 (en) * 2010-01-28 2012-08-14 Intersil Americas Inc. Monolithic integration of gallium nitride and silicon devices and circuits, structure and method
US20110180806A1 (en) * 2010-01-28 2011-07-28 Intersil Americas Inc. Monolithic integration of gallium nitride and silicon devices and circuits, structure and method
US20140054755A1 (en) * 2012-08-21 2014-02-27 Micron Technology, Inc. Methods of forming semiconductor device structures, and related semiconductor device structures
US9768123B2 (en) 2012-08-21 2017-09-19 Micron Technology, Inc. Semiconductor device structures including a distributed bragg reflector
US9159677B2 (en) * 2012-08-21 2015-10-13 Micron Technology, Inc. Methods of forming semiconductor device structures
US10014374B2 (en) 2013-12-18 2018-07-03 Intel Corporation Planar heterogeneous device
WO2015094219A1 (en) * 2013-12-18 2015-06-25 Intel Corporation Planar heterogeneous device
US10234629B2 (en) * 2013-12-20 2019-03-19 Huawei Technologies Co., Ltd. Method for reducing threading dislocation of semiconductor device
JP2017511596A (en) * 2013-12-20 2017-04-20 華為技術有限公司Huawei Technologies Co.,Ltd. The method of manufacturing a semiconductor device and a semiconductor device
EP3070751A4 (en) * 2013-12-20 2017-01-11 Huawei Technologies Co., Ltd. Semiconductor device and method for manufacturing same
EP3428957A1 (en) * 2013-12-20 2019-01-16 Huawei Technologies Co., Ltd. Method for producing semiconductor device
US20160291248A1 (en) * 2013-12-20 2016-10-06 Huawei Technologies Co.,Ltd. Semiconductor device and method for producing semiconductor device
US9818884B2 (en) 2014-03-28 2017-11-14 Intel Corporation Strain compensation in transistors
TWI565055B (en) * 2014-03-28 2017-01-01 Intel Corp Device with strain compensation and fabrication method thereof
WO2015147851A1 (en) * 2014-03-28 2015-10-01 Intel Corporation Strain compensation in transistors

Also Published As

Publication number Publication date
WO2008051503A2 (en) 2008-05-02
US20130252361A1 (en) 2013-09-26
US8502263B2 (en) 2013-08-06
US20080093622A1 (en) 2008-04-24
WO2008051503A3 (en) 2008-07-31

Similar Documents

Publication Publication Date Title
US6376866B1 (en) GaN semiconductor light emitting device having a group II-VI substrate
US6600169B2 (en) Quantum dash device
JP4032538B2 (en) The method of manufacturing a semiconductor thin film and a semiconductor element
US7781244B2 (en) Method of manufacturing nitride-composite semiconductor laser element, with disclocation control
US6984840B2 (en) Optical semiconductor device having an epitaxial layer of III-V compound semiconductor material containing N as a group V element
US6015979A (en) Nitride-based semiconductor element and method for manufacturing the same
US7160748B2 (en) Method for fabricating nitride semiconductor, method for fabricating nitride semiconductor device, and nitride semiconductor device
US5937274A (en) Fabrication method for AlGaIn NPAsSb based devices
US20150255566A1 (en) Diode-Based Devices and Methods for Making the Same
EP1473781A2 (en) Semiconductor light-emitting device and production method thereof
US20020094002A1 (en) Nitride semiconductor layer structure and a nitride semiconductor laser incorporating a portion of same
US6829270B2 (en) Nitride III-V compound semiconductor substrate, its manufacturing method, manufacturing method of a semiconductor light emitting device, and manufacturing method of a semiconductor device
US20070292979A1 (en) Semiconductor device and method of fabricating the same
CN102122675B (en) Photonic device and manufacturing method thereof
JP3988018B2 (en) Crystal film, crystal substrate and a semiconductor device
JP3830051B2 (en) A method of manufacturing a nitride semiconductor substrate, a nitride semiconductor substrate, manufacturing method and an optical semiconductor device of an optical semiconductor device
US5348912A (en) Semiconductor surface emitting laser having enhanced optical confinement
US6614059B1 (en) Semiconductor light-emitting device with quantum well
US5585309A (en) Method of making semiconductor laser
US5663592A (en) Semiconductor device having diffraction grating
EP2509119B1 (en) Light emitting element and method for manufacturing same
US20020168844A1 (en) Group III-V compound semiconductor crystal structure and method of epitaxial growth of the same as well as semiconductor device including the same
US6151347A (en) Laser diode and method of fabrication thereof
US7101444B2 (en) Defect-free semiconductor templates for epitaxial growth
US7242705B2 (en) Grating-outcoupled cavity resonator having uni-directional emission

Legal Events

Date Code Title Description
AS Assignment

Owner name: AMBERWAVE SYSTEMS CORPORATION, NEW HAMPSHIRE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LI, JIZHONG;REEL/FRAME:020207/0067

Effective date: 20071129

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION