FR2851372B1 - Procede de fabrication d'un substrat a couche isolante enterree - Google Patents

Procede de fabrication d'un substrat a couche isolante enterree

Info

Publication number
FR2851372B1
FR2851372B1 FR0401407A FR0401407A FR2851372B1 FR 2851372 B1 FR2851372 B1 FR 2851372B1 FR 0401407 A FR0401407 A FR 0401407A FR 0401407 A FR0401407 A FR 0401407A FR 2851372 B1 FR2851372 B1 FR 2851372B1
Authority
FR
France
Prior art keywords
insulating layer
layer substrate
manufacturing insulated
insulated insulating
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0401407A
Other languages
English (en)
Other versions
FR2851372A1 (fr
Inventor
Yasuo Kakizaki
Masataka Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of FR2851372A1 publication Critical patent/FR2851372A1/fr
Application granted granted Critical
Publication of FR2851372B1 publication Critical patent/FR2851372B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
FR0401407A 2003-02-14 2004-02-12 Procede de fabrication d'un substrat a couche isolante enterree Expired - Fee Related FR2851372B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003037404A JP2004247610A (ja) 2003-02-14 2003-02-14 基板の製造方法

Publications (2)

Publication Number Publication Date
FR2851372A1 FR2851372A1 (fr) 2004-08-20
FR2851372B1 true FR2851372B1 (fr) 2006-05-19

Family

ID=32767679

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0401407A Expired - Fee Related FR2851372B1 (fr) 2003-02-14 2004-02-12 Procede de fabrication d'un substrat a couche isolante enterree

Country Status (3)

Country Link
US (1) US7008860B2 (fr)
JP (1) JP2004247610A (fr)
FR (1) FR2851372B1 (fr)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090325362A1 (en) * 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
FR2892228B1 (fr) * 2005-10-18 2008-01-25 Soitec Silicon On Insulator Procede de recyclage d'une plaquette donneuse epitaxiee
JP4407127B2 (ja) * 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
TWI235407B (en) * 2004-05-10 2005-07-01 Mosel Vitelic Inc Wafer and the manufacturing and reclaiming method therefor
TWI240951B (en) * 2004-05-10 2005-10-01 Mosel Vitelic Inc Method for reclaiming wafer
JP4518886B2 (ja) * 2004-09-09 2010-08-04 シャープ株式会社 半導体素子の製造方法
EP1962340A3 (fr) * 2004-11-09 2009-12-23 S.O.I. TEC Silicon Procédé de fabrication de plaquettes composites
JP2006147711A (ja) * 2004-11-17 2006-06-08 Seiko Epson Corp 薄膜デバイス、薄膜デバイスの製造方法、集積回路、マトリクス装置、電子機器
JP2007079431A (ja) * 2005-09-16 2007-03-29 Toshiba Matsushita Display Technology Co Ltd 表示素子用アレイ基板及びその作製方法、これを用いた表示素子
US7568412B2 (en) * 2005-10-04 2009-08-04 Marquip, Llc Method for order transition on a plunge slitter
EP1777735A3 (fr) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Procédé de recyclage d'une plaquette donneuse épitaxiée
JP5042506B2 (ja) * 2006-02-16 2012-10-03 信越化学工業株式会社 半導体基板の製造方法
JP5249511B2 (ja) * 2006-11-22 2013-07-31 信越化学工業株式会社 Ｓｏｑ基板およびｓｏｑ基板の製造方法
WO2008082920A1 (fr) 2006-12-28 2008-07-10 Memc Electronic Materials, Inc. Procédé de production de plaquettes lisses
ATE518241T1 (de) * 2007-01-24 2011-08-15 Soitec Silicon On Insulator Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer
EP1986229A1 (fr) * 2007-04-27 2008-10-29 S.O.I.T.E.C. Silicon on Insulator Technologies Procédé de fabrication de galettes de matériau composé et galette de matériau composé correspondante
EP2040285A1 (fr) * 2007-09-19 2009-03-25 S.O.I. TEC Silicon Procédé de fabrication d'un substrat à orientation mixte
JP5654206B2 (ja) 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
EP2105957A3 (fr) * 2008-03-26 2011-01-19 Semiconductor Energy Laboratory Co., Ltd. Procédé de fabrication d'un substrat SOI et procédé de fabrication d'un dispositif semi-conducteur
FR2929758B1 (fr) * 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
JP4666189B2 (ja) * 2008-08-28 2011-04-06 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP5667743B2 (ja) * 2008-09-29 2015-02-12 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5364345B2 (ja) * 2008-11-12 2013-12-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5521339B2 (ja) * 2009-02-05 2014-06-11 信越半導体株式会社 多層膜付き半導体ウェーハの製造方法及び半導体デバイスの製造方法
CN102184882A (zh) * 2011-04-07 2011-09-14 中国科学院微电子研究所 一种形成复合功能材料结构的方法
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
WO2017065692A1 (fr) * 2015-10-13 2017-04-20 Nanyang Technological University Procédé de fabrication de substrat de germanium sur isolant
FR3073082B1 (fr) * 2017-10-31 2019-10-11 Soitec Procede de fabrication d'un film sur un support presentant une surface non plane
CN111180334A (zh) * 2020-01-15 2020-05-19 长江存储科技有限责任公司 半导体基底减薄方法
US20220238336A1 (en) * 2021-01-26 2022-07-28 Alliance For Sustainable Energy, Llc Facet suppression of gallium arsenide spalling using nanoimprint lithography and methods thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5909626A (en) * 1997-03-28 1999-06-01 Nec Corporation SOI substrate and fabrication process therefor
JP4302194B2 (ja) * 1997-04-25 2009-07-22 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US5985742A (en) * 1997-05-12 1999-11-16 Silicon Genesis Corporation Controlled cleavage process and device for patterned films
SG71903A1 (en) * 1998-01-30 2000-04-18 Canon Kk Process of reclamation of soi substrate and reproduced substrate
JP2000349266A (ja) * 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
JP2000349148A (ja) * 1999-06-08 2000-12-15 Sony Corp 半導体層を有する基板の製造方法
US6566233B2 (en) * 1999-12-24 2003-05-20 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
US6368947B1 (en) * 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6661025B2 (en) * 2000-09-22 2003-12-09 Seiko Epson Corporation Method of manufacturing electro-optical apparatus substrate, electro-optical apparatus substrate, electro-optical apparatus and electronic apparatus
JP2002154239A (ja) * 2000-11-17 2002-05-28 Canon Inc 画像処理方法およびプリント装置

Also Published As

Publication number Publication date
FR2851372A1 (fr) 2004-08-20
JP2004247610A (ja) 2004-09-02
US20040185638A1 (en) 2004-09-23
US7008860B2 (en) 2006-03-07

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Year of fee payment: 13

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Effective date: 20171031