FR2921749B1 - Procede de fabrication d'une structure comprenant un substrat et une couche deposee sur l'une de ses faces. - Google Patents
Procede de fabrication d'une structure comprenant un substrat et une couche deposee sur l'une de ses faces.Info
- Publication number
- FR2921749B1 FR2921749B1 FR0757891A FR0757891A FR2921749B1 FR 2921749 B1 FR2921749 B1 FR 2921749B1 FR 0757891 A FR0757891 A FR 0757891A FR 0757891 A FR0757891 A FR 0757891A FR 2921749 B1 FR2921749 B1 FR 2921749B1
- Authority
- FR
- France
- Prior art keywords
- faces
- substrate
- manufacturing
- layer deposited
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0757891A FR2921749B1 (fr) | 2007-09-27 | 2007-09-27 | Procede de fabrication d'une structure comprenant un substrat et une couche deposee sur l'une de ses faces. |
JP2010526267A JP5722038B2 (ja) | 2007-09-27 | 2008-09-23 | 基板とその一方の面上に堆積させた層とを含む構造体の製造方法 |
EP08804589A EP2203932A1 (fr) | 2007-09-27 | 2008-09-23 | Procédé de fabrication d'une structure comportant un substrat et une couche deposée sur une de ses faces |
US12/672,797 US20110192343A1 (en) | 2007-09-27 | 2008-09-23 | Method of manufacturing a structure comprising a substrate and a layer deposited on one of its faces |
CN200880108693.9A CN101809710B (zh) | 2007-09-27 | 2008-09-23 | 制造包括衬底和沉积在衬底的一个表面上的层的结构的方法 |
KR1020107009126A KR101097688B1 (ko) | 2007-09-27 | 2008-09-23 | 기판과 기판의 일 면에 증착되는 층을 포함하는 구조체를 제조하는 방법 |
PCT/EP2008/062670 WO2009040337A1 (fr) | 2007-09-27 | 2008-09-23 | Procédé de fabrication d'une structure comportant un substrat et une couche deposée sur une de ses faces |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0757891A FR2921749B1 (fr) | 2007-09-27 | 2007-09-27 | Procede de fabrication d'une structure comprenant un substrat et une couche deposee sur l'une de ses faces. |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2921749A1 FR2921749A1 (fr) | 2009-04-03 |
FR2921749B1 true FR2921749B1 (fr) | 2014-08-29 |
Family
ID=39678859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0757891A Active FR2921749B1 (fr) | 2007-09-27 | 2007-09-27 | Procede de fabrication d'une structure comprenant un substrat et une couche deposee sur l'une de ses faces. |
Country Status (7)
Country | Link |
---|---|
US (1) | US20110192343A1 (fr) |
EP (1) | EP2203932A1 (fr) |
JP (1) | JP5722038B2 (fr) |
KR (1) | KR101097688B1 (fr) |
CN (1) | CN101809710B (fr) |
FR (1) | FR2921749B1 (fr) |
WO (1) | WO2009040337A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6061251B2 (ja) | 2013-07-05 | 2017-01-18 | 株式会社豊田自動織機 | 半導体基板の製造方法 |
JP6661191B2 (ja) * | 2015-12-18 | 2020-03-11 | 株式会社テンシックス | 半導体基板の製造方法 |
US10971365B2 (en) * | 2017-02-21 | 2021-04-06 | Ev Group E. Thallner Gmbh | Method and device for bonding substrates |
FR3068508B1 (fr) * | 2017-06-30 | 2019-07-26 | Soitec | Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents |
FR3099637B1 (fr) | 2019-08-01 | 2021-07-09 | Soitec Silicon On Insulator | procédé de fabrication d’unE structure composite comprenant une couche mince en Sic monocristallin sur un substrat support en sic polycristallin |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63229751A (ja) * | 1987-03-19 | 1988-09-26 | Fujitsu Ltd | 赤外線検知素子の製造方法 |
JPH01220458A (ja) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | 半導体装置 |
JPH02175688A (ja) * | 1988-12-28 | 1990-07-06 | Asahi Chem Ind Co Ltd | 化合物半導体薄膜の成長法 |
US5296385A (en) * | 1991-12-31 | 1994-03-22 | Texas Instruments Incorporated | Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing |
JPH11251563A (ja) * | 1997-12-26 | 1999-09-17 | Canon Inc | Soi基板の熱処理方法及び熱処理装置並びにそれを用いたsoi基板の作製方法 |
US6350993B1 (en) * | 1999-03-12 | 2002-02-26 | International Business Machines Corporation | High speed composite p-channel Si/SiGe heterostructure for field effect devices |
US6881644B2 (en) * | 1999-04-21 | 2005-04-19 | Silicon Genesis Corporation | Smoothing method for cleaved films made using a release layer |
JP2000332021A (ja) * | 1999-05-18 | 2000-11-30 | Hitachi Ltd | Soi基板およびその製造方法ならびに半導体装置およびその製造方法 |
JP4450126B2 (ja) * | 2000-01-21 | 2010-04-14 | 日新電機株式会社 | シリコン系結晶薄膜の形成方法 |
KR20020036916A (ko) * | 2000-11-11 | 2002-05-17 | 주승기 | 실리콘 박막의 결정화 방법 및 이에 의해 제조된 반도체소자 |
FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
JP4802380B2 (ja) * | 2001-03-19 | 2011-10-26 | 株式会社デンソー | 半導体基板の製造方法 |
JP4556158B2 (ja) * | 2002-10-22 | 2010-10-06 | 株式会社Sumco | 貼り合わせsoi基板の製造方法および半導体装置 |
DE10250915B4 (de) * | 2002-10-31 | 2009-01-22 | Osram Opto Semiconductors Gmbh | Verfahren zur Abscheidung eines Materials auf einem Substratwafer |
WO2006082467A1 (fr) * | 2005-02-01 | 2006-08-10 | S.O.I.Tec Silicon On Insulator Technologies | Substrat destine a la cristallogenese d'un semi-conducteur de nitrure |
JP4934966B2 (ja) * | 2005-02-04 | 2012-05-23 | 株式会社Sumco | Soi基板の製造方法 |
-
2007
- 2007-09-27 FR FR0757891A patent/FR2921749B1/fr active Active
-
2008
- 2008-09-23 WO PCT/EP2008/062670 patent/WO2009040337A1/fr active Application Filing
- 2008-09-23 CN CN200880108693.9A patent/CN101809710B/zh not_active Expired - Fee Related
- 2008-09-23 EP EP08804589A patent/EP2203932A1/fr not_active Withdrawn
- 2008-09-23 JP JP2010526267A patent/JP5722038B2/ja not_active Expired - Fee Related
- 2008-09-23 KR KR1020107009126A patent/KR101097688B1/ko not_active IP Right Cessation
- 2008-09-23 US US12/672,797 patent/US20110192343A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
KR20100067117A (ko) | 2010-06-18 |
JP5722038B2 (ja) | 2015-05-20 |
KR101097688B1 (ko) | 2011-12-22 |
CN101809710A (zh) | 2010-08-18 |
US20110192343A1 (en) | 2011-08-11 |
FR2921749A1 (fr) | 2009-04-03 |
WO2009040337A1 (fr) | 2009-04-02 |
JP2010541230A (ja) | 2010-12-24 |
EP2203932A1 (fr) | 2010-07-07 |
CN101809710B (zh) | 2012-01-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
|
PLFP | Fee payment |
Year of fee payment: 10 |
|
PLFP | Fee payment |
Year of fee payment: 11 |