WO2006082467A1 - Substrat destine a la cristallogenese d'un semi-conducteur de nitrure - Google Patents

Substrat destine a la cristallogenese d'un semi-conducteur de nitrure Download PDF

Info

Publication number
WO2006082467A1
WO2006082467A1 PCT/IB2005/000436 IB2005000436W WO2006082467A1 WO 2006082467 A1 WO2006082467 A1 WO 2006082467A1 IB 2005000436 W IB2005000436 W IB 2005000436W WO 2006082467 A1 WO2006082467 A1 WO 2006082467A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
forming
support
previous
Prior art date
Application number
PCT/IB2005/000436
Other languages
English (en)
Inventor
Bruce Faure
Fabrice Letertre
Hacène Lahreche
Original Assignee
S.O.I.Tec Silicon On Insulator Technologies
Picogiga International
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S.O.I.Tec Silicon On Insulator Technologies, Picogiga International filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to PCT/IB2005/000436 priority Critical patent/WO2006082467A1/fr
Publication of WO2006082467A1 publication Critical patent/WO2006082467A1/fr

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • This invention relates to a substrate used as a support for a crystalline growth, especially heteroepitaxy of nitrides such as gallium nitride (GaN), aluminium nitride (AIN), indium nitride (InN), and alloys of this compounds (AIGaN, InGaN, ...), as well as the manufacturing of such a substrate.
  • nitrides such as gallium nitride (GaN), aluminium nitride (AIN), indium nitride (InN), and alloys of this compounds (AIGaN, InGaN, ...), as well as the manufacturing of such a substrate.
  • Nitride materials are mainly used for optics or optoelectronics applications, such alloys can be for instance found in LEDs and LDs.
  • a first main application is found in light transmitters of electromagnetic radiation with wavelength below 500 nm, particularly colours from green (500-578 nm) to ultraviolet (280-400 nm), through the blue. Indeed, these wavelengths are accessible due the fact that the gap bandwith of such nitrides semiconductors can be varied function of their composition in the requested wavelength range.
  • nitrides semiconductors have properties of charge transport (high saturation velocity of the carriers under high voltage, high breakdown voltage,...) better than materials like SiC or AsGa for high-frequency power applications.
  • the HEMT type components obtained based on GaN and AIGaN type materials have already shown greater performances for high-frequency power applications.
  • Such nitrides semiconductors are usually manufactured by crystalline growth on substrates mainly chosen among sapphire (AI 2 O 3 ) and silicon carbide (SiC).
  • substrates mainly chosen among sapphire (AI 2 O 3 ) and silicon carbide (SiC).
  • Other substrates can be used, such as (111 ) silicon (Si), gallium arsenide (AsGa), or composite substrates (made of different layers of such materials) obtained by various technique such as Smart-Cut® (for more details on Smart-Cut® technique, see for instance "Silicon-On- Insulator Technology: Materials to VLSE, 2 nd Edition" of J. P. Collinge, Kluwer Academic Publishers, p. 50-51 ).
  • Smart-Cut® for more details on Smart-Cut® technique, see for instance "Silicon-On- Insulator Technology: Materials to VLSE, 2 nd Edition" of J. P. Collinge, Kluwer Academic Publishers, p. 50-51 ).
  • the crystalline growth of nitrides semiconductor materials can, be performed by different techniques, mainly epitaxy techniques like MBE (Molecular Beam Epitaxy), MOCVD (Metallo-Organic Chemical Vapour Deposition) and HVPE (Hydride Vapour Phase Epitaxy).
  • MBE Molecular Beam Epitaxy
  • MOCVD Metallo-Organic Chemical Vapour Deposition
  • HVPE Hydride Vapour Phase Epitaxy
  • MBE Molecular Beam Epitaxy
  • MOCVD Metallo-Organic Chemical Vapour Deposition
  • HVPE Hydride Vapour Phase Epitaxy
  • the substrate temperature has to be known very precisely for improving the readability and the performance of the crystalline growth process.
  • the substrate temperature can be controlled by the measurements of the gas temperature.
  • lots of materials typically used as support for the crystalline growth of nitrides semiconductors are transparent to infrared wavelengths range, such as SiC and sapphire.
  • wafers made of such materials cannot be measured easily by infrared measurements, due to the fact that they are not transmitters of infrared wavelength. Additionally, wafers made of such materials cannot be substrates for MBE epitaxy of nitrides semiconductors which requires an infrared heating of the substrate (as previously discussed).
  • the invention proposes, according to a first aspect, a substrate for crystalline growing an alloy, comprising at least one atomic element of column III and nitrogen, on the front side of the substrate, characterized in that the substrate comprises in its rear side a rear layer of a non-metallic infrared-absorptive/emittive material.
  • a substrate for crystalline growing an alloy comprising at least one atomic element of column III and nitrogen, on the front side of the substrate, characterized in that the substrate comprises in its rear side a rear layer of a non-metallic infrared-absorptive/emittive material.
  • Other possible characteristics of this substrate are:
  • the rear layer is of an amorphous material or a polycrystalline material, such as amorphous silicon or polysilicon;
  • the substrate further comprises a bulk structure; - the bulk structure is transparent to infrared;
  • the bulk structure is of SiC, sapphire (AI 2 O 3 ), GaN, AIN, or ZnO;
  • the front face is a free face of the bulk structure
  • the substrate further comprises a composite structure, the composite structure comprising a mechanical support and a front layer, the front face of the substrate being the free surface of the front layer;
  • the front layer is of Si with (111) crystalline orientation, SiC, sapphire (AI 2 O 3 ), AsGa, GaN, AIN, or ZnO;
  • the mechanical support is of an infrared - transparent material
  • the mechanical support is of SiC, AIN, sapphire (AI 2 O 3 ), GaN, ZnO, or diamond;
  • the invention proposes a wafer comprising the said substrate and a layer of an alloy comprising at least one atomic element of column III and nitrogen.
  • the invention proposes a method of manufacturing a substrate used as a support for the crystalline growth of an alloy comprising at least one atomic element of column III and nitrogen on the front side of this substrate, characterized in that it comprises the forming of a rear layer, on the rear side of a wafer, with a non-metallic infrared- absorptive/emittive material.
  • Other possible aspects of this method of manufacturing a substrate are:
  • the technique for forming the rear layer is chosen among technique for forming a layer of an amorphous material or a layer of a polycrystalline material; - the technique for forming the rear layer is chosen among technique for forming an amorphous silicon layer or of a polysilicon layer;
  • the method further comprises, before the forming of the rear layer, the forming of a protection layer, for example of SiO 2 , on the front side of the substrate so as to protect the front side of the substrate from the atomic elements used during the forming of the rear layer;
  • a protection layer for example of SiO 2
  • the rear layer is formed on the rear side of a bulk structure, the substrate being then constituted of the bulk structure and the rear layer;
  • the bulk structure is of SiC, sapphire (AI 2 O 3 ), GaN, AIN, or ZnO;
  • the substrate further comprises the forming of a composite structure, the composite structure comprising a support structure and a front layer, the substrate then comprising the composite structure and the rear layer, the front face of the substrate being the free surface of the front layer;
  • the front layer is formed on the support structure by implementing the following steps: S providing a donor substrate with a crystalline material on top of it, this crystalline material being the same as those of the front layer to be formed;
  • the front layer is formed on the support structure by implementing the following steps:
  • the forming of the front layer on the support substrate further comprises, before the bonding step, the forming of at least one bonding layer, for example of SiO 2 or Si 3 N 4 , on the top face of the donor substrate, on the bonding face of the support substrate or on both of them;
  • the method further comprises a step of finishing the surface of the detached layer of material in order to finally have the front layer with a smoothed and cleaned surface;
  • the rear layer is formed after the forming of the front layer or before the bonding step;
  • the front layer is of Si with (111 ) crystalline orientation, SiC, sapphire (AI 2 O 3 ), AsGa, GaN, AIN, or ZnO;
  • the support structure is of SiC, sapphire (AI 2 O 3 ), AIN, GaN, ZnO, or diamond.
  • Figure 1 shows a first substrate for crystalline growth of nitride semiconductor according to the invention.
  • Figure 2 shows a second substrate for crystalline growth of nitride semiconductor according to the invention.
  • Figure 3 shows a third substrate for crystalline growth of nitride semiconductor according to the invention.
  • Figures 4a to 4d show different steps of a first method of manufacturing of a substrate according to the invention.
  • Figures 5a to 5g show different steps of a method of manufacturing a composite substrate according to the invention.
  • Figures 6a to 6g show different steps of another method of manufacturing a composite substrate according to the invention.
  • Figures 7a to 7e show different steps of another method of manufacturing a composite structure according to the invention.
  • a substrate 10 for crystal growth of nitrides semiconductors such as alloys comprising at least one atomic element of column III and a nitrogen like InN, GaN, AIN, or compounds of one of these elements, is shown.
  • This crystal growth will occur on the front side 1 of the substrate 10.
  • This front side is "epi-ready", meaning it has a surface prepared for the next nucleation.
  • the substrate 10 is here composed of two parts: - a support structure 11 for the further crystal growth, which has a free surface 1 which defines the front side 1 of the substrate 10 for receiving the deposited elements during the crystal growth, the front side 1 being used as a nucleation surface during crystal growth; - a rear layer 12 included in the rear side 2 of the substrate 10 made of a non metallic infrared absorptive material.
  • the support structure 11 is a bulk structure made of a monocrystalline or polycristalline material, such as SiC, sapphire, AIN, GaN, or ZnO which are adapted materials for crystal growth of nitrides semiconductors.
  • a monocrystalline or polycristalline material such as SiC, sapphire, AIN, GaN, or ZnO which are adapted materials for crystal growth of nitrides semiconductors.
  • the support structure 11 is composed of a mechanical structure 14, for example of a bulk SiC or a bulk sapphire, and a front layer 13 made of a semiconductor material chosen for receiving on its free surface 1 the deposited nitrides elements during the crystal growth.
  • the mechanical structure 14 can be made of a material chosen among polycrystalline SiC, polycrystalline AIN, Sapphire, ZnO, GaN, diamond.
  • the front layer 13 can be made of a material chosen among monocrystalline Si(111 ), monocrystalline SiC (6H, 4H or 3C), GaN, AIN, ZnO, AsGa, sapphire.
  • the support structure 11 is composed of a mechanical structure 14, for example made of SiC or sapphire, a front layer 13 for receiving the deposited nitrides elements during crystal growth, and a buried dielectric material 16 between said front layer 13 and said mechanical structure 14.
  • the buried layer 16 can be made of silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), or silicon oxinitride (Si x O y N z ), or other dielectric material.
  • the materials chosen for the mechanical structure 14 and for the front layer 13 can be identical to those chosen in the second embodiment.
  • the rear layer 12 is made of a non-metallic infrared-absorptive/emittive material.
  • This rear layer 12 can be made of silicon, in a polycrystalline state or in an amorphous state. This material is well adapted for the present application as the polycrystalline state or amorphous state can be easily obtained on all types of substrates, with known epitaxy techniques like LPCVD (Low Pressure Chemical Vapour Deposition) or PECVD (Plasma Enhanced Chemical Vapour Deposition). Furthermore, the silicon is one of the least expensive materials used in electronics. Additionally, a rear layer 12 sufficiently thick (i.e.
  • the infrared absorption by and emission from the rear layer 12 allow the readability of the temperature (for example by means of an optical pyrometer), and can eventually allow the heating of the substrate by infrared radiation in the case of MBE growth.
  • the presence of the rear layer 12 in the substrate 10 allows a temperature measurement by infrared detection, and eventually a heating of the substrate 10 by infrared (especially in the case of a MBE epitaxy operating on this substrate 10 for forming the nitride semiconductor).
  • This rear layer 12 is especially useful when the support structure 11 is of an infrared-transparent bulk material such as bulk SiC or bulk sapphire, or when the support structure is a composite structure globally transparent to infrared (referring to figures 2 and 3) composed of a mechanical support 14 transparent to infrared and a front layer 13 (used for the nucleation of the crystal growth) not thick enough to absorb and transmit sufficiently the infrared radiation.
  • such a composite support structure 11 is typically manufactured by epitaxy or by the Smart-Cut® technique.
  • the Smart-Cut® technique implies firstly the formation of an embrittlement zone in a wafer by atomic implantation, then a bonding of this wafer to the mechanical support 14, and finally the formation of the front layer 13 by detaching it from the donor substrate at the embrittlement zone.
  • polycrystalline silicon can be preferred for the rear layer 12, thanks to its perfect compatibility with the known techniques (chemical cleaning, ...) for preparing the substrate 10 to the further crystal growth on the front side 1.
  • the polysilicon is stable even at high temperature (around 1 ,200 0 C). Additionally, it becomes more absorbent for infrareds at high temperature and it is perfectly clean for the under ultra high vacuum that exists in frames for MBE.
  • a first embodiment of manufacturing a substrate 10 according to the invention is shown.
  • a wafer 11 nextly called a support structure 11 , is provided.
  • This support structure 11 can be made of a crystalline bulk structure, such as a monocrystalline SiC, a polycrystalline SiC, a monocrystalline AIN 1 a polycrystalline AIN, a monocrystalline sapphire, a monocrystalline ZnO, a polycrystalline ZnO, a monocrystalline GaN, a polycrystalline GaN.
  • a crystalline bulk structure such as a monocrystalline SiC, a polycrystalline SiC, a monocrystalline AIN 1 a polycrystalline AIN, a monocrystalline sapphire, a monocrystalline ZnO, a polycrystalline ZnO, a monocrystalline GaN, a polycrystalline GaN.
  • this support structure 11 can also be a composite structure (not shown) composed of a substrate and at least one layer epitaxied on the substrate.
  • Materials of the support substrate 11 are chosen for processing a crystal growth of nitrides on the front surface 1.
  • a protection layer 15 is eventually formed on the front side 1 of the support substrate 11.
  • This protection layer 15 is formed so as to protect the front side 1 of the support substrate 11 the treatment implemented during next steps. Indeed, the front side 1 of the support substrate 11 can be already prepared for receiving the deposited elements of the next crystal growth of nitrides, and protection of it is then preferred.
  • the protection layer 15 can be for instance of Si ⁇ 2 with a sufficient thickness to protect the front side 1 from the next implemented treatments. If a thermal oxidation is used, Si ⁇ 2 material is formed on both face of the substrate (not shown in fig 4b).
  • a rear layer 12 is formed on the rear side of the support substrate 11 with a non-metallic infrared-absorptive/emittive material.
  • This rear layer 12 can be formed by deposition of polycrystal silicon or amorphous silicon, done for example by LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Ehanced Chemical Vapor Deposition) at low temperature (typically less than 500°C).
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PECVD Pullasma Ehanced Chemical Vapor Deposition
  • This deposition of the rear layer 12 is processed for forming a rear layer 12 sufficiently thick for both absorbing and emitting sufficient infrared radiation, in the nitrides crystal growth conditions, for being detected by infrared measurements means (like an optical pyrometer). For example, a thickness of about or more than 1 ⁇ m can be sufficient for performing this result.
  • the thickness of the rear layer 12 can also be sufficient for heating the support structure during nitrides MBE.
  • the method further comprises a step of removing these elements on the front side, using for example an etching onto the protection layer 15.
  • a first method for performing such a chemical etching can include a first step of thermal oxidation if the protection layer 12 comprises silicon, or a Si ⁇ 2 deposition compatible with the said elements.
  • Oxide is formed by any technique on the substrate 11 to protect it during front side layer 12 removal. Removing parasitic layer 12 on layer 15 on the front side is then made by etching using a selective etching between layer 12 material and layer 15 material. By this way, surface 1 is completely protected.
  • the removal of the said deposited elements on the front face of the support substrate 11 is performed by spin-etching.
  • the substrate is rotated and a spray of an etch agent is directed to the front side for etching the silicon, the etch agent chosen can be for example TMAH in solution.
  • a dry etch assisted by plasma (also called RIE for Reactive Ion Etching) is chosen by employing SFe or NF 3 agents for removing the silicon elements.
  • This kind of etching is selective due to its great efficiency for silicon removing and its no efficiency for SiO 2 removing, the Si ⁇ 2 layer being then an etch stop. We can then succeed of suppressing any silicon element on the substrate without damaging the front side 1 for the next nucleation.
  • a step of removing the protection layer 15 is processed in order to reveal the front surface 1 of the substrate which will be used as a nucleation surface for the next crystal growth of nitride layer(s).
  • the protection layer 15 is of Si ⁇ 2
  • a HF solution can be used.
  • the front side 1 of the substrate 10 may then be prepared for being
  • CMP chemico-mechanical planarization
  • SC1 and SC2 solutions chemical cleaning
  • the protection layer 15 can be kept at the front side of the substrate 10 for being removed later, when the substrate 10 will be used as a receiver of the deposit elements of the next nitride crystal growth.
  • FIGS. 5a to 5g and figures 6a to 6g are respectively shown different steps of manufacturing a composite substrate 10 according to the invention, by using a Smart-Cut® technique.
  • a donor wafer 20 is provided.
  • This donor wafer 20 is either a bulk structure, or a composite structure like a structure having a template layer.
  • the donor wafer 20 is of monocrystalline Si with (111 ) crystal orientation, a monocrystalline SiC 6H, 4H or 3C, or is a substrate with a template layer of GaN on one side obtained by standard GaN epitaxy technique, or a GaN bulk substrate.
  • This donor wafer 20 is then implanted by atomic species with determinate atomic species to be implanted, and determinate proportion and energy conditions. This implantation is implemented so as to form an embrittlement zone 25 at a determinate depth in the donor wafer 20 with a determinate mechanical weakness.
  • these atomic species are H + between 2E16 and 5E17 atoms/cm 2 , especially between 5E16 and 8E16 atoms/cm 2 , implanted with energy between 10 and 210 keV, especially between 20 and 120 keV.
  • a dielectric layer is formed on the surface to be implanted.
  • This dielectric layer can be an oxide (Si ⁇ 2 ) with a thickness between for example 10 and 10,000 nm, especially between 50 and 5,000 nm.
  • the implanted surface of the donor wafer 20 is then optionally cleaned for eliminating contaminants (metallic elements, particulars, hydrocarbures) and for improving the surface hydrophily.
  • this dielectric layer can be completely removed.
  • a mechanical support 14 is put into contact with the donor wafer 20 at the implanted surface.
  • a dielectric layer was previously formed on the surface of the mechanical support 14 to be bonded.
  • the surface of the mechanical support 14 to be bonded can be prepared to the bonding by processing techniques such as a cleaning for improving its hydrophily and/or for removing contaminants.
  • both surfaces to be bonded can be implemented, such as CMP or plasma activation by oxygen, argon, or nitrogen ions for improving the bonding energy.
  • Both donor substrate 20 and mechanical support 14 thus prepared are put into contact, for example at room temperature.
  • a front layer 13 is taken from the donor wafer 20 by detaching it at the embrittlement zone 25.
  • an energy is provided, such as a thermal energy and/or a mechanical energy.
  • a finishing of the surface of the front layer 13 is processed in order to remove roughness and contaminants that may exist on the front surface 1.
  • this front surface 1 can be prepared for becoming a "epi- ready" surface (i.e. ready for receiving deposited elements of the nitrides crystal growth) by processing for example a CMP and a chemical etching.
  • FIGS 5e, 5f and 5g show steps of the method according to the invention respectively identical to the steps shown in figures 4b, 4c and 4d.
  • the substrate 10 is composed of a rear layer 12 and a composite support structure 11 composed of a mechanical support 14 and a front layer 13.
  • the front side 1 of the substrate 10 aiming to receive the deposited elements for the next crystal growth of nitride layer(s) is the free side of the front layer 13.
  • the final substrate 10, referring to figure 6g, is then the same as the substrate 10 illustrated by figure 5g.
  • FIGS. 7a to 7e are respectively shown different steps of manufacturing a composite substrate 10 according to the invention, by using a "back thinning" technique.
  • a donor wafer 20 is provided.
  • This donor wafer 20 is either a bulk structure, or a composite structure like a structure having a template layer.
  • the donor wafer 20 is of monocrystalline Si with (111 ) crystal orientation, or a monocrystalline SiC 6H, 4H or 3C, or a substrate with a template layer of GaN on one side obtained by standard GaN epitaxy technique, or GaN bulk substrate.
  • a mechanical support 14 is provided.
  • This mechanical support 14 is either a bulk structure, or a composite structure like a structure having a template layer.
  • the mechanical support 14 is of SiC 6H, 4H or 3C, AIN, Si (111 ), or sapphire (AI 2 O 3 ), in a monocrystalline or polycrystalline orientation.
  • the mechanical support 14 is put into contact with the donor wafer 20. A molecular adhesion may then occur.
  • a dielectric layer was previously formed on the surface of the mechanical support 14 to be bonded and/or on the surface of the donor wafer 20 to be bonded.
  • the surface of the mechanical support 14 to be bonded can be prepared to the bonding by processing techniques such as a chemical cleaning for improving its hydrophily and/or for removing contaminants.
  • both surfaces to be bonded can be implemented, such as CMP or plasma activation by oxygen, argon, or nitrogen ions for improving the bonding energy.
  • Both donor substrate 20 and mechanical support 14 thus prepared are put into contact, for example at room temperature.
  • FIG. 7d shows the forming of the rear layer 12 on the free side of the mechanical support 14 with a non-metallic infrared-absorptive/emittive material.
  • This rear layer 12 can be formed by deposition of polycrystal silicon or amorphous silicon, done for example by LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Ehanced Chemical Vapor Deposition) at low temperature (typically less than 500 0 C).
  • This deposition of the rear layer 12 is processed for forming a rear layer 12 sufficiently thick for both absorbing and emitting sufficient infrared radiation, in the nitrides crystal growth conditions, for being detected by infrared measurements means (like an optical pyrometer). For example, a thickness of about or more than 1 ⁇ m can be sufficient for performing this result.
  • the thickness of the rear layer 12 can also be sufficient for heating the support structure during nitrides MBE.
  • a step of thinning the donor substrate 20 is processed, so as to only keep a front layer 13 on the mechanical support 14.
  • Methods of thinning such as polishing, etching, grinding, can then be used for reducing the donor substrate 20 until a thickness of about a few ten micrometers. Then, various techniques of CMP are used to finally obtain a remained front layer 13 having a thickness less than 1 micrometer, with a surface "epi- ready".
  • the substrate 10 is composed of a rear layer 12 and a composite support structure 11 composed of a mechanical support 14 and a front layer 13.
  • the front side 1 of the substrate 10 aiming to receive the deposited elements for the next crystal growth of nitride layer(s) is the free side of the front layer 13.
  • rear layer 12 can also be formed at any steps of formation of the substrate 10. Then, rear layer 12 can also be formed before bonding, or after thinning.
  • the front side 1 of the substrate 10 is then a nucleation surface of the crystal growth of a semiconductor nitride, such as gallium nitride (GaN), aluminium nitride (AIN), indium nitride (InN), and alloys of this compounds (AIGaN, InGaN, ).
  • a semiconductor nitride such as gallium nitride (GaN), aluminium nitride (AIN), indium nitride (InN), and alloys of this compounds (AIGaN, InGaN, ).
  • the substrate 10 is heated by an indirect heating of the gaseous atmosphere around the substrate.
  • the substrate 10 is heated by a direct heating of the substrate by infrared absorption.
  • This epitaxy is possible with the substrate 10 according to the invention even if a main part of the wafer is of an infrared transparent material, the rear layer 12 having a sufficient thickness for sufficiently heating the whole substrate 10.
  • a better control of the temperature is reached, by way of having added to the substrate 10 an infrared- absorptive/emittive layer 12 able to increase the infrared radiation of the substrate 10 at the crystal growth temperatures. Then the detection of the temperature by measuring means (by for example an optical pyrometer) is better, and the temperature measurement is improved.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un substrat (10) destiné à la cristallogénène d'un alliage et comprenant au moins un élément atomique de la colonne III et d'azote, sur la face frontale (1) du substrat (10). L'invention est caractérisée en ce que le substrat (10) comprend sur sa face arrière (2) une couche arrière (12) d'un matériau absorbant/émettant l'infrarouge non métallique. L'invention concerne également une plaquette comportant un tel substrat et une couche générée sur ce substrat. L'invention concerne enfin le procédé de production de ce substrat.
PCT/IB2005/000436 2005-02-01 2005-02-01 Substrat destine a la cristallogenese d'un semi-conducteur de nitrure WO2006082467A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IB2005/000436 WO2006082467A1 (fr) 2005-02-01 2005-02-01 Substrat destine a la cristallogenese d'un semi-conducteur de nitrure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2005/000436 WO2006082467A1 (fr) 2005-02-01 2005-02-01 Substrat destine a la cristallogenese d'un semi-conducteur de nitrure

Publications (1)

Publication Number Publication Date
WO2006082467A1 true WO2006082467A1 (fr) 2006-08-10

Family

ID=34960711

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/000436 WO2006082467A1 (fr) 2005-02-01 2005-02-01 Substrat destine a la cristallogenese d'un semi-conducteur de nitrure

Country Status (1)

Country Link
WO (1) WO2006082467A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2905799A1 (fr) * 2006-09-12 2008-03-14 Soitec Silicon On Insulator Realisation d'un substrat en gan
FR2914488A1 (fr) * 2007-03-30 2008-10-03 Soitec Silicon On Insulator Substrat chauffage dope
WO2009040337A1 (fr) * 2007-09-27 2009-04-02 S.O.I.Tec Silicon On Insulator Technologies Procédé de fabrication d'une structure comportant un substrat et une couche deposée sur une de ses faces
EP2357660A1 (fr) * 2008-12-11 2011-08-17 Shin-Etsu Chemical Co., Ltd. Procédé de fabrication d un substrat composite sur lequel un semi-conducteur à large bande interdite est stratifié
WO2013051163A1 (fr) * 2011-10-07 2013-04-11 住友電気工業株式会社 Procédé de fabrication de film de gan et substrat composite utilisé dans ledit procédé
EP4177645A1 (fr) * 2021-11-05 2023-05-10 Samsung Electronics Co., Ltd. Dispositif optique et son procédé de fabrication

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0449524A2 (fr) * 1990-03-24 1991-10-02 Canon Kabushiki Kaisha Méthode de recuit optique pour couche semi-conductrice et procédé de fabrication d'un composant semi-conducteur utilisant cette couche semi-conductrice
US5296385A (en) * 1991-12-31 1994-03-22 Texas Instruments Incorporated Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing
US6455398B1 (en) * 1999-07-16 2002-09-24 Massachusetts Institute Of Technology Silicon on III-V semiconductor bonding for monolithic optoelectronic integration
EP1408545A2 (fr) * 2002-10-07 2004-04-14 S.O.I. Tec Silicon on Insulator Technologies Procédé pour réaliser un substrat par transfert d'une plaquette donneuse comportant des espèces étrangères, et plaquette donneuse associée
US20040152312A1 (en) * 2002-10-31 2004-08-05 Osram Opto Semiconductors Gmbh Method for depositing a material on a substrate wafer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0449524A2 (fr) * 1990-03-24 1991-10-02 Canon Kabushiki Kaisha Méthode de recuit optique pour couche semi-conductrice et procédé de fabrication d'un composant semi-conducteur utilisant cette couche semi-conductrice
US5296385A (en) * 1991-12-31 1994-03-22 Texas Instruments Incorporated Conditioning of semiconductor wafers for uniform and repeatable rapid thermal processing
US6455398B1 (en) * 1999-07-16 2002-09-24 Massachusetts Institute Of Technology Silicon on III-V semiconductor bonding for monolithic optoelectronic integration
EP1408545A2 (fr) * 2002-10-07 2004-04-14 S.O.I. Tec Silicon on Insulator Technologies Procédé pour réaliser un substrat par transfert d'une plaquette donneuse comportant des espèces étrangères, et plaquette donneuse associée
US20040152312A1 (en) * 2002-10-31 2004-08-05 Osram Opto Semiconductors Gmbh Method for depositing a material on a substrate wafer

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008031809A1 (fr) * 2006-09-12 2008-03-20 S.O.I.Tec Silicon On Insulator Technologies PROCÉDÉ DE FABRICATION D'UN SUBSTRAT DE GaN
KR101236213B1 (ko) * 2006-09-12 2013-02-22 소이텍 질화갈륨 기판을 형성하기 위한 프로세스
FR2905799A1 (fr) * 2006-09-12 2008-03-14 Soitec Silicon On Insulator Realisation d'un substrat en gan
JP2010502555A (ja) * 2006-09-12 2010-01-28 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ ＧａＮ基板の製造方法
US8263984B2 (en) 2006-09-12 2012-09-11 Soitec Process for making a GaN substrate
US8198628B2 (en) 2007-03-30 2012-06-12 Soitec Doped substrate to be heated
FR2914488A1 (fr) * 2007-03-30 2008-10-03 Soitec Silicon On Insulator Substrat chauffage dope
WO2008120092A1 (fr) * 2007-03-30 2008-10-09 S.O.I.Tec Silicon On Insulator Technologies Substrat dopé devant être chauffé
US20100044705A1 (en) * 2007-03-30 2010-02-25 Robert Langer Doped substrate to be heated
FR2921749A1 (fr) * 2007-09-27 2009-04-03 Soitec Silicon On Insulator Procede de fabrication d'une structure comprenant un substrat et une couche deposee sur l'une de ses faces.
KR101097688B1 (ko) 2007-09-27 2011-12-22 소이텍 기판과 기판의 일 면에 증착되는 층을 포함하는 구조체를 제조하는 방법
CN101809710B (zh) * 2007-09-27 2012-01-11 S.O.I.Tec绝缘体上硅技术公司 制造包括衬底和沉积在衬底的一个表面上的层的结构的方法
US20110192343A1 (en) * 2007-09-27 2011-08-11 Hocine Abir Method of manufacturing a structure comprising a substrate and a layer deposited on one of its faces
WO2009040337A1 (fr) * 2007-09-27 2009-04-02 S.O.I.Tec Silicon On Insulator Technologies Procédé de fabrication d'une structure comportant un substrat et une couche deposée sur une de ses faces
EP2357660A1 (fr) * 2008-12-11 2011-08-17 Shin-Etsu Chemical Co., Ltd. Procédé de fabrication d un substrat composite sur lequel un semi-conducteur à large bande interdite est stratifié
EP2357660A4 (fr) * 2008-12-11 2012-06-20 Shinetsu Chemical Co Procédé de fabrication d un substrat composite sur lequel un semi-conducteur à large bande interdite est stratifié
US8546245B2 (en) 2008-12-11 2013-10-01 Shin-Etsu Chemical Co., Ltd. Method for manufacturing composite substrate comprising wide bandgap semiconductor layer
WO2013051163A1 (fr) * 2011-10-07 2013-04-11 住友電気工業株式会社 Procédé de fabrication de film de gan et substrat composite utilisé dans ledit procédé
CN103180494A (zh) * 2011-10-07 2013-06-26 住友电气工业株式会社 GaN基膜的制造方法及为此使用的复合衬底
US8962365B2 (en) 2011-10-07 2015-02-24 Sumitomo Electric Industies, Ltd. Method of manufacturing GaN-based film and composite substrate used therefor
EP4177645A1 (fr) * 2021-11-05 2023-05-10 Samsung Electronics Co., Ltd. Dispositif optique et son procédé de fabrication

Similar Documents

Publication Publication Date Title
JP5031365B2 (ja) エピタキシャル成長層の形成方法
US10658227B2 (en) Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
US10381261B2 (en) Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
JP5031364B2 (ja) エピタキシャル成長層の形成方法
US7538010B2 (en) Method of fabricating an epitaxially grown layer
US7902045B2 (en) Process for fabricating a structure for epitaxy without an exclusion zone
KR100352368B1 (ko) 반도체기판 및 이것의 제조방법
KR20080078679A (ko) 기판들의 제조 방법, 특히 광학, 전자공학 또는 광전자공학분야들에 대한, 및 상기 방법에 의해 구현되는 기판
JP6726180B2 (ja) 高抵抗率半導体・オン・インシュレータウエハおよび製造方法
JP2006148066A (ja) ゲルマニウム・オン・インシュレータ（ＧｅＯＩ）型ウェーハの製造方法
WO2018025166A1 (fr) Tranche de germes pour l'épaississement de gan par épitaxie en phase gazeuse ou liquide
WO2006082467A1 (fr) Substrat destine a la cristallogenese d'un semi-conducteur de nitrure
US8198628B2 (en) Doped substrate to be heated
EP1542275A1 (fr) Méthode d'amélioration de la qualité d'une structure hétérogène

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05708564

Country of ref document: EP

Kind code of ref document: A1

WWW Wipo information: withdrawn in national office

Ref document number: 5708564

Country of ref document: EP