FR2944914B1 - Procede de transfert d'au moins une couche micro-technologique - Google Patents
Procede de transfert d'au moins une couche micro-technologiqueInfo
- Publication number
- FR2944914B1 FR2944914B1 FR0952621A FR0952621A FR2944914B1 FR 2944914 B1 FR2944914 B1 FR 2944914B1 FR 0952621 A FR0952621 A FR 0952621A FR 0952621 A FR0952621 A FR 0952621A FR 2944914 B1 FR2944914 B1 FR 2944914B1
- Authority
- FR
- France
- Prior art keywords
- transferring
- micro
- technological layer
- technological
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0952621A FR2944914B1 (fr) | 2009-04-22 | 2009-04-22 | Procede de transfert d'au moins une couche micro-technologique |
EP10725226.4A EP2422365B1 (fr) | 2009-04-22 | 2010-04-21 | Procédé de transfert d'au moins une couche micro-technologique |
US13/271,401 US8546238B2 (en) | 2009-04-22 | 2011-10-12 | Method for transferring at least one micro-technological layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0952621A FR2944914B1 (fr) | 2009-04-22 | 2009-04-22 | Procede de transfert d'au moins une couche micro-technologique |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2944914A1 FR2944914A1 (fr) | 2010-10-29 |
FR2944914B1 true FR2944914B1 (fr) | 2011-05-20 |
Family
ID=41171055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0952621A Expired - Fee Related FR2944914B1 (fr) | 2009-04-22 | 2009-04-22 | Procede de transfert d'au moins une couche micro-technologique |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2944914B1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2977069B1 (fr) * | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
FR3055063B1 (fr) * | 2016-08-11 | 2018-08-31 | Soitec | Procede de transfert d'une couche utile |
CN113120857B (zh) * | 2021-04-14 | 2024-07-02 | 中国科学院上海微系统与信息技术研究所 | 一种光学微纳结构的制备方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003046993A1 (fr) * | 2001-11-29 | 2003-06-05 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes soi |
DE10223719C1 (de) * | 2002-05-28 | 2003-11-27 | Infineon Technologies Ag | Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung |
FR2855909B1 (fr) * | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
US20050082526A1 (en) * | 2003-10-15 | 2005-04-21 | International Business Machines Corporation | Techniques for layer transfer processing |
-
2009
- 2009-04-22 FR FR0952621A patent/FR2944914B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2944914A1 (fr) | 2010-10-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 7 |
|
ST | Notification of lapse |
Effective date: 20161230 |